From: Jonathan Cameron Jonathan.Cameron@huawei.com
[ Upstream commit b9ac08b3282a95fcefb057c2886028a6807725d8 ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Updated help text to 'may' require buffers to be in their own cacheline.
Fixes: 977724d20584 ("iio:dac:ti-dac7612: Add driver for Texas Instruments DAC7612") Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com Cc: Ricardo Ribalda ribalda@kernel.org Acked-by: Nuno Sá nuno.sa@analog.com Link: https://lore.kernel.org/r/20220508175712.647246-65-jic23@kernel.org Signed-off-by: Sasha Levin sashal@kernel.org --- drivers/iio/dac/ti-dac7612.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/dac/ti-dac7612.c b/drivers/iio/dac/ti-dac7612.c index 4c0f4b5e9ff4..8195815de26f 100644 --- a/drivers/iio/dac/ti-dac7612.c +++ b/drivers/iio/dac/ti-dac7612.c @@ -31,10 +31,10 @@ struct dac7612 { struct mutex lock;
/* - * DMA (thus cache coherency maintenance) requires the + * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. */ - uint8_t data[2] ____cacheline_aligned; + uint8_t data[2] __aligned(IIO_DMA_MINALIGN); };
static int dac7612_cmd_single(struct dac7612 *priv, int channel, u16 val)