On Fri, Jan 18, 2019 at 03:39:59PM +0200, Georgi Djakov wrote:
From: Loic Poulain loic.poulain@linaro.org
commit a89e7bcb18081c611eb6cf50edd440fa4983a71a upstream.
The Clock Data Recovery (CDR) circuit allows to automatically adjust the RX sampling-point/phase for high frequency cards (SDR104, HS200...). CDR is automatically enabled during DLL configuration. However, according to the APQ8016 reference manual, this function must be disabled during TX and tuning phase in order to prevent any interferences during tuning challenges and unexpected phase alteration during TX transfers.
This patch enables/disables CDR according to the current transfer mode.
This fixes sporadic write transfer issues observed with some SDR104 and HS200 cards.
Inspired by sdhci-msm downstream patch: https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/4...
Reported-by: Leonid Segal leonid.s@variscite.com Reported-by: Manabu Igusa migusa@arrowjapan.com Signed-off-by: Loic Poulain loic.poulain@linaro.org Acked-by: Adrian Hunter adrian.hunter@intel.com Acked-by: Georgi Djakov georgi.djakov@linaro.org Signed-off-by: Ulf Hansson ulf.hansson@linaro.org [georgi: backport to v4.14] Signed-off-by: Georgi Djakov georgi.djakov@linaro.org
Both patches now applied, thanks.
greg k-h