Hi,
On Fri, Sep 30, 2022 at 11:22 AM Krzysztof Kozlowski krzysztof.kozlowski@linaro.org wrote:
The pin configuration (done with generic pin controller helpers and as expressed by bindings) requires children nodes with either:
- "pins" property and the actual configuration,
- another set of nodes with above point.
The qup_spi2_default pin configuration used second method - with a "pinmux" child.
Fixes: 8d23a0040475 ("arm64: dts: qcom: db845c: add Low speed expansion i2c and spi nodes") Cc: stable@vger.kernel.org Signed-off-by: Krzysztof Kozlowski krzysztof.kozlowski@linaro.org
Not tested on hardware.
arch/arm64/boot/dts/qcom/sdm845-db845c.dts | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts index 132417e2d11e..a157eab66dee 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts +++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts @@ -1123,7 +1123,9 @@ &wifi {
/* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qup_spi2_default {
drive-strength = <16>;
pinmux {drive-strength = <16>;};
The convention on Qualcomm boards of this era is that muxing (setting the function) is done under a "pinmux" node and, unless some of the pins need to be treated differently like for the UARTs, configuration (bias, drive strength, etc) is done under a "pinconf" subnode. I believe that the "pinconf" subnode also needs to replicate the list of pins, or at least that's what we did everywhere else on sdm845 / sc7180.
Thus to match conventions, I assume you'd do:
&qup_spi2_default { pinconf { pins = "gpio27", "gpio28", "gpio29", "gpio30"; drive-strength = <16>; }; };
We've since moved away from this to a less cumbersome approach, but for "older" boards like db845c we should probably match the existing convention, or have a flag day and change all sdm845 boards over to the new convention.
-Doug