3.16.72-rc1 review patch. If anyone has any objections, please let me know.
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From: Jean-Francois Dagenais jeff.dagenais@gmail.com
commit 06003531502d06bc89d32528f6ec96bf978790f9 upstream.
When issuing the write DAC register and write eeprom command, the two powerdown bits (PD0 and PD1) are assumed by the chip to be present in the bytes sent. Leaving them at 0 implies "powerdown disabled" which is a different state that the current one. By adding the current state of the powerdown in the i2c write, the chip will correctly power-on exactly like as it is at the moment of store_eeprom call.
This is documented in MCP4725's datasheet, FIGURE 6-2: "Write Commands for DAC Input Register and EEPROM" and MCP4726's datasheet, FIGURE 6-3: "Write All Memory Command".
Signed-off-by: Jean-Francois Dagenais jeff.dagenais@gmail.com Acked-by: Peter Meerwald-Stadler pmeerw@pmeerw.net Signed-off-by: Jonathan Cameron Jonathan.Cameron@huawei.com [bwh: Backported to 3.16: adjust context] Signed-off-by: Ben Hutchings ben@decadent.org.uk --- drivers/iio/dac/mcp4725.c | 1 + 1 file changed, 1 insertion(+)
--- a/drivers/iio/dac/mcp4725.c +++ b/drivers/iio/dac/mcp4725.c @@ -86,6 +86,7 @@ static ssize_t mcp4725_store_eeprom(stru return 0;
inoutbuf[0] = 0x60; /* write EEPROM */ + inoutbuf[0] |= data->powerdown ? ((data->powerdown_mode + 1) << 1) : 0; inoutbuf[1] = data->dac_value >> 4; inoutbuf[2] = (data->dac_value & 0xf) << 4;