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-----Original Message----- From: Deucher, Alexander Sent: Wednesday, December 3, 2025 11:48 AM To: Koenig, Christian Christian.Koenig@amd.com; Greg Kroah-Hartman gregkh@linuxfoundation.org; stable@vger.kernel.org Cc: patches@lists.linux.dev; Liang, Prike Prike.Liang@amd.com Subject: RE: [PATCH 6.17 129/146] drm/amdgpu: attach tlb fence to the PTs update
-----Original Message----- From: Koenig, Christian Christian.Koenig@amd.com Sent: Wednesday, December 3, 2025 11:03 AM To: Greg Kroah-Hartman gregkh@linuxfoundation.org; stable@vger.kernel.org Cc: patches@lists.linux.dev; Liang, Prike Prike.Liang@amd.com; Deucher, Alexander Alexander.Deucher@amd.com Subject: Re: [PATCH 6.17 129/146] drm/amdgpu: attach tlb fence to the PTs update
Oh, wait a second, that one should clearly *not* be backported!
@Alex or do we have userqueue support working on 6.17? I don't think so.
Yes, userq support is available in 6.17. That said, this patch did end up causing a regression on SI parts. I've got a fix for that which will land soon.
After further investigation this patch and it's upcoming fix should only go to 6.17. Please drop from older stable kernels if it's been queued up on those.
Thanks,
Alex
Alex
Regards, Christian.
On 12/3/25 16:28, Greg Kroah-Hartman wrote:
6.17-stable review patch. If anyone has any objections, please let me
know.
From: Prike Liang Prike.Liang@amd.com
commit b4a7f4e7ad2b120a94f3111f92a11520052c762d upstream.
Ensure the userq TLB flush is emitted only after the VM update finishes and the PT BOs have been annotated with bookkeeping fences.
Suggested-by: Christian König christian.koenig@amd.com Signed-off-by: Prike Liang Prike.Liang@amd.com Reviewed-by: Christian König christian.koenig@amd.com Signed-off-by: Alex Deucher alexander.deucher@amd.com (cherry picked from commit f3854e04b708d73276c4488231a8bd66d30b4671) Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman gregkh@linuxfoundation.org
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1056,7 +1056,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_upd }
/* Prepare a TLB flush fence to be attached to PTs */
- if (!params->unlocked && vm->is_compute_context) {
if (!params->unlocked) { amdgpu_vm_tlb_fence_create(params->adev, vm, fence);
/* Makes sure no PD/PT is freed before the flush */