The recently submitted fix-commit revealed a problem in the iDMA 32-bit
platform code. Even though the controller supported only a single master
the dw_dma_acpi_filter() method hard-coded two master interfaces with IDs
0 and 1. As a result the sanity check implemented in the commit
b336268dde75 ("dmaengine: dw: Add peripheral bus width verification")
got incorrect interface data width and thus prevented the client drivers
from configuring the DMA-channel with the EINVAL error returned. E.g.,
the next error was printed for the PXA2xx SPI controller driver trying
to configure the requested channels:
> [ 164.525604] pxa2xx_spi_pci 0000:00:07.1: DMA slave config failed
> [ 164.536105] pxa2xx_spi_pci 0000:00:07.1: failed to get DMA TX descriptor
> [ 164.543213] spidev spi-SPT0001:00: SPI transfer failed: -16
The problem would have been spotted much earlier if the iDMA 32-bit
controller supported more than one master interfaces. But since it
supports just a single master and the iDMA 32-bit specific code just
ignores the master IDs in the CTLLO preparation method, the issue has
been gone unnoticed so far.
Fix the problem by specifying the default master ID for both memory
and peripheral devices in the driver data. Thus the issue noticed for
the iDMA 32-bit controllers will be eliminated and the ACPI-probed
DW DMA controllers will be configured with the correct master ID by
default.
Cc: stable(a)vger.kernel.org
Fixes: b336268dde75 ("dmaengine: dw: Add peripheral bus width verification")
Fixes: 199244d69458 ("dmaengine: dw: add support of iDMA 32-bit hardware")
Reported-by: Ferry Toth <fntoth(a)gmail.com>
Closes: https://lore.kernel.org/dmaengine/ZuXbCKUs1iOqFu51@black.fi.intel.com/
Reported-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com>
Closes: https://lore.kernel.org/dmaengine/ZuXgI-VcHpMgbZ91@black.fi.intel.com/
Tested-by: Ferry Toth <fntoth(a)gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com>
---
v5: rebranded to follow the compliances
Vinod, please apply this for v6.12-rcX as we have a problem to fix.
drivers/dma/dw/acpi.c | 6 ++++--
drivers/dma/dw/internal.h | 8 ++++++++
drivers/dma/dw/pci.c | 4 ++--
3 files changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/dw/acpi.c b/drivers/dma/dw/acpi.c
index c510c109d2c3..b6452fffa657 100644
--- a/drivers/dma/dw/acpi.c
+++ b/drivers/dma/dw/acpi.c
@@ -8,13 +8,15 @@
static bool dw_dma_acpi_filter(struct dma_chan *chan, void *param)
{
+ struct dw_dma *dw = to_dw_dma(chan->device);
+ struct dw_dma_chip_pdata *data = dev_get_drvdata(dw->dma.dev);
struct acpi_dma_spec *dma_spec = param;
struct dw_dma_slave slave = {
.dma_dev = dma_spec->dev,
.src_id = dma_spec->slave_id,
.dst_id = dma_spec->slave_id,
- .m_master = 0,
- .p_master = 1,
+ .m_master = data->m_master,
+ .p_master = data->p_master,
};
return dw_dma_filter(chan, &slave);
diff --git a/drivers/dma/dw/internal.h b/drivers/dma/dw/internal.h
index 563ce73488db..f1bd06a20cd6 100644
--- a/drivers/dma/dw/internal.h
+++ b/drivers/dma/dw/internal.h
@@ -51,11 +51,15 @@ struct dw_dma_chip_pdata {
int (*probe)(struct dw_dma_chip *chip);
int (*remove)(struct dw_dma_chip *chip);
struct dw_dma_chip *chip;
+ u8 m_master;
+ u8 p_master;
};
static __maybe_unused const struct dw_dma_chip_pdata dw_dma_chip_pdata = {
.probe = dw_dma_probe,
.remove = dw_dma_remove,
+ .m_master = 0,
+ .p_master = 1,
};
static const struct dw_dma_platform_data idma32_pdata = {
@@ -72,6 +76,8 @@ static __maybe_unused const struct dw_dma_chip_pdata idma32_chip_pdata = {
.pdata = &idma32_pdata,
.probe = idma32_dma_probe,
.remove = idma32_dma_remove,
+ .m_master = 0,
+ .p_master = 0,
};
static const struct dw_dma_platform_data xbar_pdata = {
@@ -88,6 +94,8 @@ static __maybe_unused const struct dw_dma_chip_pdata xbar_chip_pdata = {
.pdata = &xbar_pdata,
.probe = idma32_dma_probe,
.remove = idma32_dma_remove,
+ .m_master = 0,
+ .p_master = 0,
};
#endif /* _DMA_DW_INTERNAL_H */
diff --git a/drivers/dma/dw/pci.c b/drivers/dma/dw/pci.c
index ad2d4d012cf7..e8a0eb81726a 100644
--- a/drivers/dma/dw/pci.c
+++ b/drivers/dma/dw/pci.c
@@ -56,10 +56,10 @@ static int dw_pci_probe(struct pci_dev *pdev, const struct pci_device_id *pid)
if (ret)
return ret;
- dw_dma_acpi_controller_register(chip->dw);
-
pci_set_drvdata(pdev, data);
+ dw_dma_acpi_controller_register(chip->dw);
+
return 0;
}
--
2.43.0.rc1.1336.g36b5255a03ac
Due to some issues with hibernation on Lunar Lake (integrated), it was
decided to re-use the migration logic from Battle Mage (discrete).
However in 6.11 there were several patches missing to allow that to
work. A few patches were picked automatically for 6.11.10, but they are
not sufficient. Bring the additional patches and some tests to make
sure the backports work: this correspond to 20 of the patches here.
Others were additional fixes or dependencies.
This was tested on top of 6.11.10.
Akshata Jahagirdar (5):
drm/xe/migrate: Handle clear ccs logic for xe2 dgfx
drm/xe/migrate: Add helper function to program identity map
drm/xe/migrate: Add kunit to test clear functionality
drm/xe/xe2: Introduce identity map for compressed pat for vram
drm/xe/xe_migrate: Handle migration logic for xe2+ dgfx
Aradhya Bhatia (1):
drm/xe/xe2lpg: Extend Wa_15016589081 for xe2lpg
Chaitanya Kumar Borah (1):
drm/i915: Do not explicilty enable FEC in DP_TP_CTL for UHBR rates
Daniele Ceraolo Spurio (1):
drm/xe/uc: Use managed bo for HuC and GSC objects
Gustavo Sousa (2):
drm/xe/xe2: Extend performance tuning to media GT
drm/xe/xe2: Add performance tuning for L3 cache flushing
He Lugang (1):
drm/xe: use devm_add_action_or_reset() helper
Imre Deak (5):
drm/xe: Handle polling only for system s/r in
xe_display_pm_suspend/resume()
drm/i915/dp: Assume panel power is off if runtime suspended
drm/i915/dp: Disable unnecessary HPD polling for eDP
drm/xe/display: Separate the d3cold and non-d3cold runtime PM handling
drm/xe/display: Add missing HPD interrupt enabling during non-d3cold
RPM resume
Maarten Lankhorst (2):
drm/xe: Remove runtime argument from display s/r functions
drm/xe: Fix missing conversion to xe_display_pm_runtime_resume
Matthew Auld (3):
drm/xe/client: use mem_type from the current resource
drm/xe/queue: move xa_alloc to prevent UAF
drm/xe/bmg: improve cache flushing behaviour
Matthew Brost (1):
drm/xe: Do not run GPU page fault handler on a closed VM
Michal Wajdeczko (4):
drm/xe/kunit: Kill xe_cur_kunit()
drm/xe/kunit: Simplify xe_bo live tests code layout
drm/xe/kunit: Simplify xe_dma_buf live tests code layout
drm/xe/kunit: Simplify xe_migrate live tests code layout
Rodrigo Vivi (1):
drm/{i915, xe}: Avoid direct inspection of dpt_vma from outside dpt
Suraj Kandpal (2):
drm/xe/display: Do not suspend resume dp mst during runtime
drm/xe/display: Do not do intel_fbdev_set_suspend during runtime
Thomas Hellström (1):
drm/xe: Use separate rpm lockdep map for non-d3cold-capable devices
Vinod Govindapillai (1):
drm/xe/display: handle HPD polling in display runtime suspend/resume
drivers/gpu/drm/i915/display/intel_dp.c | 16 +-
drivers/gpu/drm/i915/display/intel_dpt.c | 4 +
drivers/gpu/drm/i915/display/intel_dpt.h | 3 +
.../drm/i915/display/skl_universal_plane.c | 3 +-
drivers/gpu/drm/i915/intel_runtime_pm.h | 8 +-
.../xe/compat-i915-headers/intel_runtime_pm.h | 8 +
drivers/gpu/drm/xe/display/xe_display.c | 78 ++++-
drivers/gpu/drm/xe/display/xe_display.h | 12 +-
drivers/gpu/drm/xe/display/xe_fb_pin.c | 9 +-
drivers/gpu/drm/xe/regs/xe_gt_regs.h | 12 +-
drivers/gpu/drm/xe/tests/Makefile | 3 -
drivers/gpu/drm/xe/tests/xe_bo.c | 24 +-
drivers/gpu/drm/xe/tests/xe_bo_test.c | 21 --
drivers/gpu/drm/xe/tests/xe_bo_test.h | 14 -
drivers/gpu/drm/xe/tests/xe_dma_buf.c | 20 +-
drivers/gpu/drm/xe/tests/xe_dma_buf_test.c | 20 --
drivers/gpu/drm/xe/tests/xe_dma_buf_test.h | 13 -
drivers/gpu/drm/xe/tests/xe_live_test_mod.c | 9 +
drivers/gpu/drm/xe/tests/xe_migrate.c | 299 +++++++++++++++++-
drivers/gpu/drm/xe/tests/xe_migrate_test.c | 20 --
drivers/gpu/drm/xe/tests/xe_migrate_test.h | 13 -
drivers/gpu/drm/xe/tests/xe_mocs.c | 8 +-
drivers/gpu/drm/xe/tests/xe_pci_test.c | 4 +-
drivers/gpu/drm/xe/tests/xe_test.h | 8 +-
drivers/gpu/drm/xe/xe_drm_client.c | 7 +-
drivers/gpu/drm/xe/xe_exec_queue.c | 4 +-
drivers/gpu/drm/xe/xe_gsc.c | 12 +-
drivers/gpu/drm/xe/xe_gsc_proxy.c | 36 +--
drivers/gpu/drm/xe/xe_gt.c | 1 -
drivers/gpu/drm/xe/xe_gt_freq.c | 4 +-
drivers/gpu/drm/xe/xe_gt_pagefault.c | 6 +
drivers/gpu/drm/xe/xe_gt_sysfs.c | 2 +-
drivers/gpu/drm/xe/xe_huc.c | 19 +-
drivers/gpu/drm/xe/xe_migrate.c | 185 +++++++----
drivers/gpu/drm/xe/xe_module.c | 9 +
drivers/gpu/drm/xe/xe_pm.c | 100 ++++--
drivers/gpu/drm/xe/xe_pm.h | 1 +
drivers/gpu/drm/xe/xe_tuning.c | 28 ++
drivers/gpu/drm/xe/xe_wa.c | 4 +
39 files changed, 735 insertions(+), 312 deletions(-)
delete mode 100644 drivers/gpu/drm/xe/tests/xe_bo_test.c
delete mode 100644 drivers/gpu/drm/xe/tests/xe_bo_test.h
delete mode 100644 drivers/gpu/drm/xe/tests/xe_dma_buf_test.c
delete mode 100644 drivers/gpu/drm/xe/tests/xe_dma_buf_test.h
delete mode 100644 drivers/gpu/drm/xe/tests/xe_migrate_test.c
delete mode 100644 drivers/gpu/drm/xe/tests/xe_migrate_test.h
--
2.47.0
On certain i.MX8 series parts [1], the PPS channel 0
is routed internally to eDMA, and the external PPS
pin is available on channel 1. In addition, on
certain boards, the PPS may be wired on the PCB to
an EVENTOUTn pin other than 0. On these systems
it is necessary that the PPS channel be able
to be configured from the Device Tree.
[1] https://lore.kernel.org/all/ZrPYOWA3FESx197L@lizhi-Precision-Tower-5810/
Changes in v2:
* add upstream hash (pick -x)
Francesco Dolcini (3):
dt-bindings: net: fec: add pps channel property
net: fec: refactor PPS channel configuration
net: fec: make PPS channel configurable
Documentation/devicetree/bindings/net/fsl,fec.yaml | 7 +++++++
drivers/net/ethernet/freescale/fec_ptp.c | 11 ++++++-----
2 files changed, 13 insertions(+), 5 deletions(-)
--
2.34.1
On certain i.MX8 series parts [1], the PPS channel 0
is routed internally to eDMA, and the external PPS
pin is available on channel 1. In addition, on
certain boards, the PPS may be wired on the PCB to
an EVENTOUTn pin other than 0. On these systems
it is necessary that the PPS channel be able
to be configured from the Device Tree.
[1] https://lore.kernel.org/all/ZrPYOWA3FESx197L@lizhi-Precision-Tower-5810/
Francesco Dolcini (3):
dt-bindings: net: fec: add pps channel property
net: fec: refactor PPS channel configuration
net: fec: make PPS channel configurable
Documentation/devicetree/bindings/net/fsl,fec.yaml | 7 +++++++
drivers/net/ethernet/freescale/fec_ptp.c | 11 ++++++-----
2 files changed, 13 insertions(+), 5 deletions(-)
--
2.34.1