November 2020 - Linux-stable-mirror

[merged] mm-memcg-link-page-counters-to-root-if-use_hierarchy-is-false.patch removed from -mm tree

by akpm＠linux-foundation.org

The patch titled Subject: mm: memcg: link page counters to root if use_hierarchy is false has been removed from the -mm tree. Its filename was mm-memcg-link-page-counters-to-root-if-use_hierarchy-is-false.patch This patch was dropped because it was merged into mainline or a subsystem tree ------------------------------------------------------ From: Roman Gushchin <guro(a)fb.com> Subject: mm: memcg: link page counters to root if use_hierarchy is false Richard reported a warning which can be reproduced by running the LTP madvise6 test (cgroup v1 in the non-hierarchical mode should be used): [ 9.841552] ------------[ cut here ]------------ [ 9.841788] WARNING: CPU: 0 PID: 12 at mm/page_counter.c:57 page_counter_uncharge (mm/page_counter.c:57 mm/page_counter.c:50 mm/page_counter.c:156) [ 9.841982] Modules linked in: [ 9.842072] CPU: 0 PID: 12 Comm: kworker/0:1 Not tainted 5.9.0-rc7-22-default #77 [ 9.842266] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS rel-1.13.0-48-gd9c812d-rebuilt.opensuse.org 04/01/2014 [ 9.842571] Workqueue: events drain_local_stock [ 9.842750] RIP: 0010:page_counter_uncharge (mm/page_counter.c:57 mm/page_counter.c:50 mm/page_counter.c:156) [ 9.842894] Code: 0f c1 45 00 4c 29 e0 48 89 ef 48 89 c3 48 89 c6 e8 2a fe ff ff 48 85 db 78 10 48 8b 6d 28 48 85 ed 75 d8 5b 5d 41 5c 41 5d c3 <0f> 0b eb ec 90 e8 4b f9 88 2a 48 8b 17 48 39 d6 72 41 41 54 49 89 [ 9.843438] RSP: 0018:ffffb1c18006be28 EFLAGS: 00010086 [ 9.843585] RAX: ffffffffffffffff RBX: ffffffffffffffff RCX: ffff94803bc2cae0 [ 9.843806] RDX: 0000000000000001 RSI: ffffffffffffffff RDI: ffff948007d2b248 [ 9.844026] RBP: ffff948007d2b248 R08: ffff948007c58eb0 R09: ffff948007da05ac [ 9.844248] R10: 0000000000000018 R11: 0000000000000018 R12: 0000000000000001 [ 9.844477] R13: ffffffffffffffff R14: 0000000000000000 R15: ffff94803bc2cac0 [ 9.844696] FS: 0000000000000000(0000) GS:ffff94803bc00000(0000) knlGS:0000000000000000 [ 9.844915] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 9.845096] CR2: 00007f0579ee0384 CR3: 000000002cc0a000 CR4: 00000000000006f0 [ 9.845319] Call Trace: [ 9.845429] __memcg_kmem_uncharge (mm/memcontrol.c:3022) [ 9.845582] drain_obj_stock (./include/linux/rcupdate.h:689 mm/memcontrol.c:3114) [ 9.845684] drain_local_stock (mm/memcontrol.c:2255) [ 9.845789] process_one_work (./arch/x86/include/asm/jump_label.h:25 ./include/linux/jump_label.h:200 ./include/trace/events/workqueue.h:108 kernel/workqueue.c:2274) [ 9.845898] worker_thread (./include/linux/list.h:282 kernel/workqueue.c:2416) [ 9.846034] ? process_one_work (kernel/workqueue.c:2358) [ 9.846162] kthread (kernel/kthread.c:292) [ 9.846271] ? __kthread_bind_mask (kernel/kthread.c:245) [ 9.846420] ret_from_fork (arch/x86/entry/entry_64.S:300) [ 9.846531] ---[ end trace 8b5647c1eba9d18a ]--- The problem occurs because in the non-hierarchical mode non-root page counters are not linked to root page counters, so the charge is not propagated to the root memory cgroup. After the removal of the original memory cgroup and reparenting of the object cgroup, the root cgroup might be uncharged by draining a objcg stock, for example. It leads to an eventual underflow of the charge and triggers a warning. Fix it by linking all page counters to corresponding root page counters in the non-hierarchical mode. Please note, that in the non-hierarchical mode all objcgs are always reparented to the root memory cgroup, even if the hierarchy has more than 1 level. This patch doesn't change it. The patch also doesn't affect how the hierarchical mode is working, which is the only sane and truly supported mode now. Thanks to Richard for reporting, debugging and providing an alternative version of the fix! Link: https://lkml.kernel.org/r/20201026231326.3212225-1-guro@fb.com Fixes: bf4f059954dc ("mm: memcg/slab: obj_cgroup API") Signed-off-by: Roman Gushchin <guro(a)fb.com> Debugged-by: Richard Palethorpe <rpalethorpe(a)suse.com> Reported-by: <ltp(a)lists.linux.it> Reviewed-by: Shakeel Butt <shakeelb(a)google.com> Acked-by: Johannes Weiner <hannes(a)cmpxchg.org> Reviewed-by: Michal Koutný <mkoutny(a)suse.com> Cc: Michal Hocko <mhocko(a)kernel.org> Cc: <stable(a)vger.kernel.org> Signed-off-by: Andrew Morton <akpm(a)linux-foundation.org> --- mm/memcontrol.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) --- a/mm/memcontrol.c~mm-memcg-link-page-counters-to-root-if-use_hierarchy-is-false +++ a/mm/memcontrol.c @@ -5345,17 +5345,22 @@ mem_cgroup_css_alloc(struct cgroup_subsy memcg->swappiness = mem_cgroup_swappiness(parent); memcg->oom_kill_disable = parent->oom_kill_disable; } - if (parent && parent->use_hierarchy) { + if (!parent) { + page_counter_init(&memcg->memory, NULL); + page_counter_init(&memcg->swap, NULL); + page_counter_init(&memcg->kmem, NULL); + page_counter_init(&memcg->tcpmem, NULL); + } else if (parent->use_hierarchy) { memcg->use_hierarchy = true; page_counter_init(&memcg->memory, &parent->memory); page_counter_init(&memcg->swap, &parent->swap); page_counter_init(&memcg->kmem, &parent->kmem); page_counter_init(&memcg->tcpmem, &parent->tcpmem); } else { - page_counter_init(&memcg->memory, NULL); - page_counter_init(&memcg->swap, NULL); - page_counter_init(&memcg->kmem, NULL); - page_counter_init(&memcg->tcpmem, NULL); + page_counter_init(&memcg->memory, &root_mem_cgroup->memory); + page_counter_init(&memcg->swap, &root_mem_cgroup->swap); + page_counter_init(&memcg->kmem, &root_mem_cgroup->kmem); + page_counter_init(&memcg->tcpmem, &root_mem_cgroup->tcpmem); /* * Deeper hierachy with use_hierarchy == false doesn't make * much sense so let cgroup subsystem know about this _ Patches currently in -mm which might be from guro(a)fb.com are mm-memcontrol-use-helpers-to-read-pages-memcg-data.patch mm-memcontrol-slab-use-helpers-to-access-slab-pages-memcg_data.patch mm-introduce-page-memcg-flags.patch mm-convert-page-kmemcg-type-to-a-page-memcg-flag.patch mm-vmstat-fix-proc-sys-vm-stat_refresh-generating-false-warnings.patch mm-vmstat-fix-proc-sys-vm-stat_refresh-generating-false-warnings-fix.patch

4 years, 6 months

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[merged] hugetlb_cgroup-fix-reservation-accounting.patch removed from -mm tree

by akpm＠linux-foundation.org

The patch titled Subject: hugetlb_cgroup: fix reservation accounting has been removed from the -mm tree. Its filename was hugetlb_cgroup-fix-reservation-accounting.patch This patch was dropped because it was merged into mainline or a subsystem tree ------------------------------------------------------ From: Mike Kravetz <mike.kravetz(a)oracle.com> Subject: hugetlb_cgroup: fix reservation accounting Michal Privoznik was using "free page reporting" in QEMU/virtio-balloon with hugetlbfs and hit the warning below. QEMU with free page hinting uses fallocate(FALLOC_FL_PUNCH_HOLE) to discard pages that are reported as free by a VM. The reporting granularity is in pageblock granularity. So when the guest reports 2M chunks, we fallocate(FALLOC_FL_PUNCH_HOLE) one huge page in QEMU. [ 315.251417] ------------[ cut here ]------------ [ 315.251424] WARNING: CPU: 7 PID: 6636 at mm/page_counter.c:57 page_counter_uncharge+0x4b/0x50 [ 315.251425] Modules linked in: ... [ 315.251466] CPU: 7 PID: 6636 Comm: qemu-system-x86 Not tainted 5.9.0 #137 [ 315.251467] Hardware name: Gigabyte Technology Co., Ltd. X570 AORUS PRO/X570 AORUS PRO, BIOS F21 07/31/2020 [ 315.251469] RIP: 0010:page_counter_uncharge+0x4b/0x50 ... [ 315.251479] Call Trace: [ 315.251485] hugetlb_cgroup_uncharge_file_region+0x4b/0x80 [ 315.251487] region_del+0x1d3/0x300 [ 315.251489] hugetlb_unreserve_pages+0x39/0xb0 [ 315.251492] remove_inode_hugepages+0x1a8/0x3d0 [ 315.251495] ? tlb_finish_mmu+0x7a/0x1d0 [ 315.251497] hugetlbfs_fallocate+0x3c4/0x5c0 [ 315.251519] ? kvm_arch_vcpu_ioctl_run+0x614/0x1700 [kvm] [ 315.251522] ? file_has_perm+0xa2/0xb0 [ 315.251524] ? inode_security+0xc/0x60 [ 315.251525] ? selinux_file_permission+0x4e/0x120 [ 315.251527] vfs_fallocate+0x146/0x290 [ 315.251529] __x64_sys_fallocate+0x3e/0x70 [ 315.251531] do_syscall_64+0x33/0x40 [ 315.251533] entry_SYSCALL_64_after_hwframe+0x44/0xa9 ... [ 315.251542] ---[ end trace 4c88c62ccb1349c9 ]--- Investigation of the issue uncovered bugs in hugetlb cgroup reservation accounting. This patch addresses the found issues. Link: https://lkml.kernel.org/r/20201021204426.36069-1-mike.kravetz@oracle.com Fixes: 075a61d07a8e ("hugetlb_cgroup: add accounting for shared mappings") Cc: <stable(a)vger.kernel.org> Reported-by: Michal Privoznik <mprivozn(a)redhat.com> Co-developed-by: David Hildenbrand <david(a)redhat.com> Signed-off-by: David Hildenbrand <david(a)redhat.com> Signed-off-by: Mike Kravetz <mike.kravetz(a)oracle.com> Tested-by: Michal Privoznik <mprivozn(a)redhat.com> Acked-by: Michael S. Tsirkin <mst(a)redhat.com> Reviewed-by: Mina Almasry <almasrymina(a)google.com> Cc: David Hildenbrand <david(a)redhat.com> Cc: Michal Hocko <mhocko(a)kernel.org> Cc: Muchun Song <songmuchun(a)bytedance.com> Cc: "Aneesh Kumar K . V" <aneesh.kumar(a)linux.vnet.ibm.com> Cc: Tejun Heo <tj(a)kernel.org> Cc: <stable(a)vger.kernel.org> Signed-off-by: Andrew Morton <akpm(a)linux-foundation.org> --- mm/hugetlb.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) --- a/mm/hugetlb.c~hugetlb_cgroup-fix-reservation-accounting +++ a/mm/hugetlb.c @@ -648,6 +648,8 @@ retry: } del += t - f; + hugetlb_cgroup_uncharge_file_region( + resv, rg, t - f); /* New entry for end of split region */ nrg->from = t; @@ -660,9 +662,6 @@ retry: /* Original entry is trimmed */ rg->to = f; - hugetlb_cgroup_uncharge_file_region( - resv, rg, nrg->to - nrg->from); - list_add(&nrg->link, &rg->link); nrg = NULL; break; @@ -678,17 +677,17 @@ retry: } if (f <= rg->from) { /* Trim beginning of region */ - del += t - rg->from; - rg->from = t; - hugetlb_cgroup_uncharge_file_region(resv, rg, t - rg->from); - } else { /* Trim end of region */ - del += rg->to - f; - rg->to = f; + del += t - rg->from; + rg->from = t; + } else { /* Trim end of region */ hugetlb_cgroup_uncharge_file_region(resv, rg, rg->to - f); + + del += rg->to - f; + rg->to = f; } } @@ -2443,6 +2442,9 @@ struct page *alloc_huge_page(struct vm_a rsv_adjust = hugepage_subpool_put_pages(spool, 1); hugetlb_acct_memory(h, -rsv_adjust); + if (deferred_reserve) + hugetlb_cgroup_uncharge_page_rsvd(hstate_index(h), + pages_per_huge_page(h), page); } return page; _ Patches currently in -mm which might be from mike.kravetz(a)oracle.com are

4 years, 6 months

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[PATCH 1/8] of: fix linker-section match-table corruption

by Johan Hovold

Specify type alignment when declaring linker-section match-table entries to prevent gcc from increasing alignment and corrupting the various tables with padding (e.g. timers, irqchips, clocks, reserved memory). This is specifically needed on x86 where gcc (typically) aligns larger objects like struct of_device_id with static extent on 32-byte boundaries which at best prevents matching on anything but the first entry. Here's a 64-bit example where all entries are corrupt as 16 bytes of padding has been inserted before the first entry: ffffffff8266b4b0 D __clk_of_table ffffffff8266b4c0 d __of_table_fixed_factor_clk ffffffff8266b5a0 d __of_table_fixed_clk ffffffff8266b680 d __clk_of_table_sentinel And here's a 32-bit example where the 8-byte-aligned table happens to be placed on a 32-byte boundary so that all but the first entry are corrupt due to the 28 bytes of padding inserted between entries: 812b3ec0 D __irqchip_of_table 812b3ec0 d __of_table_irqchip1 812b3fa0 d __of_table_irqchip2 812b4080 d __of_table_irqchip3 812b4160 d irqchip_of_match_end Verified on x86 using gcc-9.3 and gcc-4.9 (which uses 64-byte alignment), and on arm using gcc-7.2. Note that there are no in-tree users of these tables on x86 currently (even if they are included in the image). Fixes: 54196ccbe0ba ("of: consolidate linker section OF match table declarations") Fixes: f6e916b82022 ("irqchip: add basic infrastructure") Cc: stable <stable(a)vger.kernel.org> # 3.9 Signed-off-by: Johan Hovold <johan(a)kernel.org> --- include/linux/of.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/of.h b/include/linux/of.h index 5d51891cbf1a..af655d264f10 100644 --- a/include/linux/of.h +++ b/include/linux/of.h @@ -1300,6 +1300,7 @@ static inline int of_get_available_child_count(const struct device_node *np) #define _OF_DECLARE(table, name, compat, fn, fn_type) \ static const struct of_device_id __of_table_##name \ __used __section("__" #table "_of_table") \ + __aligned(__alignof__(struct of_device_id)) \ = { .compatible = compat, \ .data = (fn == (fn_type)NULL) ? fn : fn } #else -- 2.26.2

4 years, 6 months

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stable-rc/queue/4.4 baseline: 132 runs, 5 regressions (v4.4.241-41-g583b80963b82)

by kernelci.org bot

stable-rc/queue/4.4 baseline: 132 runs, 5 regressions (v4.4.241-41-g583b80963b82) Regressions Summary ------------------- platform | arch | lab | compiler | defconfig | regressions -----------------+--------+---------------+----------+---------------------+------------ beagle-xm | arm | lab-baylibre | gcc-8 | omap2plus_defconfig | 2 panda | arm | lab-collabora | gcc-8 | omap2plus_defconfig | 1 qemu_i386-uefi | i386 | lab-collabora | gcc-8 | i386_defconfig | 1 qemu_x86_64-uefi | x86_64 | lab-baylibre | gcc-8 | x86_64_defconfig | 1 Details: https://kernelci.org/test/job/stable-rc/branch/queue%2F4.4/kernel/v4.4.241-… Test: baseline Tree: stable-rc Branch: queue/4.4 Describe: v4.4.241-41-g583b80963b82 URL: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git SHA: 583b80963b822c557b0ef90686b21bfad1de1afa Test Regressions ---------------- platform | arch | lab | compiler | defconfig | regressions -----------------+--------+---------------+----------+---------------------+------------ beagle-xm | arm | lab-baylibre | gcc-8 | omap2plus_defconfig | 2 Details: https://kernelci.org/test/plan/id/5fa15523e78717f60e3fe7db Results: 2 PASS, 2 FAIL, 1 SKIP Full config: omap2plus_defconfig Compiler: gcc-8 (arm-linux-gnueabihf-gcc (Debian 8.3.0-2) 8.3.0) Plain log: https://storage.kernelci.org//stable-rc/queue-4.4/v4.4.241-41-g583b80963b82… HTML log: https://storage.kernelci.org//stable-rc/queue-4.4/v4.4.241-41-g583b80963b82… Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05-4-g97706c5d… * baseline.dmesg.crit: https://kernelci.org/test/case/id/5fa15523e78717f60e3fe7e0 new failure (last pass: v4.4.241-35-g00e1b9176297) 1 lines 2020-11-03 13:01:40.956000+00:00 Connected to omap3-beagle-xm console [channel connected] (~$quit to exit) 2020-11-03 13:01:40.956000+00:00 (user:khilman) is already connected 2020-11-03 13:01:52.107000+00:00 2020-11-03 13:01:52.113000+00:00 U-Boot SPL 2018.09-rc2-00001-ge6aa9785acb2 (Aug 15 2018 - 09:41:52 -0700) 2020-11-03 13:01:52.117000+00:00 Trying to boot from MMC1 2020-11-03 13:01:52.307000+00:00 spl_load_image_fat_os: error reading image args, err - -2 2020-11-03 13:01:52.858000+00:00 2020-11-03 13:01:52.864000+00:00 U-Boot SPL 2018.09-rc2-00001-ge6aa9785acb2 (Aug 15 2018 - 09:41:52 -0700) 2020-11-03 13:01:52.868000+00:00 Trying to boot from MMC1 2020-11-03 13:01:53.058000+00:00 spl_load_image_fat_os: error reading image args, err - -2 ... (451 line(s) more) * baseline.dmesg.emerg: https://kernelci.org/test/case/id/5fa15523e78717f60e3fe7e2 new failure (last pass: v4.4.241-35-g00e1b9176297) 28 lines 2020-11-03 13:03:27.287000+00:00 kern :emerg : Stack: (0xcba11d10 to 0xcba12000) 2020-11-03 13:03:27.295000+00:00 kern :emerg : 1d00: bf02b8fc bf010b84 cb98f410 bf02b988 2020-11-03 13:03:27.304000+00:00 kern :emerg : 1d20: cb98f410 bf2010a8 00000002 cb98b010 cb98f410 bf24fb54 cbbca390 cbbca390 2020-11-03 13:03:27.312000+00:00 kern :emerg : 1d40: 00000000 00000000 ce226930 c01fb3d8 ce226930 ce226930 c0857e88 00000001 2020-11-03 13:03:27.320000+00:00 kern :emerg : 1d60: ce226930 cbbca390 cbbca450 00000000 ce226930 c0857e88 00000001 c09612c0 2020-11-03 13:03:27.328000+00:00 kern :emerg : 1d80: ffffffed bf253ff4 fffffdfb 00000028 00000001 c00ce2f4 bf254188 c04070e8 2020-11-03 13:03:27.336000+00:00 kern :emerg : 1da0: c09612c0 c120da30 bf253ff4 00000000 00000028 c04055bc c09612c0 c09612f4 2020-11-03 13:03:27.344000+00:00 kern :emerg : 1dc0: bf253ff4 00000000 00000000 c0405764 00000000 bf253ff4 c04056d8 c0403a88 2020-11-03 13:03:27.353000+00:00 kern :emerg : 1de0: ce0c38a4 ce220910 bf253ff4 cbcda4c0 c09dd3a8 c0404bd4 bf252b6c c095e460 2020-11-03 13:03:27.361000+00:00 kern :emerg : 1e00: cbca6b00 bf253ff4 c095e460 cbca6b00 bf257000 c040619c c095e460 c095e460 ... (16 line(s) more) platform | arch | lab | compiler | defconfig | regressions -----------------+--------+---------------+----------+---------------------+------------ panda | arm | lab-collabora | gcc-8 | omap2plus_defconfig | 1 Details: https://kernelci.org/test/plan/id/5fa1550c01a57c010c3fe7d6 Results: 3 PASS, 1 FAIL, 1 SKIP Full config: omap2plus_defconfig Compiler: gcc-8 (arm-linux-gnueabihf-gcc (Debian 8.3.0-2) 8.3.0) Plain log: https://storage.kernelci.org//stable-rc/queue-4.4/v4.4.241-41-g583b80963b82… HTML log: https://storage.kernelci.org//stable-rc/queue-4.4/v4.4.241-41-g583b80963b82… Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05-4-g97706c5d… * baseline.dmesg.emerg: https://kernelci.org/test/case/id/5fa1550c01a57c010c3fe7dd failing since 2 days (last pass: v4.4.241-8-gd71fd6297abd, first fail: v4.4.241-10-g5dfc3f093ca4) 2 lines platform | arch | lab | compiler | defconfig | regressions -----------------+--------+---------------+----------+---------------------+------------ qemu_i386-uefi | i386 | lab-collabora | gcc-8 | i386_defconfig | 1 Details: https://kernelci.org/test/plan/id/5fa1548e51b6bc655b3fe844 Results: 0 PASS, 1 FAIL, 0 SKIP Full config: i386_defconfig Compiler: gcc-8 (gcc (Debian 8.3.0-6) 8.3.0) Plain log: https://storage.kernelci.org//stable-rc/queue-4.4/v4.4.241-41-g583b80963b82… HTML log: https://storage.kernelci.org//stable-rc/queue-4.4/v4.4.241-41-g583b80963b82… Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05-4-g97706c5d… * baseline.login: https://kernelci.org/test/case/id/5fa1548e51b6bc655b3fe845 new failure (last pass: v4.4.241-35-g00e1b9176297) platform | arch | lab | compiler | defconfig | regressions -----------------+--------+---------------+----------+---------------------+------------ qemu_x86_64-uefi | x86_64 | lab-baylibre | gcc-8 | x86_64_defconfig | 1 Details: https://kernelci.org/test/plan/id/5fa154591e37ec2a643fe7ff Results: 0 PASS, 1 FAIL, 0 SKIP Full config: x86_64_defconfig Compiler: gcc-8 (gcc (Debian 8.3.0-6) 8.3.0) Plain log: https://storage.kernelci.org//stable-rc/queue-4.4/v4.4.241-41-g583b80963b82… HTML log: https://storage.kernelci.org//stable-rc/queue-4.4/v4.4.241-41-g583b80963b82… Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05-4-g97706c5d… * baseline.login: https://kernelci.org/test/case/id/5fa154591e37ec2a643fe800 new failure (last pass: v4.4.241-35-g00e1b9176297)

4 years, 6 months

1
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[PATCH v2 00/14] Backport of patch series for stable 4.19 branch

by Juergen Gross

V2: correct patch 2 Juergen Gross (14): xen/events: don't use chip_data for legacy IRQs xen/events: avoid removing an event channel while handling it xen/events: add a proper barrier to 2-level uevent unmasking xen/events: fix race in evtchn_fifo_unmask() xen/events: add a new "late EOI" evtchn framework xen/blkback: use lateeoi irq binding xen/netback: use lateeoi irq binding xen/scsiback: use lateeoi irq binding xen/pvcallsback: use lateeoi irq binding xen/pciback: use lateeoi irq binding xen/events: switch user event channels to lateeoi model xen/events: use a common cpu hotplug hook for event channels xen/events: defer eoi in case of excessive number of events xen/events: block rogue events for some time .../admin-guide/kernel-parameters.txt | 8 + drivers/block/xen-blkback/blkback.c | 22 +- drivers/block/xen-blkback/xenbus.c | 5 +- drivers/net/xen-netback/common.h | 15 + drivers/net/xen-netback/interface.c | 61 ++- drivers/net/xen-netback/netback.c | 11 +- drivers/net/xen-netback/rx.c | 13 +- drivers/xen/events/events_2l.c | 9 +- drivers/xen/events/events_base.c | 451 ++++++++++++++++-- drivers/xen/events/events_fifo.c | 83 ++-- drivers/xen/events/events_internal.h | 20 +- drivers/xen/evtchn.c | 7 +- drivers/xen/pvcalls-back.c | 76 +-- drivers/xen/xen-pciback/pci_stub.c | 14 +- drivers/xen/xen-pciback/pciback.h | 12 +- drivers/xen/xen-pciback/pciback_ops.c | 48 +- drivers/xen/xen-pciback/xenbus.c | 2 +- drivers/xen/xen-scsiback.c | 23 +- include/xen/events.h | 29 +- 19 files changed, 731 insertions(+), 178 deletions(-) -- 2.26.2

4 years, 6 months

2
15
0 0

[PATCH v2 00/13] Backport of patch series for stable 5.4 branch

by Juergen Gross

V2: correct first patch Juergen Gross (13): xen/events: avoid removing an event channel while handling it xen/events: add a proper barrier to 2-level uevent unmasking xen/events: fix race in evtchn_fifo_unmask() xen/events: add a new "late EOI" evtchn framework xen/blkback: use lateeoi irq binding xen/netback: use lateeoi irq binding xen/scsiback: use lateeoi irq binding xen/pvcallsback: use lateeoi irq binding xen/pciback: use lateeoi irq binding xen/events: switch user event channels to lateeoi model xen/events: use a common cpu hotplug hook for event channels xen/events: defer eoi in case of excessive number of events xen/events: block rogue events for some time .../admin-guide/kernel-parameters.txt | 8 + drivers/block/xen-blkback/blkback.c | 22 +- drivers/block/xen-blkback/xenbus.c | 5 +- drivers/net/xen-netback/common.h | 15 + drivers/net/xen-netback/interface.c | 61 ++- drivers/net/xen-netback/netback.c | 11 +- drivers/net/xen-netback/rx.c | 13 +- drivers/xen/events/events_2l.c | 9 +- drivers/xen/events/events_base.c | 422 ++++++++++++++++-- drivers/xen/events/events_fifo.c | 83 ++-- drivers/xen/events/events_internal.h | 20 +- drivers/xen/evtchn.c | 7 +- drivers/xen/pvcalls-back.c | 76 ++-- drivers/xen/xen-pciback/pci_stub.c | 14 +- drivers/xen/xen-pciback/pciback.h | 12 +- drivers/xen/xen-pciback/pciback_ops.c | 48 +- drivers/xen/xen-pciback/xenbus.c | 2 +- drivers/xen/xen-scsiback.c | 23 +- include/xen/events.h | 29 +- 19 files changed, 710 insertions(+), 170 deletions(-) -- 2.26.2

4 years, 6 months

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stable-rc/queue/4.9 baseline: 150 runs, 3 regressions (v4.9.241-47-gd40a052345b6)

by kernelci.org bot

stable-rc/queue/4.9 baseline: 150 runs, 3 regressions (v4.9.241-47-gd40a052345b6) Regressions Summary ------------------- platform | arch | lab | compiler | defconfig | regressions ----------------------+------+---------------+----------+---------------------+------------ at91-sama5d4_xplained | arm | lab-baylibre | gcc-8 | sama5_defconfig | 1 beagle-xm | arm | lab-baylibre | gcc-8 | multi_v7_defconfig | 1 panda | arm | lab-collabora | gcc-8 | omap2plus_defconfig | 1 Details: https://kernelci.org/test/job/stable-rc/branch/queue%2F4.9/kernel/v4.9.241-… Test: baseline Tree: stable-rc Branch: queue/4.9 Describe: v4.9.241-47-gd40a052345b6 URL: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git SHA: d40a052345b6f1081e1e50f3fdd9b46f709e6f32 Test Regressions ---------------- platform | arch | lab | compiler | defconfig | regressions ----------------------+------+---------------+----------+---------------------+------------ at91-sama5d4_xplained | arm | lab-baylibre | gcc-8 | sama5_defconfig | 1 Details: https://kernelci.org/test/plan/id/5fa148a8b7494722c43fe7df Results: 0 PASS, 1 FAIL, 0 SKIP Full config: sama5_defconfig Compiler: gcc-8 (arm-linux-gnueabihf-gcc (Debian 8.3.0-2) 8.3.0) Plain log: https://storage.kernelci.org//stable-rc/queue-4.9/v4.9.241-47-gd40a052345b6… HTML log: https://storage.kernelci.org//stable-rc/queue-4.9/v4.9.241-47-gd40a052345b6… Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05-4-g97706c5d… * baseline.login: https://kernelci.org/test/case/id/5fa148a8b7494722c43fe7e0 failing since 5 days (last pass: v4.9.240-139-gd719c4ad8056, first fail: v4.9.240-139-g65bd9a74252c) platform | arch | lab | compiler | defconfig | regressions ----------------------+------+---------------+----------+---------------------+------------ beagle-xm | arm | lab-baylibre | gcc-8 | multi_v7_defconfig | 1 Details: https://kernelci.org/test/plan/id/5fa14b2235c4b87c813fe7d8 Results: 0 PASS, 1 FAIL, 0 SKIP Full config: multi_v7_defconfig Compiler: gcc-8 (arm-linux-gnueabihf-gcc (Debian 8.3.0-2) 8.3.0) Plain log: https://storage.kernelci.org//stable-rc/queue-4.9/v4.9.241-47-gd40a052345b6… HTML log: https://storage.kernelci.org//stable-rc/queue-4.9/v4.9.241-47-gd40a052345b6… Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05-4-g97706c5d… * baseline.login: https://kernelci.org/test/case/id/5fa14b2235c4b87c813fe7d9 new failure (last pass: v4.9.241-44-g29192a9a3096) platform | arch | lab | compiler | defconfig | regressions ----------------------+------+---------------+----------+---------------------+------------ panda | arm | lab-collabora | gcc-8 | omap2plus_defconfig | 1 Details: https://kernelci.org/test/plan/id/5fa149c779f169bb913fe7ec Results: 3 PASS, 1 FAIL, 1 SKIP Full config: omap2plus_defconfig Compiler: gcc-8 (arm-linux-gnueabihf-gcc (Debian 8.3.0-2) 8.3.0) Plain log: https://storage.kernelci.org//stable-rc/queue-4.9/v4.9.241-47-gd40a052345b6… HTML log: https://storage.kernelci.org//stable-rc/queue-4.9/v4.9.241-47-gd40a052345b6… Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/kci-2020.05-4-g97706c5d… * baseline.dmesg.emerg: https://kernelci.org/test/case/id/5fa149c779f169bb913fe7f3 new failure (last pass: v4.9.241-44-g29192a9a3096) 2 lines

4 years, 6 months

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FAILED: patch "[PATCH] memory: brcmstb: Add driver for DPFE" failed to apply to 4.19-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 4.19-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 2f330caff5776239abb3e0337533886dbb21f6df Mon Sep 17 00:00:00 2001 From: Markus Mayer <mmayer(a)broadcom.com> Date: Thu, 24 Aug 2017 16:36:26 -0700 Subject: [PATCH] memory: brcmstb: Add driver for DPFE This driver allows access to DRAM properties, such as the refresh rate, via the Broadcom STB DDR PHY Front End (DPFE). The refresh rate can be used as indirect indicator of the DRAM temperature. The driver also allows setting of the sampling interval. Signed-off-by: Markus Mayer <mmayer(a)broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli(a)gmail.com> diff --git a/MAINTAINERS b/MAINTAINERS index 2281af4b41b6..43ed9eb98c43 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2963,6 +2963,14 @@ L: bcm-kernel-feedback-list(a)broadcom.com S: Maintained F: drivers/mtd/nand/brcmnand/ +BROADCOM STB DPFE DRIVER +M: Markus Mayer <mmayer(a)broadcom.com> +M: bcm-kernel-feedback-list(a)broadcom.com +L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt +F: drivers/memory/brcmstb_dpfe.c + BROADCOM SYSTEMPORT ETHERNET DRIVER M: Florian Fainelli <f.fainelli(a)gmail.com> L: netdev(a)vger.kernel.org diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index e88097fbc085..9cb8b61ee5cc 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -8,6 +8,7 @@ endif obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o +obj-$(CONFIG_ARCH_BRCMSTB) += brcmstb_dpfe.o obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o obj-$(CONFIG_OMAP_GPMC) += omap-gpmc.o diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c new file mode 100644 index 000000000000..21242c401af5 --- /dev/null +++ b/drivers/memory/brcmstb_dpfe.c @@ -0,0 +1,701 @@ +/* + * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs + * + * Copyright (c) 2017 Broadcom + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +/* + * This driver provides access to the DPFE interface of Broadcom STB SoCs. + * The firmware running on the DCPU inside the DDR PHY can provide current + * information about the system's RAM, for instance the DRAM refresh rate. + * This can be used as an indirect indicator for the DRAM's temperature. + * Slower refresh rate means cooler RAM, higher refresh rate means hotter + * RAM. + * + * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which + * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls. + * + * Note regarding the loading of the firmware image: we use be32_to_cpu() + * and le_32_to_cpu(), so we can support the following four cases: + * - LE kernel + LE firmware image (the most common case) + * - LE kernel + BE firmware image + * - BE kernel + LE firmware image + * - BE kernel + BE firmware image + * + * The DPCU always runs in big endian mode. The firwmare image, however, can + * be in either format. Also, communication between host CPU and DCPU is + * always in little endian. + */ + +#include <linux/delay.h> +#include <linux/firmware.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +#define DRVNAME "brcmstb-dpfe" +#define FIRMWARE_NAME "dpfe.bin" + +/* DCPU register offsets */ +#define REG_DCPU_RESET 0x0 +#define REG_TO_DCPU_MBOX 0x10 +#define REG_TO_HOST_MBOX 0x14 + +/* Message RAM */ +#define DCPU_MSG_RAM(x) (0x100 + (x) * sizeof(u32)) + +/* DRAM Info Offsets & Masks */ +#define DRAM_INFO_INTERVAL 0x0 +#define DRAM_INFO_MR4 0x4 +#define DRAM_INFO_ERROR 0x8 +#define DRAM_INFO_MR4_MASK 0xff + +/* DRAM MR4 Offsets & Masks */ +#define DRAM_MR4_REFRESH 0x0 /* Refresh rate */ +#define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */ +#define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */ +#define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */ +#define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */ + +#define DRAM_MR4_REFRESH_MASK 0x7 +#define DRAM_MR4_SR_ABORT_MASK 0x1 +#define DRAM_MR4_PPRE_MASK 0x1 +#define DRAM_MR4_TH_OFFS_MASK 0x3 +#define DRAM_MR4_TUF_MASK 0x1 + +/* DRAM Vendor Offsets & Masks */ +#define DRAM_VENDOR_MR5 0x0 +#define DRAM_VENDOR_MR6 0x4 +#define DRAM_VENDOR_MR7 0x8 +#define DRAM_VENDOR_MR8 0xc +#define DRAM_VENDOR_ERROR 0x10 +#define DRAM_VENDOR_MASK 0xff + +/* Reset register bits & masks */ +#define DCPU_RESET_SHIFT 0x0 +#define DCPU_RESET_MASK 0x1 +#define DCPU_CLK_DISABLE_SHIFT 0x2 + +/* DCPU return codes */ +#define DCPU_RET_ERROR_BIT BIT(31) +#define DCPU_RET_SUCCESS 0x1 +#define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0)) +#define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1)) +#define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2)) +#define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3)) +/* This error code is not firmware defined and only used in the driver. */ +#define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4)) + +/* Firmware magic */ +#define DPFE_BE_MAGIC 0xfe1010fe +#define DPFE_LE_MAGIC 0xfe0101fe + +/* Error codes */ +#define ERR_INVALID_MAGIC -1 +#define ERR_INVALID_SIZE -2 +#define ERR_INVALID_CHKSUM -3 + +/* Message types */ +#define DPFE_MSG_TYPE_COMMAND 1 +#define DPFE_MSG_TYPE_RESPONSE 2 + +#define DELAY_LOOP_MAX 200000 + +enum dpfe_msg_fields { + MSG_HEADER, + MSG_COMMAND, + MSG_ARG_COUNT, + MSG_ARG0, + MSG_CHKSUM, + MSG_FIELD_MAX /* Last entry */ +}; + +enum dpfe_commands { + DPFE_CMD_GET_INFO, + DPFE_CMD_GET_REFRESH, + DPFE_CMD_GET_VENDOR, + DPFE_CMD_MAX /* Last entry */ +}; + +struct dpfe_msg { + u32 header; + u32 command; + u32 arg_count; + u32 arg0; + u32 chksum; /* This is the sum of all other entries. */ +}; + +/* + * Format of the binary firmware file: + * + * entry + * 0 header + * value: 0xfe0101fe <== little endian + * 0xfe1010fe <== big endian + * 1 sequence: + * [31:16] total segments on this build + * [15:0] this segment sequence. + * 2 FW version + * 3 IMEM byte size + * 4 DMEM byte size + * IMEM + * DMEM + * last checksum ==> sum of everything + */ +struct dpfe_firmware_header { + u32 magic; + u32 sequence; + u32 version; + u32 imem_size; + u32 dmem_size; +}; + +/* Things we only need during initialization. */ +struct init_data { + unsigned int dmem_len; + unsigned int imem_len; + unsigned int chksum; + bool is_big_endian; +}; + +/* Things we need for as long as we are active. */ +struct private_data { + void __iomem *regs; + void __iomem *dmem; + void __iomem *imem; + struct device *dev; + unsigned int index; + struct mutex lock; +}; + +static const char *error_text[] = { + "Success", "Header code incorrect", "Unknown command or argument", + "Incorrect checksum", "Malformed command", "Timed out", +}; + +/* List of supported firmware commands */ +static const u32 dpfe_commands[DPFE_CMD_MAX][MSG_FIELD_MAX] = { + [DPFE_CMD_GET_INFO] = { + [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, + [MSG_COMMAND] = 1, + [MSG_ARG_COUNT] = 1, + [MSG_ARG0] = 1, + [MSG_CHKSUM] = 4, + }, + [DPFE_CMD_GET_REFRESH] = { + [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, + [MSG_COMMAND] = 2, + [MSG_ARG_COUNT] = 1, + [MSG_ARG0] = 1, + [MSG_CHKSUM] = 5, + }, + [DPFE_CMD_GET_VENDOR] = { + [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, + [MSG_COMMAND] = 2, + [MSG_ARG_COUNT] = 1, + [MSG_ARG0] = 2, + [MSG_CHKSUM] = 6, + }, +}; + +static void __disable_dcpu(void __iomem *regs) +{ + u32 val; + + /* Check if DCPU is running */ + val = readl_relaxed(regs + REG_DCPU_RESET); + if (!(val & DCPU_RESET_MASK)) { + /* Put DCPU in reset */ + val |= (1 << DCPU_RESET_SHIFT); + writel_relaxed(val, regs + REG_DCPU_RESET); + } +} + +static void __enable_dcpu(void __iomem *regs) +{ + u32 val; + + /* Clear mailbox registers. */ + writel_relaxed(0, regs + REG_TO_DCPU_MBOX); + writel_relaxed(0, regs + REG_TO_HOST_MBOX); + + /* Disable DCPU clock gating */ + val = readl_relaxed(regs + REG_DCPU_RESET); + val &= ~(1 << DCPU_CLK_DISABLE_SHIFT); + writel_relaxed(val, regs + REG_DCPU_RESET); + + /* Take DCPU out of reset */ + val = readl_relaxed(regs + REG_DCPU_RESET); + val &= ~(1 << DCPU_RESET_SHIFT); + writel_relaxed(val, regs + REG_DCPU_RESET); +} + +static unsigned int get_msg_chksum(const u32 msg[]) +{ + unsigned int sum = 0; + unsigned int i; + + /* Don't include the last field in the checksum. */ + for (i = 0; i < MSG_FIELD_MAX - 1; i++) + sum += msg[i]; + + return sum; +} + +static int __send_command(struct private_data *priv, unsigned int cmd, + u32 result[]) +{ + const u32 *msg = dpfe_commands[cmd]; + void __iomem *regs = priv->regs; + unsigned int i, chksum; + int ret = 0; + u32 resp; + + if (cmd >= DPFE_CMD_MAX) + return -1; + + mutex_lock(&priv->lock); + + /* Write command and arguments to message area */ + for (i = 0; i < MSG_FIELD_MAX; i++) + writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i)); + + /* Tell DCPU there is a command waiting */ + writel_relaxed(1, regs + REG_TO_DCPU_MBOX); + + /* Wait for DCPU to process the command */ + for (i = 0; i < DELAY_LOOP_MAX; i++) { + /* Read response code */ + resp = readl_relaxed(regs + REG_TO_HOST_MBOX); + if (resp > 0) + break; + udelay(5); + } + + if (i == DELAY_LOOP_MAX) { + resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT); + ret = -ffs(resp); + } else { + /* Read response data */ + for (i = 0; i < MSG_FIELD_MAX; i++) + result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i)); + } + + /* Tell DCPU we are done */ + writel_relaxed(0, regs + REG_TO_HOST_MBOX); + + mutex_unlock(&priv->lock); + + if (ret) + return ret; + + /* Verify response */ + chksum = get_msg_chksum(result); + if (chksum != result[MSG_CHKSUM]) + resp = DCPU_RET_ERR_CHKSUM; + + if (resp != DCPU_RET_SUCCESS) { + resp &= ~DCPU_RET_ERROR_BIT; + ret = -ffs(resp); + } + + return ret; +} + +/* Ensure that the firmware file loaded meets all the requirements. */ +static int __verify_firmware(struct init_data *init, + const struct firmware *fw) +{ + const struct dpfe_firmware_header *header = (void *)fw->data; + unsigned int dmem_size, imem_size, total_size; + bool is_big_endian = false; + const u32 *chksum_ptr; + + if (header->magic == DPFE_BE_MAGIC) + is_big_endian = true; + else if (header->magic != DPFE_LE_MAGIC) + return ERR_INVALID_MAGIC; + + if (is_big_endian) { + dmem_size = be32_to_cpu(header->dmem_size); + imem_size = be32_to_cpu(header->imem_size); + } else { + dmem_size = le32_to_cpu(header->dmem_size); + imem_size = le32_to_cpu(header->imem_size); + } + + /* Data and instruction sections are 32 bit words. */ + if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0) + return ERR_INVALID_SIZE; + + /* + * The header + the data section + the instruction section + the + * checksum must be equal to the total firmware size. + */ + total_size = dmem_size + imem_size + sizeof(*header) + + sizeof(*chksum_ptr); + if (total_size != fw->size) + return ERR_INVALID_SIZE; + + /* The checksum comes at the very end. */ + chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size; + + init->is_big_endian = is_big_endian; + init->dmem_len = dmem_size; + init->imem_len = imem_size; + init->chksum = (is_big_endian) + ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr); + + return 0; +} + +/* Verify checksum by reading back the firmware from co-processor RAM. */ +static int __verify_fw_checksum(struct init_data *init, + struct private_data *priv, + const struct dpfe_firmware_header *header, + u32 checksum) +{ + u32 magic, sequence, version, sum; + u32 __iomem *dmem = priv->dmem; + u32 __iomem *imem = priv->imem; + unsigned int i; + + if (init->is_big_endian) { + magic = be32_to_cpu(header->magic); + sequence = be32_to_cpu(header->sequence); + version = be32_to_cpu(header->version); + } else { + magic = le32_to_cpu(header->magic); + sequence = le32_to_cpu(header->sequence); + version = le32_to_cpu(header->version); + } + + sum = magic + sequence + version + init->dmem_len + init->imem_len; + + for (i = 0; i < init->dmem_len / sizeof(u32); i++) + sum += readl_relaxed(dmem + i); + + for (i = 0; i < init->imem_len / sizeof(u32); i++) + sum += readl_relaxed(imem + i); + + return (sum == checksum) ? 0 : -1; +} + +static int __write_firmware(u32 __iomem *mem, const u32 *fw, + unsigned int size, bool is_big_endian) +{ + unsigned int i; + + /* Convert size to 32-bit words. */ + size /= sizeof(u32); + + /* It is recommended to clear the firmware area first. */ + for (i = 0; i < size; i++) + writel_relaxed(0, mem + i); + + /* Now copy it. */ + if (is_big_endian) { + for (i = 0; i < size; i++) + writel_relaxed(be32_to_cpu(fw[i]), mem + i); + } else { + for (i = 0; i < size; i++) + writel_relaxed(le32_to_cpu(fw[i]), mem + i); + } + + return 0; +} + +static int brcmstb_dpfe_download_firmware(struct platform_device *pdev, + struct init_data *init) +{ + const struct dpfe_firmware_header *header; + unsigned int dmem_size, imem_size; + struct device *dev = &pdev->dev; + bool is_big_endian = false; + struct private_data *priv; + const struct firmware *fw; + const u32 *dmem, *imem; + const void *fw_blob; + int ret; + + ret = request_firmware(&fw, FIRMWARE_NAME, dev); + /* request_firmware() prints its own error messages. */ + if (ret) + return ret; + + priv = platform_get_drvdata(pdev); + + ret = __verify_firmware(init, fw); + if (ret) + return -EFAULT; + + __disable_dcpu(priv->regs); + + is_big_endian = init->is_big_endian; + dmem_size = init->dmem_len; + imem_size = init->imem_len; + + /* At the beginning of the firmware blob is a header. */ + header = (struct dpfe_firmware_header *)fw->data; + /* Void pointer to the beginning of the actual firmware. */ + fw_blob = fw->data + sizeof(*header); + /* IMEM comes right after the header. */ + imem = fw_blob; + /* DMEM follows after IMEM. */ + dmem = fw_blob + imem_size; + + ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian); + if (ret) + return ret; + ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian); + if (ret) + return ret; + + ret = __verify_fw_checksum(init, priv, header, init->chksum); + if (ret) + return ret; + + __enable_dcpu(priv->regs); + + return 0; +} + +static ssize_t generic_show(unsigned int command, u32 response[], + struct device *dev, char *buf) +{ + struct private_data *priv; + int ret; + + priv = dev_get_drvdata(dev); + if (!priv) + return sprintf(buf, "ERROR: driver private data not set\n"); + + ret = __send_command(priv, command, response); + if (ret < 0) + return sprintf(buf, "ERROR: %s\n", error_text[-ret]); + + return 0; +} + +static ssize_t show_info(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + u32 response[MSG_FIELD_MAX]; + unsigned int info; + int ret; + + ret = generic_show(DPFE_CMD_GET_INFO, response, dev, buf); + if (ret) + return ret; + + info = response[MSG_ARG0]; + + return sprintf(buf, "%u.%u.%u.%u\n", + (info >> 24) & 0xff, + (info >> 16) & 0xff, + (info >> 8) & 0xff, + info & 0xff); +} + +static ssize_t show_refresh(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + u32 response[MSG_FIELD_MAX]; + void __iomem *info; + struct private_data *priv; + unsigned int offset; + u8 refresh, sr_abort, ppre, thermal_offs, tuf; + u32 mr4; + int ret; + + ret = generic_show(DPFE_CMD_GET_REFRESH, response, dev, buf); + if (ret) + return ret; + + priv = dev_get_drvdata(dev); + offset = response[MSG_ARG0]; + info = priv->dmem + offset; + + mr4 = readl_relaxed(info + DRAM_INFO_MR4) & DRAM_INFO_MR4_MASK; + + refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK; + sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK; + ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK; + thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK; + tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK; + + return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n", + readl_relaxed(info + DRAM_INFO_INTERVAL), + refresh, sr_abort, ppre, thermal_offs, tuf, + readl_relaxed(info + DRAM_INFO_ERROR)); +} + +static ssize_t store_refresh(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + u32 response[MSG_FIELD_MAX]; + struct private_data *priv; + void __iomem *info; + unsigned int offset; + unsigned long val; + int ret; + + if (kstrtoul(buf, 0, &val) < 0) + return -EINVAL; + + priv = dev_get_drvdata(dev); + + ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response); + if (ret) + return ret; + + offset = response[MSG_ARG0]; + info = priv->dmem + offset; + writel_relaxed(val, info + DRAM_INFO_INTERVAL); + + return count; +} + +static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + u32 response[MSG_FIELD_MAX]; + struct private_data *priv; + void __iomem *info; + unsigned int offset; + int ret; + + ret = generic_show(DPFE_CMD_GET_VENDOR, response, dev, buf); + if (ret) + return ret; + + offset = response[MSG_ARG0]; + priv = dev_get_drvdata(dev); + info = priv->dmem + offset; + + return sprintf(buf, "%#x %#x %#x %#x %#x\n", + readl_relaxed(info + DRAM_VENDOR_MR5) & DRAM_VENDOR_MASK, + readl_relaxed(info + DRAM_VENDOR_MR6) & DRAM_VENDOR_MASK, + readl_relaxed(info + DRAM_VENDOR_MR7) & DRAM_VENDOR_MASK, + readl_relaxed(info + DRAM_VENDOR_MR8) & DRAM_VENDOR_MASK, + readl_relaxed(info + DRAM_VENDOR_ERROR)); +} + +static int brcmstb_dpfe_resume(struct platform_device *pdev) +{ + struct init_data init; + + return brcmstb_dpfe_download_firmware(pdev, &init); +} + +static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL); +static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh); +static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL); +static struct attribute *dpfe_attrs[] = { + &dev_attr_dpfe_info.attr, + &dev_attr_dpfe_refresh.attr, + &dev_attr_dpfe_vendor.attr, + NULL +}; +ATTRIBUTE_GROUPS(dpfe); + +static int brcmstb_dpfe_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct private_data *priv; + struct device *dpfe_dev; + struct init_data init; + struct resource *res; + u32 index; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->lock); + platform_set_drvdata(pdev, priv); + + /* Cell index is optional; default to 0 if not present. */ + ret = of_property_read_u32(dev->of_node, "cell-index", &index); + if (ret) + index = 0; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu"); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "couldn't map DCPU registers\n"); + return -ENODEV; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem"); + priv->dmem = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->dmem)) { + dev_err(dev, "Couldn't map DCPU data memory\n"); + return -ENOENT; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem"); + priv->imem = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->imem)) { + dev_err(dev, "Couldn't map DCPU instruction memory\n"); + return -ENOENT; + } + + ret = brcmstb_dpfe_download_firmware(pdev, &init); + if (ret) + goto err; + + dpfe_dev = devm_kzalloc(dev, sizeof(*dpfe_dev), GFP_KERNEL); + if (!dpfe_dev) { + ret = -ENOMEM; + goto err; + } + + priv->dev = dpfe_dev; + priv->index = index; + + dpfe_dev->parent = dev; + dpfe_dev->groups = dpfe_groups; + dpfe_dev->of_node = dev->of_node; + dev_set_drvdata(dpfe_dev, priv); + dev_set_name(dpfe_dev, "dpfe%u", index); + + ret = device_register(dpfe_dev); + if (ret) + goto err; + + dev_info(dev, "registered.\n"); + + return 0; + +err: + dev_err(dev, "failed to initialize -- error %d\n", ret); + + return ret; +} + +static const struct of_device_id brcmstb_dpfe_of_match[] = { + { .compatible = "brcm,dpfe-cpu", }, + {} +}; +MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match); + +static struct platform_driver brcmstb_dpfe_driver = { + .driver = { + .name = DRVNAME, + .of_match_table = brcmstb_dpfe_of_match, + }, + .probe = brcmstb_dpfe_probe, + .resume = brcmstb_dpfe_resume, +}; + +module_platform_driver(brcmstb_dpfe_driver); + +MODULE_AUTHOR("Markus Mayer <mmayer(a)broadcom.com>"); +MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver"); +MODULE_LICENSE("GPL");

4 years, 6 months

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FAILED: patch "[PATCH] memory: brcmstb: Add driver for DPFE" failed to apply to 5.4-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 5.4-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 2f330caff5776239abb3e0337533886dbb21f6df Mon Sep 17 00:00:00 2001 From: Markus Mayer <mmayer(a)broadcom.com> Date: Thu, 24 Aug 2017 16:36:26 -0700 Subject: [PATCH] memory: brcmstb: Add driver for DPFE This driver allows access to DRAM properties, such as the refresh rate, via the Broadcom STB DDR PHY Front End (DPFE). The refresh rate can be used as indirect indicator of the DRAM temperature. The driver also allows setting of the sampling interval. Signed-off-by: Markus Mayer <mmayer(a)broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli(a)gmail.com> diff --git a/MAINTAINERS b/MAINTAINERS index 2281af4b41b6..43ed9eb98c43 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2963,6 +2963,14 @@ L: bcm-kernel-feedback-list(a)broadcom.com S: Maintained F: drivers/mtd/nand/brcmnand/ +BROADCOM STB DPFE DRIVER +M: Markus Mayer <mmayer(a)broadcom.com> +M: bcm-kernel-feedback-list(a)broadcom.com +L: linux-arm-kernel(a)lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: Documentation/devicetree/bindings/memory-controllers/brcm,dpfe-cpu.txt +F: drivers/memory/brcmstb_dpfe.c + BROADCOM SYSTEMPORT ETHERNET DRIVER M: Florian Fainelli <f.fainelli(a)gmail.com> L: netdev(a)vger.kernel.org diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index e88097fbc085..9cb8b61ee5cc 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -8,6 +8,7 @@ endif obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o +obj-$(CONFIG_ARCH_BRCMSTB) += brcmstb_dpfe.o obj-$(CONFIG_TI_AEMIF) += ti-aemif.o obj-$(CONFIG_TI_EMIF) += emif.o obj-$(CONFIG_OMAP_GPMC) += omap-gpmc.o diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c new file mode 100644 index 000000000000..21242c401af5 --- /dev/null +++ b/drivers/memory/brcmstb_dpfe.c @@ -0,0 +1,701 @@ +/* + * DDR PHY Front End (DPFE) driver for Broadcom set top box SoCs + * + * Copyright (c) 2017 Broadcom + * + * Released under the GPLv2 only. + * SPDX-License-Identifier: GPL-2.0 + */ + +/* + * This driver provides access to the DPFE interface of Broadcom STB SoCs. + * The firmware running on the DCPU inside the DDR PHY can provide current + * information about the system's RAM, for instance the DRAM refresh rate. + * This can be used as an indirect indicator for the DRAM's temperature. + * Slower refresh rate means cooler RAM, higher refresh rate means hotter + * RAM. + * + * Throughout the driver, we use readl_relaxed() and writel_relaxed(), which + * already contain the appropriate le32_to_cpu()/cpu_to_le32() calls. + * + * Note regarding the loading of the firmware image: we use be32_to_cpu() + * and le_32_to_cpu(), so we can support the following four cases: + * - LE kernel + LE firmware image (the most common case) + * - LE kernel + BE firmware image + * - BE kernel + LE firmware image + * - BE kernel + BE firmware image + * + * The DPCU always runs in big endian mode. The firwmare image, however, can + * be in either format. Also, communication between host CPU and DCPU is + * always in little endian. + */ + +#include <linux/delay.h> +#include <linux/firmware.h> +#include <linux/io.h> +#include <linux/module.h> +#include <linux/of_address.h> +#include <linux/platform_device.h> + +#define DRVNAME "brcmstb-dpfe" +#define FIRMWARE_NAME "dpfe.bin" + +/* DCPU register offsets */ +#define REG_DCPU_RESET 0x0 +#define REG_TO_DCPU_MBOX 0x10 +#define REG_TO_HOST_MBOX 0x14 + +/* Message RAM */ +#define DCPU_MSG_RAM(x) (0x100 + (x) * sizeof(u32)) + +/* DRAM Info Offsets & Masks */ +#define DRAM_INFO_INTERVAL 0x0 +#define DRAM_INFO_MR4 0x4 +#define DRAM_INFO_ERROR 0x8 +#define DRAM_INFO_MR4_MASK 0xff + +/* DRAM MR4 Offsets & Masks */ +#define DRAM_MR4_REFRESH 0x0 /* Refresh rate */ +#define DRAM_MR4_SR_ABORT 0x3 /* Self Refresh Abort */ +#define DRAM_MR4_PPRE 0x4 /* Post-package repair entry/exit */ +#define DRAM_MR4_TH_OFFS 0x5 /* Thermal Offset; vendor specific */ +#define DRAM_MR4_TUF 0x7 /* Temperature Update Flag */ + +#define DRAM_MR4_REFRESH_MASK 0x7 +#define DRAM_MR4_SR_ABORT_MASK 0x1 +#define DRAM_MR4_PPRE_MASK 0x1 +#define DRAM_MR4_TH_OFFS_MASK 0x3 +#define DRAM_MR4_TUF_MASK 0x1 + +/* DRAM Vendor Offsets & Masks */ +#define DRAM_VENDOR_MR5 0x0 +#define DRAM_VENDOR_MR6 0x4 +#define DRAM_VENDOR_MR7 0x8 +#define DRAM_VENDOR_MR8 0xc +#define DRAM_VENDOR_ERROR 0x10 +#define DRAM_VENDOR_MASK 0xff + +/* Reset register bits & masks */ +#define DCPU_RESET_SHIFT 0x0 +#define DCPU_RESET_MASK 0x1 +#define DCPU_CLK_DISABLE_SHIFT 0x2 + +/* DCPU return codes */ +#define DCPU_RET_ERROR_BIT BIT(31) +#define DCPU_RET_SUCCESS 0x1 +#define DCPU_RET_ERR_HEADER (DCPU_RET_ERROR_BIT | BIT(0)) +#define DCPU_RET_ERR_INVAL (DCPU_RET_ERROR_BIT | BIT(1)) +#define DCPU_RET_ERR_CHKSUM (DCPU_RET_ERROR_BIT | BIT(2)) +#define DCPU_RET_ERR_COMMAND (DCPU_RET_ERROR_BIT | BIT(3)) +/* This error code is not firmware defined and only used in the driver. */ +#define DCPU_RET_ERR_TIMEDOUT (DCPU_RET_ERROR_BIT | BIT(4)) + +/* Firmware magic */ +#define DPFE_BE_MAGIC 0xfe1010fe +#define DPFE_LE_MAGIC 0xfe0101fe + +/* Error codes */ +#define ERR_INVALID_MAGIC -1 +#define ERR_INVALID_SIZE -2 +#define ERR_INVALID_CHKSUM -3 + +/* Message types */ +#define DPFE_MSG_TYPE_COMMAND 1 +#define DPFE_MSG_TYPE_RESPONSE 2 + +#define DELAY_LOOP_MAX 200000 + +enum dpfe_msg_fields { + MSG_HEADER, + MSG_COMMAND, + MSG_ARG_COUNT, + MSG_ARG0, + MSG_CHKSUM, + MSG_FIELD_MAX /* Last entry */ +}; + +enum dpfe_commands { + DPFE_CMD_GET_INFO, + DPFE_CMD_GET_REFRESH, + DPFE_CMD_GET_VENDOR, + DPFE_CMD_MAX /* Last entry */ +}; + +struct dpfe_msg { + u32 header; + u32 command; + u32 arg_count; + u32 arg0; + u32 chksum; /* This is the sum of all other entries. */ +}; + +/* + * Format of the binary firmware file: + * + * entry + * 0 header + * value: 0xfe0101fe <== little endian + * 0xfe1010fe <== big endian + * 1 sequence: + * [31:16] total segments on this build + * [15:0] this segment sequence. + * 2 FW version + * 3 IMEM byte size + * 4 DMEM byte size + * IMEM + * DMEM + * last checksum ==> sum of everything + */ +struct dpfe_firmware_header { + u32 magic; + u32 sequence; + u32 version; + u32 imem_size; + u32 dmem_size; +}; + +/* Things we only need during initialization. */ +struct init_data { + unsigned int dmem_len; + unsigned int imem_len; + unsigned int chksum; + bool is_big_endian; +}; + +/* Things we need for as long as we are active. */ +struct private_data { + void __iomem *regs; + void __iomem *dmem; + void __iomem *imem; + struct device *dev; + unsigned int index; + struct mutex lock; +}; + +static const char *error_text[] = { + "Success", "Header code incorrect", "Unknown command or argument", + "Incorrect checksum", "Malformed command", "Timed out", +}; + +/* List of supported firmware commands */ +static const u32 dpfe_commands[DPFE_CMD_MAX][MSG_FIELD_MAX] = { + [DPFE_CMD_GET_INFO] = { + [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, + [MSG_COMMAND] = 1, + [MSG_ARG_COUNT] = 1, + [MSG_ARG0] = 1, + [MSG_CHKSUM] = 4, + }, + [DPFE_CMD_GET_REFRESH] = { + [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, + [MSG_COMMAND] = 2, + [MSG_ARG_COUNT] = 1, + [MSG_ARG0] = 1, + [MSG_CHKSUM] = 5, + }, + [DPFE_CMD_GET_VENDOR] = { + [MSG_HEADER] = DPFE_MSG_TYPE_COMMAND, + [MSG_COMMAND] = 2, + [MSG_ARG_COUNT] = 1, + [MSG_ARG0] = 2, + [MSG_CHKSUM] = 6, + }, +}; + +static void __disable_dcpu(void __iomem *regs) +{ + u32 val; + + /* Check if DCPU is running */ + val = readl_relaxed(regs + REG_DCPU_RESET); + if (!(val & DCPU_RESET_MASK)) { + /* Put DCPU in reset */ + val |= (1 << DCPU_RESET_SHIFT); + writel_relaxed(val, regs + REG_DCPU_RESET); + } +} + +static void __enable_dcpu(void __iomem *regs) +{ + u32 val; + + /* Clear mailbox registers. */ + writel_relaxed(0, regs + REG_TO_DCPU_MBOX); + writel_relaxed(0, regs + REG_TO_HOST_MBOX); + + /* Disable DCPU clock gating */ + val = readl_relaxed(regs + REG_DCPU_RESET); + val &= ~(1 << DCPU_CLK_DISABLE_SHIFT); + writel_relaxed(val, regs + REG_DCPU_RESET); + + /* Take DCPU out of reset */ + val = readl_relaxed(regs + REG_DCPU_RESET); + val &= ~(1 << DCPU_RESET_SHIFT); + writel_relaxed(val, regs + REG_DCPU_RESET); +} + +static unsigned int get_msg_chksum(const u32 msg[]) +{ + unsigned int sum = 0; + unsigned int i; + + /* Don't include the last field in the checksum. */ + for (i = 0; i < MSG_FIELD_MAX - 1; i++) + sum += msg[i]; + + return sum; +} + +static int __send_command(struct private_data *priv, unsigned int cmd, + u32 result[]) +{ + const u32 *msg = dpfe_commands[cmd]; + void __iomem *regs = priv->regs; + unsigned int i, chksum; + int ret = 0; + u32 resp; + + if (cmd >= DPFE_CMD_MAX) + return -1; + + mutex_lock(&priv->lock); + + /* Write command and arguments to message area */ + for (i = 0; i < MSG_FIELD_MAX; i++) + writel_relaxed(msg[i], regs + DCPU_MSG_RAM(i)); + + /* Tell DCPU there is a command waiting */ + writel_relaxed(1, regs + REG_TO_DCPU_MBOX); + + /* Wait for DCPU to process the command */ + for (i = 0; i < DELAY_LOOP_MAX; i++) { + /* Read response code */ + resp = readl_relaxed(regs + REG_TO_HOST_MBOX); + if (resp > 0) + break; + udelay(5); + } + + if (i == DELAY_LOOP_MAX) { + resp = (DCPU_RET_ERR_TIMEDOUT & ~DCPU_RET_ERROR_BIT); + ret = -ffs(resp); + } else { + /* Read response data */ + for (i = 0; i < MSG_FIELD_MAX; i++) + result[i] = readl_relaxed(regs + DCPU_MSG_RAM(i)); + } + + /* Tell DCPU we are done */ + writel_relaxed(0, regs + REG_TO_HOST_MBOX); + + mutex_unlock(&priv->lock); + + if (ret) + return ret; + + /* Verify response */ + chksum = get_msg_chksum(result); + if (chksum != result[MSG_CHKSUM]) + resp = DCPU_RET_ERR_CHKSUM; + + if (resp != DCPU_RET_SUCCESS) { + resp &= ~DCPU_RET_ERROR_BIT; + ret = -ffs(resp); + } + + return ret; +} + +/* Ensure that the firmware file loaded meets all the requirements. */ +static int __verify_firmware(struct init_data *init, + const struct firmware *fw) +{ + const struct dpfe_firmware_header *header = (void *)fw->data; + unsigned int dmem_size, imem_size, total_size; + bool is_big_endian = false; + const u32 *chksum_ptr; + + if (header->magic == DPFE_BE_MAGIC) + is_big_endian = true; + else if (header->magic != DPFE_LE_MAGIC) + return ERR_INVALID_MAGIC; + + if (is_big_endian) { + dmem_size = be32_to_cpu(header->dmem_size); + imem_size = be32_to_cpu(header->imem_size); + } else { + dmem_size = le32_to_cpu(header->dmem_size); + imem_size = le32_to_cpu(header->imem_size); + } + + /* Data and instruction sections are 32 bit words. */ + if ((dmem_size % sizeof(u32)) != 0 || (imem_size % sizeof(u32)) != 0) + return ERR_INVALID_SIZE; + + /* + * The header + the data section + the instruction section + the + * checksum must be equal to the total firmware size. + */ + total_size = dmem_size + imem_size + sizeof(*header) + + sizeof(*chksum_ptr); + if (total_size != fw->size) + return ERR_INVALID_SIZE; + + /* The checksum comes at the very end. */ + chksum_ptr = (void *)fw->data + sizeof(*header) + dmem_size + imem_size; + + init->is_big_endian = is_big_endian; + init->dmem_len = dmem_size; + init->imem_len = imem_size; + init->chksum = (is_big_endian) + ? be32_to_cpu(*chksum_ptr) : le32_to_cpu(*chksum_ptr); + + return 0; +} + +/* Verify checksum by reading back the firmware from co-processor RAM. */ +static int __verify_fw_checksum(struct init_data *init, + struct private_data *priv, + const struct dpfe_firmware_header *header, + u32 checksum) +{ + u32 magic, sequence, version, sum; + u32 __iomem *dmem = priv->dmem; + u32 __iomem *imem = priv->imem; + unsigned int i; + + if (init->is_big_endian) { + magic = be32_to_cpu(header->magic); + sequence = be32_to_cpu(header->sequence); + version = be32_to_cpu(header->version); + } else { + magic = le32_to_cpu(header->magic); + sequence = le32_to_cpu(header->sequence); + version = le32_to_cpu(header->version); + } + + sum = magic + sequence + version + init->dmem_len + init->imem_len; + + for (i = 0; i < init->dmem_len / sizeof(u32); i++) + sum += readl_relaxed(dmem + i); + + for (i = 0; i < init->imem_len / sizeof(u32); i++) + sum += readl_relaxed(imem + i); + + return (sum == checksum) ? 0 : -1; +} + +static int __write_firmware(u32 __iomem *mem, const u32 *fw, + unsigned int size, bool is_big_endian) +{ + unsigned int i; + + /* Convert size to 32-bit words. */ + size /= sizeof(u32); + + /* It is recommended to clear the firmware area first. */ + for (i = 0; i < size; i++) + writel_relaxed(0, mem + i); + + /* Now copy it. */ + if (is_big_endian) { + for (i = 0; i < size; i++) + writel_relaxed(be32_to_cpu(fw[i]), mem + i); + } else { + for (i = 0; i < size; i++) + writel_relaxed(le32_to_cpu(fw[i]), mem + i); + } + + return 0; +} + +static int brcmstb_dpfe_download_firmware(struct platform_device *pdev, + struct init_data *init) +{ + const struct dpfe_firmware_header *header; + unsigned int dmem_size, imem_size; + struct device *dev = &pdev->dev; + bool is_big_endian = false; + struct private_data *priv; + const struct firmware *fw; + const u32 *dmem, *imem; + const void *fw_blob; + int ret; + + ret = request_firmware(&fw, FIRMWARE_NAME, dev); + /* request_firmware() prints its own error messages. */ + if (ret) + return ret; + + priv = platform_get_drvdata(pdev); + + ret = __verify_firmware(init, fw); + if (ret) + return -EFAULT; + + __disable_dcpu(priv->regs); + + is_big_endian = init->is_big_endian; + dmem_size = init->dmem_len; + imem_size = init->imem_len; + + /* At the beginning of the firmware blob is a header. */ + header = (struct dpfe_firmware_header *)fw->data; + /* Void pointer to the beginning of the actual firmware. */ + fw_blob = fw->data + sizeof(*header); + /* IMEM comes right after the header. */ + imem = fw_blob; + /* DMEM follows after IMEM. */ + dmem = fw_blob + imem_size; + + ret = __write_firmware(priv->dmem, dmem, dmem_size, is_big_endian); + if (ret) + return ret; + ret = __write_firmware(priv->imem, imem, imem_size, is_big_endian); + if (ret) + return ret; + + ret = __verify_fw_checksum(init, priv, header, init->chksum); + if (ret) + return ret; + + __enable_dcpu(priv->regs); + + return 0; +} + +static ssize_t generic_show(unsigned int command, u32 response[], + struct device *dev, char *buf) +{ + struct private_data *priv; + int ret; + + priv = dev_get_drvdata(dev); + if (!priv) + return sprintf(buf, "ERROR: driver private data not set\n"); + + ret = __send_command(priv, command, response); + if (ret < 0) + return sprintf(buf, "ERROR: %s\n", error_text[-ret]); + + return 0; +} + +static ssize_t show_info(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + u32 response[MSG_FIELD_MAX]; + unsigned int info; + int ret; + + ret = generic_show(DPFE_CMD_GET_INFO, response, dev, buf); + if (ret) + return ret; + + info = response[MSG_ARG0]; + + return sprintf(buf, "%u.%u.%u.%u\n", + (info >> 24) & 0xff, + (info >> 16) & 0xff, + (info >> 8) & 0xff, + info & 0xff); +} + +static ssize_t show_refresh(struct device *dev, + struct device_attribute *devattr, char *buf) +{ + u32 response[MSG_FIELD_MAX]; + void __iomem *info; + struct private_data *priv; + unsigned int offset; + u8 refresh, sr_abort, ppre, thermal_offs, tuf; + u32 mr4; + int ret; + + ret = generic_show(DPFE_CMD_GET_REFRESH, response, dev, buf); + if (ret) + return ret; + + priv = dev_get_drvdata(dev); + offset = response[MSG_ARG0]; + info = priv->dmem + offset; + + mr4 = readl_relaxed(info + DRAM_INFO_MR4) & DRAM_INFO_MR4_MASK; + + refresh = (mr4 >> DRAM_MR4_REFRESH) & DRAM_MR4_REFRESH_MASK; + sr_abort = (mr4 >> DRAM_MR4_SR_ABORT) & DRAM_MR4_SR_ABORT_MASK; + ppre = (mr4 >> DRAM_MR4_PPRE) & DRAM_MR4_PPRE_MASK; + thermal_offs = (mr4 >> DRAM_MR4_TH_OFFS) & DRAM_MR4_TH_OFFS_MASK; + tuf = (mr4 >> DRAM_MR4_TUF) & DRAM_MR4_TUF_MASK; + + return sprintf(buf, "%#x %#x %#x %#x %#x %#x %#x\n", + readl_relaxed(info + DRAM_INFO_INTERVAL), + refresh, sr_abort, ppre, thermal_offs, tuf, + readl_relaxed(info + DRAM_INFO_ERROR)); +} + +static ssize_t store_refresh(struct device *dev, struct device_attribute *attr, + const char *buf, size_t count) +{ + u32 response[MSG_FIELD_MAX]; + struct private_data *priv; + void __iomem *info; + unsigned int offset; + unsigned long val; + int ret; + + if (kstrtoul(buf, 0, &val) < 0) + return -EINVAL; + + priv = dev_get_drvdata(dev); + + ret = __send_command(priv, DPFE_CMD_GET_REFRESH, response); + if (ret) + return ret; + + offset = response[MSG_ARG0]; + info = priv->dmem + offset; + writel_relaxed(val, info + DRAM_INFO_INTERVAL); + + return count; +} + +static ssize_t show_vendor(struct device *dev, struct device_attribute *devattr, + char *buf) +{ + u32 response[MSG_FIELD_MAX]; + struct private_data *priv; + void __iomem *info; + unsigned int offset; + int ret; + + ret = generic_show(DPFE_CMD_GET_VENDOR, response, dev, buf); + if (ret) + return ret; + + offset = response[MSG_ARG0]; + priv = dev_get_drvdata(dev); + info = priv->dmem + offset; + + return sprintf(buf, "%#x %#x %#x %#x %#x\n", + readl_relaxed(info + DRAM_VENDOR_MR5) & DRAM_VENDOR_MASK, + readl_relaxed(info + DRAM_VENDOR_MR6) & DRAM_VENDOR_MASK, + readl_relaxed(info + DRAM_VENDOR_MR7) & DRAM_VENDOR_MASK, + readl_relaxed(info + DRAM_VENDOR_MR8) & DRAM_VENDOR_MASK, + readl_relaxed(info + DRAM_VENDOR_ERROR)); +} + +static int brcmstb_dpfe_resume(struct platform_device *pdev) +{ + struct init_data init; + + return brcmstb_dpfe_download_firmware(pdev, &init); +} + +static DEVICE_ATTR(dpfe_info, 0444, show_info, NULL); +static DEVICE_ATTR(dpfe_refresh, 0644, show_refresh, store_refresh); +static DEVICE_ATTR(dpfe_vendor, 0444, show_vendor, NULL); +static struct attribute *dpfe_attrs[] = { + &dev_attr_dpfe_info.attr, + &dev_attr_dpfe_refresh.attr, + &dev_attr_dpfe_vendor.attr, + NULL +}; +ATTRIBUTE_GROUPS(dpfe); + +static int brcmstb_dpfe_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct private_data *priv; + struct device *dpfe_dev; + struct init_data init; + struct resource *res; + u32 index; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + mutex_init(&priv->lock); + platform_set_drvdata(pdev, priv); + + /* Cell index is optional; default to 0 if not present. */ + ret = of_property_read_u32(dev->of_node, "cell-index", &index); + if (ret) + index = 0; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-cpu"); + priv->regs = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->regs)) { + dev_err(dev, "couldn't map DCPU registers\n"); + return -ENODEV; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-dmem"); + priv->dmem = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->dmem)) { + dev_err(dev, "Couldn't map DCPU data memory\n"); + return -ENOENT; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dpfe-imem"); + priv->imem = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->imem)) { + dev_err(dev, "Couldn't map DCPU instruction memory\n"); + return -ENOENT; + } + + ret = brcmstb_dpfe_download_firmware(pdev, &init); + if (ret) + goto err; + + dpfe_dev = devm_kzalloc(dev, sizeof(*dpfe_dev), GFP_KERNEL); + if (!dpfe_dev) { + ret = -ENOMEM; + goto err; + } + + priv->dev = dpfe_dev; + priv->index = index; + + dpfe_dev->parent = dev; + dpfe_dev->groups = dpfe_groups; + dpfe_dev->of_node = dev->of_node; + dev_set_drvdata(dpfe_dev, priv); + dev_set_name(dpfe_dev, "dpfe%u", index); + + ret = device_register(dpfe_dev); + if (ret) + goto err; + + dev_info(dev, "registered.\n"); + + return 0; + +err: + dev_err(dev, "failed to initialize -- error %d\n", ret); + + return ret; +} + +static const struct of_device_id brcmstb_dpfe_of_match[] = { + { .compatible = "brcm,dpfe-cpu", }, + {} +}; +MODULE_DEVICE_TABLE(of, brcmstb_dpfe_of_match); + +static struct platform_driver brcmstb_dpfe_driver = { + .driver = { + .name = DRVNAME, + .of_match_table = brcmstb_dpfe_of_match, + }, + .probe = brcmstb_dpfe_probe, + .resume = brcmstb_dpfe_resume, +}; + +module_platform_driver(brcmstb_dpfe_driver); + +MODULE_AUTHOR("Markus Mayer <mmayer(a)broadcom.com>"); +MODULE_DESCRIPTION("BRCMSTB DDR PHY Front End Driver"); +MODULE_LICENSE("GPL");

4 years, 6 months

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FAILED: patch "[PATCH] mmc: sdhci-of-esdhc: set timeout to max before tuning" failed to apply to 4.19-stable tree

by gregkh＠linuxfoundation.org

The patch below does not apply to the 4.19-stable tree. If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <stable(a)vger.kernel.org>. thanks, greg k-h ------------------ original commit in Linus's tree ------------------ >From 0add6e9b88d0632a25323aaf4987dbacb0e4ae64 Mon Sep 17 00:00:00 2001 From: Michael Walle <michael(a)walle.cc> Date: Fri, 23 Oct 2020 00:23:37 +0200 Subject: [PATCH] mmc: sdhci-of-esdhc: set timeout to max before tuning On rare occations there is the following error: mmc0: Tuning timeout, falling back to fixed sampling clock There are SD cards which takes a significant longer time to reply to the first CMD19 command. The eSDHC takes the data timeout value into account during the tuning period. The SDHCI core doesn't explicitly set this timeout for the tuning procedure. Thus on the slow cards, there might be a spurious "Buffer Read Ready" interrupt, which in turn triggers a wrong sequence of events. In the end this will lead to an unsuccessful tuning procedure and to the above error. To workaround this, set the timeout to the maximum value (which is the best we can do) and the SDHCI core will take care of the proper timeout handling. Fixes: ba49cbd0936e ("mmc: sdhci-of-esdhc: add tuning support") Signed-off-by: Michael Walle <michael(a)walle.cc> Acked-by: Adrian Hunter <adrian.hunter(a)intel.com> Cc: stable(a)vger.kernel.org Link: https://lore.kernel.org/r/20201022222337.19857-1-michael@walle.cc Signed-off-by: Ulf Hansson <ulf.hansson(a)linaro.org> diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c index 0b45eff6fed4..baf7801a1804 100644 --- a/drivers/mmc/host/sdhci-of-esdhc.c +++ b/drivers/mmc/host/sdhci-of-esdhc.c @@ -1052,6 +1052,17 @@ static int esdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) esdhc_tuning_block_enable(host, true); + /* + * The eSDHC controller takes the data timeout value into account + * during tuning. If the SD card is too slow sending the response, the + * timer will expire and a "Buffer Read Ready" interrupt without data + * is triggered. This leads to tuning errors. + * + * Just set the timeout to the maximum value because the core will + * already take care of it in sdhci_send_tuning(). + */ + sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL); + hs400_tuning = host->flags & SDHCI_HS400_TUNING; do {

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Linux-stable-mirror November 2020