This is a note to let you know that I've just added the patch titled
x86/microcode: Synchronize late microcode loading
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum…
The filename of the patch is:
x86-microcode-synchronize-late-microcode-loading.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable(a)vger.kernel.org> know about it.
>From a5321aec6412b20b5ad15db2d6b916c05349dbff Mon Sep 17 00:00:00 2001
From: Ashok Raj <ashok.raj(a)intel.com>
Date: Wed, 28 Feb 2018 11:28:46 +0100
Subject: x86/microcode: Synchronize late microcode loading
From: Ashok Raj <ashok.raj(a)intel.com>
commit a5321aec6412b20b5ad15db2d6b916c05349dbff upstream.
Original idea by Ashok, completely rewritten by Borislav.
Before you read any further: the early loading method is still the
preferred one and you should always do that. The following patch is
improving the late loading mechanism for long running jobs and cloud use
cases.
Gather all cores and serialize the microcode update on them by doing it
one-by-one to make the late update process as reliable as possible and
avoid potential issues caused by the microcode update.
[ Borislav: Rewrite completely. ]
Co-developed-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Ashok Raj <ashok.raj(a)intel.com>
Signed-off-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Tested-by: Ashok Raj <ashok.raj(a)intel.com>
Reviewed-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Cc: Arjan Van De Ven <arjan.van.de.ven(a)intel.com>
Link: https://lkml.kernel.org/r/20180228102846.13447-8-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
arch/x86/kernel/cpu/microcode/core.c | 118 +++++++++++++++++++++++++++--------
1 file changed, 92 insertions(+), 26 deletions(-)
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -22,13 +22,16 @@
#define pr_fmt(fmt) "microcode: " fmt
#include <linux/platform_device.h>
+#include <linux/stop_machine.h>
#include <linux/syscore_ops.h>
#include <linux/miscdevice.h>
#include <linux/capability.h>
#include <linux/firmware.h>
#include <linux/kernel.h>
+#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/cpu.h>
+#include <linux/nmi.h>
#include <linux/fs.h>
#include <linux/mm.h>
@@ -64,6 +67,11 @@ LIST_HEAD(microcode_cache);
*/
static DEFINE_MUTEX(microcode_mutex);
+/*
+ * Serialize late loading so that CPUs get updated one-by-one.
+ */
+static DEFINE_SPINLOCK(update_lock);
+
struct ucode_cpu_info ucode_cpu_info[NR_CPUS];
struct cpu_info_ctx {
@@ -486,6 +494,19 @@ static void __exit microcode_dev_exit(vo
/* fake device for request_firmware */
static struct platform_device *microcode_pdev;
+/*
+ * Late loading dance. Why the heavy-handed stomp_machine effort?
+ *
+ * - HT siblings must be idle and not execute other code while the other sibling
+ * is loading microcode in order to avoid any negative interactions caused by
+ * the loading.
+ *
+ * - In addition, microcode update on the cores must be serialized until this
+ * requirement can be relaxed in the future. Right now, this is conservative
+ * and good.
+ */
+#define SPINUNIT 100 /* 100 nsec */
+
static int check_online_cpus(void)
{
if (num_online_cpus() == num_present_cpus())
@@ -496,23 +517,85 @@ static int check_online_cpus(void)
return -EINVAL;
}
-static enum ucode_state reload_for_cpu(int cpu)
+static atomic_t late_cpus;
+
+/*
+ * Returns:
+ * < 0 - on error
+ * 0 - no update done
+ * 1 - microcode was updated
+ */
+static int __reload_late(void *info)
{
- struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
+ unsigned int timeout = NSEC_PER_SEC;
+ int all_cpus = num_online_cpus();
+ int cpu = smp_processor_id();
+ enum ucode_state err;
+ int ret = 0;
+
+ atomic_dec(&late_cpus);
+
+ /*
+ * Wait for all CPUs to arrive. A load will not be attempted unless all
+ * CPUs show up.
+ * */
+ while (atomic_read(&late_cpus)) {
+ if (timeout < SPINUNIT) {
+ pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n",
+ atomic_read(&late_cpus));
+ return -1;
+ }
+
+ ndelay(SPINUNIT);
+ timeout -= SPINUNIT;
+
+ touch_nmi_watchdog();
+ }
+
+ spin_lock(&update_lock);
+ apply_microcode_local(&err);
+ spin_unlock(&update_lock);
+
+ if (err > UCODE_NFOUND) {
+ pr_warn("Error reloading microcode on CPU %d\n", cpu);
+ ret = -1;
+ } else if (err == UCODE_UPDATED) {
+ ret = 1;
+ }
- if (!uci->valid)
- return UCODE_OK;
+ atomic_inc(&late_cpus);
- return apply_microcode_on_target(cpu);
+ while (atomic_read(&late_cpus) != all_cpus)
+ cpu_relax();
+
+ return ret;
+}
+
+/*
+ * Reload microcode late on all CPUs. Wait for a sec until they
+ * all gather together.
+ */
+static int microcode_reload_late(void)
+{
+ int ret;
+
+ atomic_set(&late_cpus, num_online_cpus());
+
+ ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask);
+ if (ret < 0)
+ return ret;
+ else if (ret > 0)
+ microcode_check();
+
+ return ret;
}
static ssize_t reload_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t size)
{
- int cpu, bsp = boot_cpu_data.cpu_index;
enum ucode_state tmp_ret = UCODE_OK;
- bool do_callback = false;
+ int bsp = boot_cpu_data.cpu_index;
unsigned long val;
ssize_t ret = 0;
@@ -534,30 +617,13 @@ static ssize_t reload_store(struct devic
goto put;
mutex_lock(µcode_mutex);
-
- for_each_online_cpu(cpu) {
- tmp_ret = reload_for_cpu(cpu);
- if (tmp_ret > UCODE_NFOUND) {
- pr_warn("Error reloading microcode on CPU %d\n", cpu);
-
- /* set retval for the first encountered reload error */
- if (!ret)
- ret = -EINVAL;
- }
-
- if (tmp_ret == UCODE_UPDATED)
- do_callback = true;
- }
-
- if (!ret && do_callback)
- microcode_check();
-
+ ret = microcode_reload_late();
mutex_unlock(µcode_mutex);
put:
put_online_cpus();
- if (!ret)
+ if (ret >= 0)
ret = size;
return ret;
Patches currently in stable-queue which might be from ashok.raj(a)intel.com are
queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch
This is a note to let you know that I've just added the patch titled
x86/microcode: Request microcode on the BSP
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum…
The filename of the patch is:
x86-microcode-request-microcode-on-the-bsp.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable(a)vger.kernel.org> know about it.
>From cfb52a5a09c8ae3a1dafb44ce549fde5b69e8117 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp(a)suse.de>
Date: Wed, 28 Feb 2018 11:28:45 +0100
Subject: x86/microcode: Request microcode on the BSP
From: Borislav Petkov <bp(a)suse.de>
commit cfb52a5a09c8ae3a1dafb44ce549fde5b69e8117 upstream.
... so that any newer version can land in the cache and can later be
fished out by the application functions. Do that before grabbing the
hotplug lock.
Signed-off-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Tested-by: Ashok Raj <ashok.raj(a)intel.com>
Reviewed-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Cc: Arjan Van De Ven <arjan.van.de.ven(a)intel.com>
Link: https://lkml.kernel.org/r/20180228102846.13447-7-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
arch/x86/kernel/cpu/microcode/core.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -499,15 +499,10 @@ static int check_online_cpus(void)
static enum ucode_state reload_for_cpu(int cpu)
{
struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
- enum ucode_state ustate;
if (!uci->valid)
return UCODE_OK;
- ustate = microcode_ops->request_microcode_fw(cpu, µcode_pdev->dev, true);
- if (ustate != UCODE_OK)
- return ustate;
-
return apply_microcode_on_target(cpu);
}
@@ -515,11 +510,11 @@ static ssize_t reload_store(struct devic
struct device_attribute *attr,
const char *buf, size_t size)
{
+ int cpu, bsp = boot_cpu_data.cpu_index;
enum ucode_state tmp_ret = UCODE_OK;
bool do_callback = false;
unsigned long val;
ssize_t ret = 0;
- int cpu;
ret = kstrtoul(buf, 0, &val);
if (ret)
@@ -528,6 +523,10 @@ static ssize_t reload_store(struct devic
if (val != 1)
return size;
+ tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev, true);
+ if (tmp_ret != UCODE_OK)
+ return size;
+
get_online_cpus();
ret = check_online_cpus();
Patches currently in stable-queue which might be from bp(a)suse.de are
queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/edac-mv64x60-fix-an-error-handling-path.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch
This is a note to let you know that I've just added the patch titled
x86/microcode/intel: Writeback and invalidate caches before updating microcode
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum…
The filename of the patch is:
x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable(a)vger.kernel.org> know about it.
>From 91df9fdf51492aec9fed6b4cbd33160886740f47 Mon Sep 17 00:00:00 2001
From: Ashok Raj <ashok.raj(a)intel.com>
Date: Wed, 28 Feb 2018 11:28:42 +0100
Subject: x86/microcode/intel: Writeback and invalidate caches before updating microcode
From: Ashok Raj <ashok.raj(a)intel.com>
commit 91df9fdf51492aec9fed6b4cbd33160886740f47 upstream.
Updating microcode is less error prone when caches have been flushed and
depending on what exactly the microcode is updating. For example, some
of the issues around certain Broadwell parts can be addressed by doing a
full cache flush.
[ Borislav: Massage it and use native_wbinvd() in both cases. ]
Signed-off-by: Ashok Raj <ashok.raj(a)intel.com>
Signed-off-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Tested-by: Ashok Raj <ashok.raj(a)intel.com>
Cc: Arjan Van De Ven <arjan.van.de.ven(a)intel.com>
Link: http://lkml.kernel.org/r/1519352533-15992-3-git-send-email-ashok.raj@intel.…
Link: https://lkml.kernel.org/r/20180228102846.13447-4-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
arch/x86/kernel/cpu/microcode/intel.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -600,6 +600,12 @@ static int apply_microcode_early(struct
return UCODE_OK;
}
+ /*
+ * Writeback and invalidate caches before updating microcode to avoid
+ * internal issues depending on what the microcode is updating.
+ */
+ native_wbinvd();
+
/* write microcode via MSR 0x79 */
native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -816,6 +822,12 @@ static enum ucode_state apply_microcode_
return UCODE_OK;
}
+ /*
+ * Writeback and invalidate caches before updating microcode to avoid
+ * internal issues depending on what the microcode is updating.
+ */
+ native_wbinvd();
+
/* write microcode via MSR 0x79 */
wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
Patches currently in stable-queue which might be from ashok.raj(a)intel.com are
queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch
This is a note to let you know that I've just added the patch titled
x86/microcode/intel: Look into the patch cache first
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum…
The filename of the patch is:
x86-microcode-intel-look-into-the-patch-cache-first.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable(a)vger.kernel.org> know about it.
>From d8c3b52c00a05036e0a6b315b4b17921a7b67997 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp(a)suse.de>
Date: Wed, 28 Feb 2018 11:28:44 +0100
Subject: x86/microcode/intel: Look into the patch cache first
From: Borislav Petkov <bp(a)suse.de>
commit d8c3b52c00a05036e0a6b315b4b17921a7b67997 upstream.
The cache might contain a newer patch - look in there first.
A follow-on change will make sure newest patches are loaded into the
cache of microcode patches.
Signed-off-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Tested-by: Ashok Raj <ashok.raj(a)intel.com>
Cc: Arjan Van De Ven <arjan.van.de.ven(a)intel.com>
Link: https://lkml.kernel.org/r/20180228102846.13447-6-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
arch/x86/kernel/cpu/microcode/intel.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -791,9 +791,9 @@ static int collect_cpu_info(int cpu_num,
static enum ucode_state apply_microcode_intel(int cpu)
{
- struct microcode_intel *mc;
- struct ucode_cpu_info *uci;
+ struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
struct cpuinfo_x86 *c = &cpu_data(cpu);
+ struct microcode_intel *mc;
static int prev_rev;
u32 rev;
@@ -801,11 +801,10 @@ static enum ucode_state apply_microcode_
if (WARN_ON(raw_smp_processor_id() != cpu))
return UCODE_ERROR;
- uci = ucode_cpu_info + cpu;
- mc = uci->mc;
+ /* Look for a newer patch in our cache: */
+ mc = find_patch(uci);
if (!mc) {
- /* Look for a newer patch in our cache: */
- mc = find_patch(uci);
+ mc = uci->mc;
if (!mc)
return UCODE_NFOUND;
}
Patches currently in stable-queue which might be from bp(a)suse.de are
queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/edac-mv64x60-fix-an-error-handling-path.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch
This is a note to let you know that I've just added the patch titled
x86/microcode/intel: Check microcode revision before updating sibling threads
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum…
The filename of the patch is:
x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable(a)vger.kernel.org> know about it.
>From c182d2b7d0ca48e0d6ff16f7d883161238c447ed Mon Sep 17 00:00:00 2001
From: Ashok Raj <ashok.raj(a)intel.com>
Date: Wed, 28 Feb 2018 11:28:41 +0100
Subject: x86/microcode/intel: Check microcode revision before updating sibling threads
From: Ashok Raj <ashok.raj(a)intel.com>
commit c182d2b7d0ca48e0d6ff16f7d883161238c447ed upstream.
After updating microcode on one of the threads of a core, the other
thread sibling automatically gets the update since the microcode
resources on a hyperthreaded core are shared between the two threads.
Check the microcode revision on the CPU before performing a microcode
update and thus save us the WRMSR 0x79 because it is a particularly
expensive operation.
[ Borislav: Massage changelog and coding style. ]
Signed-off-by: Ashok Raj <ashok.raj(a)intel.com>
Signed-off-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Tested-by: Ashok Raj <ashok.raj(a)intel.com>
Cc: Arjan Van De Ven <arjan.van.de.ven(a)intel.com>
Link: http://lkml.kernel.org/r/1519352533-15992-2-git-send-email-ashok.raj@intel.…
Link: https://lkml.kernel.org/r/20180228102846.13447-3-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
arch/x86/kernel/cpu/microcode/intel.c | 27 ++++++++++++++++++++++++---
1 file changed, 24 insertions(+), 3 deletions(-)
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -589,6 +589,17 @@ static int apply_microcode_early(struct
if (!mc)
return 0;
+ /*
+ * Save us the MSR write below - which is a particular expensive
+ * operation - when the other hyperthread has updated the microcode
+ * already.
+ */
+ rev = intel_get_microcode_revision();
+ if (rev >= mc->hdr.rev) {
+ uci->cpu_sig.rev = rev;
+ return UCODE_OK;
+ }
+
/* write microcode via MSR 0x79 */
native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -776,7 +787,7 @@ static enum ucode_state apply_microcode_
{
struct microcode_intel *mc;
struct ucode_cpu_info *uci;
- struct cpuinfo_x86 *c;
+ struct cpuinfo_x86 *c = &cpu_data(cpu);
static int prev_rev;
u32 rev;
@@ -793,6 +804,18 @@ static enum ucode_state apply_microcode_
return UCODE_NFOUND;
}
+ /*
+ * Save us the MSR write below - which is a particular expensive
+ * operation - when the other hyperthread has updated the microcode
+ * already.
+ */
+ rev = intel_get_microcode_revision();
+ if (rev >= mc->hdr.rev) {
+ uci->cpu_sig.rev = rev;
+ c->microcode = rev;
+ return UCODE_OK;
+ }
+
/* write microcode via MSR 0x79 */
wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
@@ -813,8 +836,6 @@ static enum ucode_state apply_microcode_
prev_rev = rev;
}
- c = &cpu_data(cpu);
-
uci->cpu_sig.rev = rev;
c->microcode = rev;
Patches currently in stable-queue which might be from ashok.raj(a)intel.com are
queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch
This is a note to let you know that I've just added the patch titled
x86/microcode: Get rid of struct apply_microcode_ctx
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum…
The filename of the patch is:
x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable(a)vger.kernel.org> know about it.
>From 854857f5944c59a881ff607b37ed9ed41d031a3b Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp(a)suse.de>
Date: Wed, 28 Feb 2018 11:28:40 +0100
Subject: x86/microcode: Get rid of struct apply_microcode_ctx
From: Borislav Petkov <bp(a)suse.de>
commit 854857f5944c59a881ff607b37ed9ed41d031a3b upstream.
It is a useless remnant from earlier times. Use the ucode_state enum
directly.
No functional change.
Signed-off-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Tested-by: Ashok Raj <ashok.raj(a)intel.com>
Cc: Arjan Van De Ven <arjan.van.de.ven(a)intel.com>
Link: https://lkml.kernel.org/r/20180228102846.13447-2-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
arch/x86/kernel/cpu/microcode/core.c | 19 ++++++++-----------
1 file changed, 8 insertions(+), 11 deletions(-)
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -373,26 +373,23 @@ static int collect_cpu_info(int cpu)
return ret;
}
-struct apply_microcode_ctx {
- enum ucode_state err;
-};
-
static void apply_microcode_local(void *arg)
{
- struct apply_microcode_ctx *ctx = arg;
+ enum ucode_state *err = arg;
- ctx->err = microcode_ops->apply_microcode(smp_processor_id());
+ *err = microcode_ops->apply_microcode(smp_processor_id());
}
static int apply_microcode_on_target(int cpu)
{
- struct apply_microcode_ctx ctx = { .err = 0 };
+ enum ucode_state err;
int ret;
- ret = smp_call_function_single(cpu, apply_microcode_local, &ctx, 1);
- if (!ret)
- ret = ctx.err;
-
+ ret = smp_call_function_single(cpu, apply_microcode_local, &err, 1);
+ if (!ret) {
+ if (err == UCODE_ERROR)
+ ret = 1;
+ }
return ret;
}
Patches currently in stable-queue which might be from bp(a)suse.de are
queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/edac-mv64x60-fix-an-error-handling-path.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch
This is a note to let you know that I've just added the patch titled
x86/microcode: Fix CPU synchronization routine
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum…
The filename of the patch is:
x86-microcode-fix-cpu-synchronization-routine.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable(a)vger.kernel.org> know about it.
>From bb8c13d61a629276a162c1d2b1a20a815cbcfbb7 Mon Sep 17 00:00:00 2001
From: Borislav Petkov <bp(a)suse.de>
Date: Wed, 14 Mar 2018 19:36:15 +0100
Subject: x86/microcode: Fix CPU synchronization routine
From: Borislav Petkov <bp(a)suse.de>
commit bb8c13d61a629276a162c1d2b1a20a815cbcfbb7 upstream.
Emanuel reported an issue with a hang during microcode update because my
dumb idea to use one atomic synchronization variable for both rendezvous
- before and after update - was simply bollocks:
microcode: microcode_reload_late: late_cpus: 4
microcode: __reload_late: cpu 2 entered
microcode: __reload_late: cpu 1 entered
microcode: __reload_late: cpu 3 entered
microcode: __reload_late: cpu 0 entered
microcode: __reload_late: cpu 1 left
microcode: Timeout while waiting for CPUs rendezvous, remaining: 1
CPU1 above would finish, leave and the others will still spin waiting for
it to join.
So do two synchronization atomics instead, which makes the code a lot more
straightforward.
Also, since the update is serialized and it also takes quite some time per
microcode engine, increase the exit timeout by the number of CPUs on the
system.
That's ok because the moment all CPUs are done, that timeout will be cut
short.
Furthermore, panic when some of the CPUs timeout when returning from a
microcode update: we can't allow a system with not all cores updated.
Also, as an optimization, do not do the exit sync if microcode wasn't
updated.
Reported-by: Emanuel Czirai <xftroxgpx(a)protonmail.com>
Signed-off-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Tested-by: Emanuel Czirai <xftroxgpx(a)protonmail.com>
Tested-by: Ashok Raj <ashok.raj(a)intel.com>
Tested-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Link: https://lkml.kernel.org/r/20180314183615.17629-2-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
arch/x86/kernel/cpu/microcode/core.c | 68 +++++++++++++++++++++--------------
1 file changed, 41 insertions(+), 27 deletions(-)
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -517,7 +517,29 @@ static int check_online_cpus(void)
return -EINVAL;
}
-static atomic_t late_cpus;
+static atomic_t late_cpus_in;
+static atomic_t late_cpus_out;
+
+static int __wait_for_cpus(atomic_t *t, long long timeout)
+{
+ int all_cpus = num_online_cpus();
+
+ atomic_inc(t);
+
+ while (atomic_read(t) < all_cpus) {
+ if (timeout < SPINUNIT) {
+ pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n",
+ all_cpus - atomic_read(t));
+ return 1;
+ }
+
+ ndelay(SPINUNIT);
+ timeout -= SPINUNIT;
+
+ touch_nmi_watchdog();
+ }
+ return 0;
+}
/*
* Returns:
@@ -527,30 +549,16 @@ static atomic_t late_cpus;
*/
static int __reload_late(void *info)
{
- unsigned int timeout = NSEC_PER_SEC;
- int all_cpus = num_online_cpus();
int cpu = smp_processor_id();
enum ucode_state err;
int ret = 0;
- atomic_dec(&late_cpus);
-
/*
* Wait for all CPUs to arrive. A load will not be attempted unless all
* CPUs show up.
* */
- while (atomic_read(&late_cpus)) {
- if (timeout < SPINUNIT) {
- pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n",
- atomic_read(&late_cpus));
- return -1;
- }
-
- ndelay(SPINUNIT);
- timeout -= SPINUNIT;
-
- touch_nmi_watchdog();
- }
+ if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC))
+ return -1;
spin_lock(&update_lock);
apply_microcode_local(&err);
@@ -558,15 +566,22 @@ static int __reload_late(void *info)
if (err > UCODE_NFOUND) {
pr_warn("Error reloading microcode on CPU %d\n", cpu);
- ret = -1;
- } else if (err == UCODE_UPDATED) {
+ return -1;
+ /* siblings return UCODE_OK because their engine got updated already */
+ } else if (err == UCODE_UPDATED || err == UCODE_OK) {
ret = 1;
+ } else {
+ return ret;
}
- atomic_inc(&late_cpus);
-
- while (atomic_read(&late_cpus) != all_cpus)
- cpu_relax();
+ /*
+ * Increase the wait timeout to a safe value here since we're
+ * serializing the microcode update and that could take a while on a
+ * large number of CPUs. And that is fine as the *actual* timeout will
+ * be determined by the last CPU finished updating and thus cut short.
+ */
+ if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC * num_online_cpus()))
+ panic("Timeout during microcode update!\n");
return ret;
}
@@ -579,12 +594,11 @@ static int microcode_reload_late(void)
{
int ret;
- atomic_set(&late_cpus, num_online_cpus());
+ atomic_set(&late_cpus_in, 0);
+ atomic_set(&late_cpus_out, 0);
ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask);
- if (ret < 0)
- return ret;
- else if (ret > 0)
+ if (ret > 0)
microcode_check();
return ret;
Patches currently in stable-queue which might be from bp(a)suse.de are
queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/edac-mv64x60-fix-an-error-handling-path.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch
This is a note to let you know that I've just added the patch titled
x86/microcode: Do not upload microcode if CPUs are offline
to the 4.15-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=sum…
The filename of the patch is:
x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
and it can be found in the queue-4.15 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable(a)vger.kernel.org> know about it.
>From 30ec26da9967d0d785abc24073129a34c3211777 Mon Sep 17 00:00:00 2001
From: Ashok Raj <ashok.raj(a)intel.com>
Date: Wed, 28 Feb 2018 11:28:43 +0100
Subject: x86/microcode: Do not upload microcode if CPUs are offline
From: Ashok Raj <ashok.raj(a)intel.com>
commit 30ec26da9967d0d785abc24073129a34c3211777 upstream.
Avoid loading microcode if any of the CPUs are offline, and issue a
warning. Having different microcode revisions on the system at any time
is outright dangerous.
[ Borislav: Massage changelog. ]
Signed-off-by: Ashok Raj <ashok.raj(a)intel.com>
Signed-off-by: Borislav Petkov <bp(a)suse.de>
Signed-off-by: Thomas Gleixner <tglx(a)linutronix.de>
Tested-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Tested-by: Ashok Raj <ashok.raj(a)intel.com>
Reviewed-by: Tom Lendacky <thomas.lendacky(a)amd.com>
Cc: Arjan Van De Ven <arjan.van.de.ven(a)intel.com>
Link: http://lkml.kernel.org/r/1519352533-15992-4-git-send-email-ashok.raj@intel.…
Link: https://lkml.kernel.org/r/20180228102846.13447-5-bp@alien8.de
Signed-off-by: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org>
---
arch/x86/kernel/cpu/microcode/core.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -486,6 +486,16 @@ static void __exit microcode_dev_exit(vo
/* fake device for request_firmware */
static struct platform_device *microcode_pdev;
+static int check_online_cpus(void)
+{
+ if (num_online_cpus() == num_present_cpus())
+ return 0;
+
+ pr_err("Not all CPUs online, aborting microcode update.\n");
+
+ return -EINVAL;
+}
+
static enum ucode_state reload_for_cpu(int cpu)
{
struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
@@ -519,7 +529,13 @@ static ssize_t reload_store(struct devic
return size;
get_online_cpus();
+
+ ret = check_online_cpus();
+ if (ret)
+ goto put;
+
mutex_lock(µcode_mutex);
+
for_each_online_cpu(cpu) {
tmp_ret = reload_for_cpu(cpu);
if (tmp_ret > UCODE_NFOUND) {
@@ -538,6 +554,8 @@ static ssize_t reload_store(struct devic
microcode_check();
mutex_unlock(µcode_mutex);
+
+put:
put_online_cpus();
if (!ret)
Patches currently in stable-queue which might be from ashok.raj(a)intel.com are
queue-4.15/x86-microcode-intel-check-microcode-revision-before-updating-sibling-threads.patch
queue-4.15/x86-microcode-attempt-late-loading-only-when-new-microcode-is-present.patch
queue-4.15/x86-microcode-propagate-return-value-from-updating-functions.patch
queue-4.15/x86-cpu-check-cpu-feature-bits-after-microcode-upgrade.patch
queue-4.15/x86-microcode-intel-writeback-and-invalidate-caches-before-updating-microcode.patch
queue-4.15/x86-microcode-intel-look-into-the-patch-cache-first.patch
queue-4.15/x86-microcode-request-microcode-on-the-bsp.patch
queue-4.15/x86-microcode-get-rid-of-struct-apply_microcode_ctx.patch
queue-4.15/x86-microcode-fix-cpu-synchronization-routine.patch
queue-4.15/x86-microcode-synchronize-late-microcode-loading.patch
queue-4.15/x86-microcode-do-not-upload-microcode-if-cpus-are-offline.patch
queue-4.15/x86-cpu-add-a-microcode-loader-callback.patch