On 10/07/2025 16:23, Andreas Schwab wrote:
On Jul 10 2025, Clément Léger wrote:
On 10/07/2025 15:53, Andreas Schwab wrote:
On Jul 10 2025, Clément Léger wrote:
This selftest tests all the currently emulated instructions (except for the RV32 compressed ones which are left as a future exercise for a RV32 user). For the FPU instructions, all the FPU registers are tested.
If that didn't catch the missing sign extension that I just fixed in https://lore.kernel.org/linux-riscv/mvmikk0goil.fsf@suse.de, you should consider extending the tests.
Hi Andreas, you link doesn't work and I didn't find anything about sign extension except a patch you wrote for arch_cmpxg().
lore.k.o is currently down, here's the patch I have sent:
From 77c8255da24ee4fac54e2371594d7210d1ddee19 Mon Sep 17 00:00:00 2001 From: Andreas Schwab schwab@suse.de Date: Thu, 10 Jul 2025 13:52:35 +0200 Subject: [PATCH] riscv: traps_misaligned: properly sign extend value in misaligned load handler
Add missing cast to signed long.
Signed-off-by: Andreas Schwab schwab@suse.de
arch/riscv/kernel/traps_misaligned.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 93043924fe6c..f760e4fcc052 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -461,7 +461,7 @@ static int handle_scalar_misaligned_load(struct pt_regs *regs) } if (!fp)
SET_RD(insn, regs, val.data_ulong << shift >> shift);
SET_RD(insn, regs, (long)(val.data_ulong << shift) >> shift);
Hi Andreas,
Nice catch, it seems like it was fixed in OpenSBI but never backported in the kernel. As you suggested, I'll modify the test to test the sign extension.
Thanks,
Clément
else if (len == 8) set_f64_rd(insn, regs, val.data_u64); else