[PATCH v3 05/21] arm64/esr: Document ISS for ZT0 being disabled

SME2 defines a new ISS code for use when trapping acesses to ZT0, add a definition for it.

Signed-off-by: Mark Brown broonie@kernel.org --- arch/arm64/include/asm/esr.h | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/include/asm/esr.h b/arch/arm64/include/asm/esr.h index 15b34fbfca66..5f3271e9d5df 100644 --- a/arch/arm64/include/asm/esr.h +++ b/arch/arm64/include/asm/esr.h @@ -341,6 +341,7 @@ #define ESR_ELx_SME_ISS_ILL 1 #define ESR_ELx_SME_ISS_SM_DISABLED 2 #define ESR_ELx_SME_ISS_ZA_DISABLED 3 +#define ESR_ELx_SME_ISS_ZT_DISABLED 4

#ifndef __ASSEMBLY__ #include <asm/types.h>