On Tue, Jul 01, 2025 at 01:00:47PM -0700, Jesse Taube wrote:
+#define SBI_DBTR_TDATA1_TYPE_SHIFT (__riscv_xlen - 4)
I just double checked and see that this shift is 4 less than xlen, so...
+enum McontrolType {
- SBI_DBTR_TDATA1_TYPE_NONE = (0UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_LEGACY = (1UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_MCONTROL = (2UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_ICOUNT = (3UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_ITRIGGER = (4UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_ETRIGGER = (5UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_MCONTROL6 = (6UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_TMEXTTRIGGER = (7UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_RESERVED0 = (8UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_RESERVED1 = (9UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_RESERVED2 = (10UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_RESERVED3 = (11UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_CUSTOM0 = (12UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_CUSTOM1 = (13UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_CUSTOM2 = (14UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
- SBI_DBTR_TDATA1_TYPE_DISABLED = (15UL << SBI_DBTR_TDATA1_TYPE_SHIFT),
...all these will require unsigned long (as the UL's provide), but that means...
+static unsigned long gen_tdata1(enum McontrolType type, enum Tdata1Value value, enum Tdata1Mode mode) +{
- switch (type) {
- case SBI_DBTR_TDATA1_TYPE_MCONTROL:
return gen_tdata1_mcontrol(mode, value) | mcontrol_size(SIZE_32BIT);
- case SBI_DBTR_TDATA1_TYPE_MCONTROL6:
return gen_tdata1_mcontrol6(mode, value) | mcontrol6_size(SIZE_32BIT);
- default:
assert_msg(false, "Invalid mcontrol type: %u", (int)type);
...my suggestion here was wrong for rv64. We need
assert_msg(false, "Invalid mcontrol type: %lu", (unsigned long)type);
I've fixed it up while applying to riscv/sbi
https://gitlab.com/jones-drew/kvm-unit-tests/-/commits/riscv/sbi
Thanks, drew