On Thu, Apr 11, 2024 at 09:11:21PM -0700, Charlie Jenkins wrote:
xtheadvector is not vector 1.0 compatible, but it can leverage all of the same save/restore routines as vector plus riscv_v_first_use_handler(). vector 1.0 and xtheadvector are mutually exclusive so there is no risk of overlap.
I think this not okay to do - if a program checks hwcap to see if vector is supported they'll get told it is on T-Head system where only the 0.7.1 is.
Signed-off-by: Charlie Jenkins charlie@rivosinc.com
arch/riscv/kernel/cpufeature.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 41a4d2028428..59f628b1341c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -647,9 +647,13 @@ static void __init riscv_fill_hwcap_from_isa_string(unsigned long *isa2hwcap) * Many vendors with T-Head CPU cores which implement the 0.7.1 * version of the vector specification put "v" into their DTs. * CPU cores with the ratified spec will contain non-zero
* marchid.
* marchid. Only allow "v" to be set if xtheadvector is present.
if (acpi_disabled && this_vendorid == THEAD_VENDOR_ID &&
if (__riscv_isa_vendor_extension_available(isavendorinfo->isa,RISCV_ISA_VENDOR_EXT_XTHEADVECTOR)) {this_hwcap |= isa2hwcap[RISCV_ISA_EXT_v];set_bit(RISCV_ISA_EXT_v, isainfo->isa);} else if (acpi_disabled && this_vendorid == THEAD_VENDOR_ID &&@@ -776,6 +780,15 @@ static int __init riscv_fill_hwcap_from_ext_list(unsigned long *isa2hwcap) of_node_put(cpu_node);
/** Enable kernel vector routines if xtheadvector is present*/if (__riscv_isa_vendor_extension_available(isavendorinfo->isa,RISCV_ISA_VENDOR_EXT_XTHEADVECTOR)) {this_hwcap |= isa2hwcap[RISCV_ISA_EXT_v];set_bit(RISCV_ISA_EXT_v, isainfo->isa);}- /*
- All "okay" harts should have same isa. Set HWCAP based on
- common capabilities of every "okay" hart, in case they don't.
-- 2.44.0