On Mon, Oct 20, 2025 at 12:20:46PM +0800, Xu Lu wrote:
This patch adds support for the Zalasr ISA extension, which supplies the real load acquire/store release instructions.
The specification can be found here: https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc
This patch seires has been tested with ltp on Qemu with Brensan's zalasr support patch[1].
Some false positive spacing error happens during patch checking. Thus I CCed maintainers of checkpatch.pl as well.
[1] https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytVEcz4F-gfvCOX...
v4:
- Apply acquire/release semantics to arch_atomic operations. Thanks
to Andrea.
Perhaps I wasn't clear enough, sorry, but I did mean my suggestion (specifically, the use of .aq/.rl annotations) to be conditional on zalasr. Same observation for xchg/cmpxchg below. IOW, I really expected this series to introduce _no changes_ to our lowerings when !zalasr. If any !zalasr-changes are needed, I'd suggest isolating /submitting them in dedicated patches.
But other than that, this looks pretty good to me. Perhaps something else to consider for zalasr is our lowering of smp_cond_load_acquire() (can't spot an actual bug now, but recall the principle "zalasr -> use .aq/.rl annotations ..."): riscv currently uses the "generic", fence- based implementation from include/asm-generic/barrier.h; compare that with e.g. the implementation from arch/arm64/include/asm/barrier.h .
Andrea
v3:
- Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations
so as to ensure FENCE.TSO ordering between operations which precede the UNLOCK+LOCK sequence and operations which follow the sequence. Thanks to Andrea.
- Support hwprobe of Zalasr.
- Allow Zalasr extensions for Guest/VM.
v2:
- Adjust the order of Zalasr and Zalrsc in dt-bindings. Thanks to
Conor.
Xu Lu (10): riscv: Add ISA extension parsing for Zalasr dt-bindings: riscv: Add Zalasr ISA extension description riscv: hwprobe: Export Zalasr extension riscv: Introduce Zalasr instructions riscv: Apply Zalasr to smp_load_acquire/smp_store_release riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations riscv: Apply acquire/release semantics to arch_atomic operations riscv: Remove arch specific __atomic_acquire/release_fence RISC-V: KVM: Allow Zalasr extensions for Guest/VM RISC-V: KVM: selftests: Add Zalasr extensions to get-reg-list test
Documentation/arch/riscv/hwprobe.rst | 5 +- .../devicetree/bindings/riscv/extensions.yaml | 5 + arch/riscv/include/asm/atomic.h | 70 ++++++++- arch/riscv/include/asm/barrier.h | 91 +++++++++-- arch/riscv/include/asm/cmpxchg.h | 144 +++++++++--------- arch/riscv/include/asm/fence.h | 4 - arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/insn-def.h | 79 ++++++++++ arch/riscv/include/uapi/asm/hwprobe.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + arch/riscv/kernel/sys_hwprobe.c | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 + .../selftests/kvm/riscv/get-reg-list.c | 4 + 14 files changed, 314 insertions(+), 95 deletions(-)
-- 2.20.1