Oliver Upton oupton@kernel.org writes:
On Tue, Dec 09, 2025 at 08:51:17PM +0000, Colton Lewis wrote:
Because ARM hardware is not yet capable of direct interrupt injection
PPI injection, it can do LPIs just fine.
Clarification noted. I will update the message.
@@ -961,6 +964,12 @@ static irqreturn_t armv8pmu_handle_irq(struct arm_pmu *cpu_pmu) */ perf_event_overflow(event, &data, regs); }
- govf = pmovsr & kvm_pmu_guest_counter_mask(cpu_pmu);
- if (kvm_pmu_is_partitioned(cpu_pmu) && govf)
kvm_pmu_handle_guest_irq(govf);
The state ownership of this whole interaction is very odd. I would much rather that KVM have full ownership of the range of counters while the guest is loaded. By that I mean the PMUv3 driver only clears overflows on PMCs that it owns and KVM will do the same on the back of the IRQ.
If I'm understanding correctly this is a code location concern, because the host driver has to handle the interrupt in this function or a callee of this function.
I will do it that way. It would be duplicating a small amount of logic in kvm_pmu_handle_guest_irq() but I see your reasoning.
Similarly, KVM should be leaving the "guest" range of counters in a non-overflow condition at vcpu_put().
Noted from your comments on kvm_pmu_put()
Thanks, Oliver