On Wed, Sep 06, 2023 at 06:33:14PM +0000, Puranjay Mohan wrote:
The cpuv4 added the support of an instruction that is similar to load but also sign-extends the result after the load.
BPF_MEMSX | <size> | BPF_LDX means dst = *(signed size *) (src + offset) here <size> can be one of BPF_B, BPF_H, BPF_W.
ARM32 has instructions to load a byte or a half word with sign extension into a 32bit register. As the JIT uses two 32 bit registers to simulate a 64-bit BPF register, an extra instruction is emitted to sign-extent the result up to the second register.
Signed-off-by: Puranjay Mohan puranjay12@gmail.com
Reviewed-by: Russell King (Oracle) rmk+kernel@armlinux.org.uk
but see below...
Thanks!
+static inline void emit_ldsx_r(const s8 dst[], const s8 src,
s16 off, struct jit_ctx *ctx, const u8 sz){- const s8 *tmp = bpf2a32[TMP_REG_1];
- const s8 *rd = is_stacked(dst_lo) ? tmp : dst;
- s8 rm = src;
- int add_off;
- if (!is_ldst_imm8(off, sz)) {
I think a comment here would be useful: /* offset does not fit in the load/store immediate, * construct an ADD instruction to apply the offset. */
otherwise I'm sure someone will question why we aren't handling the zero case below... since zero will fit in the load/store immediate.