On Mon, Jan 13, 2025 at 04:36:33PM +0800, Yunhui Cui wrote:
Enabling cbo.clean and cbo.flush in user mode makes it more convenient to manage the cache state and achieve better performance.
Reviewed-by: Andrew Jones ajones@ventanamicro.com Signed-off-by: Yunhui Cui cuiyunhui@bytedance.com
arch/riscv/kernel/cpufeature.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c0916ed318c2..60d180b98f52 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -30,6 +30,7 @@ #define NUM_ALPHA_EXTS ('z' - 'a' + 1) static bool any_cpu_has_zicboz; +static bool any_cpu_has_zicbom; unsigned long elf_hwcap __read_mostly; @@ -87,6 +88,8 @@ static int riscv_ext_zicbom_validate(const struct riscv_isa_ext_data *data, pr_err("Zicbom disabled as cbom-block-size present, but is not a power-of-2\n"); return -EINVAL; }
- any_cpu_has_zicbom = true; return 0;
} @@ -944,6 +947,11 @@ void __init riscv_user_isa_enable(void) current->thread.envcfg |= ENVCFG_CBZE; else if (any_cpu_has_zicboz) pr_warn("Zicboz disabled as it is unavailable on some harts\n");
- if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZICBOM))
current->thread.envcfg |= ENVCFG_CBCFE;- else if (any_cpu_has_zicbom)
pr_warn("Zicbom disabled as it is unavailable on some harts\n");}
#ifdef CONFIG_RISCV_ALTERNATIVE
2.39.2
Please use a cover letter with a changelog or at least changelogs under the '---' of each patch.
Thanks, drew