On Fri, Dec 09, 2022, Oliver Upton wrote:
An interesting feature of the Arm architecture is that the stage-1 MMU supports two distinct VA regions, controlled by TTBR{0,1}_EL1. As KVM selftests on arm64 only uses TTBR0_EL1, the VA space is constrained to [0, 2^(va_bits)). This is different from other architectures that allow for addressing low and high regions of the VA space from a single page table.
KVM selftests' VA space allocator presumes the valid address range is split between low and high memory based the MSB, which of course is a poor match for arm64's TTBR0 region.
Add a helper that correctly handles both addressing schemes with a comment describing each.
Signed-off-by: Oliver Upton oliver.upton@linux.dev
Thanks much! Looks awesome, especially the comment!
Reviewed-by: Sean Christopherson seanjc@google.com
.../selftests/kvm/include/kvm_util_base.h | 1 + tools/testing/selftests/kvm/lib/kvm_util.c | 49 ++++++++++++++++--- 2 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h b/tools/testing/selftests/kvm/include/kvm_util_base.h index 6cd86da698b3..b193863d754f 100644 --- a/tools/testing/selftests/kvm/include/kvm_util_base.h +++ b/tools/testing/selftests/kvm/include/kvm_util_base.h @@ -103,6 +103,7 @@ struct kvm_vm { struct sparsebit *vpages_mapped; bool has_irqchip; bool pgd_created;
- bool has_split_va_space; vm_paddr_t ucall_mmio_addr; vm_paddr_t pgd; vm_vaddr_t gdt;
diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c index a256ec67aff6..53d15f32f220 100644 --- a/tools/testing/selftests/kvm/lib/kvm_util.c +++ b/tools/testing/selftests/kvm/lib/kvm_util.c @@ -186,6 +186,43 @@ const struct vm_guest_mode_params vm_guest_mode_params[] = { _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params) == NUM_VM_MODES, "Missing new mode params?"); +/*
- Initializes vm->vpages_valid to match the canonical VA space of the
- architecture.
- Most architectures split the range addressed by a single page table into a
- low and high region based on the MSB of the VA. On architectures with this
- behavior the VA region spans [0, 2^(va_bits - 1)), [-(2^(va_bits - 1), -1].
- arm64 is a bit different from the rest of the crowd, as the low and high
- regions of the VA space are addressed by distinct paging structures
- (TTBR{0,1}_EL1).
Oooh, they're different CR3s in x86 terminology?