On 5/15/25 1:22 AM, Clément Léger wrote:
SBI_FWFT_MISALIGNED_DELEG needs hedeleg to be modified to delegate misaligned load/store exceptions. Save and restore it during CPU load/put.
Signed-off-by: Clément Léger cleger@rivosinc.com Reviewed-by: Deepak Gupta debug@rivosinc.com Reviewed-by: Andrew Jones ajones@ventanamicro.com
arch/riscv/kvm/vcpu_sbi_fwft.c | 41 ++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+)
diff --git a/arch/riscv/kvm/vcpu_sbi_fwft.c b/arch/riscv/kvm/vcpu_sbi_fwft.c index b0f66c7bf010..6770c043bbcb 100644 --- a/arch/riscv/kvm/vcpu_sbi_fwft.c +++ b/arch/riscv/kvm/vcpu_sbi_fwft.c @@ -14,6 +14,8 @@ #include <asm/kvm_vcpu_sbi.h> #include <asm/kvm_vcpu_sbi_fwft.h> +#define MIS_DELEG (BIT_ULL(EXC_LOAD_MISALIGNED) | BIT_ULL(EXC_STORE_MISALIGNED))
- struct kvm_sbi_fwft_feature { /**
- @id: Feature ID
@@ -68,7 +70,46 @@ static bool kvm_fwft_is_defined_feature(enum sbi_fwft_feature_t feature) return false; } +static bool kvm_sbi_fwft_misaligned_delegation_supported(struct kvm_vcpu *vcpu) +{
- return misaligned_traps_can_delegate();
+}
+static long kvm_sbi_fwft_set_misaligned_delegation(struct kvm_vcpu *vcpu,
struct kvm_sbi_fwft_config *conf,
unsigned long value)
+{
- struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
- if (value == 1) {
cfg->hedeleg |= MIS_DELEG;
csr_set(CSR_HEDELEG, MIS_DELEG);
- } else if (value == 0) {
cfg->hedeleg &= ~MIS_DELEG;
csr_clear(CSR_HEDELEG, MIS_DELEG);
- } else {
return SBI_ERR_INVALID_PARAM;
- }
- return SBI_SUCCESS;
+}
+static long kvm_sbi_fwft_get_misaligned_delegation(struct kvm_vcpu *vcpu,
struct kvm_sbi_fwft_config *conf,
unsigned long *value)
+{
- *value = (csr_read(CSR_HEDELEG) & MIS_DELEG) == MIS_DELEG;
- return SBI_SUCCESS;
+}
- static const struct kvm_sbi_fwft_feature features[] = {
- {
.id = SBI_FWFT_MISALIGNED_EXC_DELEG,
.supported = kvm_sbi_fwft_misaligned_delegation_supported,
.set = kvm_sbi_fwft_set_misaligned_delegation,
.get = kvm_sbi_fwft_get_misaligned_delegation,
- }, };
static struct kvm_sbi_fwft_config *
LGTM. Reviewed-by: Atish Patra atishp@rivosinc.com