Re: [PATCH v4] selftests: riscv: add misaligned access testing

On Jul 10 2025, Clément Léger wrote:

This selftest tests all the currently emulated instructions (except for the RV32 compressed ones which are left as a future exercise for a RV32 user). For the FPU instructions, all the FPU registers are tested.

If that didn't catch the missing sign extension that I just fixed in https://lore.kernel.org/linux-riscv/mvmikk0goil.fsf@suse.de, you should consider extending the tests.