Migrate xandespmu out of riscv_isa_ext and into a new Andes-specific vendor namespace.
Signed-off-by: Charlie Jenkins charlie@rivosinc.com --- arch/riscv/include/asm/hwcap.h | 4 +++- arch/riscv/include/asm/vendor_extensions.h | 3 +++ arch/riscv/kernel/cpufeature.c | 1 - arch/riscv/kernel/vendor_extensions.c | 4 ++++ arch/riscv/kernel/vendor_extensions/Makefile | 1 + arch/riscv/kernel/vendor_extensions/andes_extensions.c | 13 +++++++++++++ drivers/perf/riscv_pmu_sbi.c | 7 ++++--- 7 files changed, 28 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 38157be5becd..4b986e4b56f2 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -80,7 +80,6 @@ #define RISCV_ISA_EXT_ZFA 71 #define RISCV_ISA_EXT_ZTSO 72 #define RISCV_ISA_EXT_ZACAS 73 -#define RISCV_ISA_EXT_XANDESPMU 74
#define RISCV_ISA_EXT_XLINUXENVCFG 127
@@ -103,6 +102,9 @@ */ #define RISCV_ISA_VENDOR_EXT_BASE 0x8000
+/* Andes Vendor Extensions */ +#define RISCV_ISA_VENDOR_EXT_XANDESPMU 0x8000 + /* THead Vendor Extensions */ #define RISCV_ISA_VENDOR_EXT_XTHEADVECTOR 0x8000
diff --git a/arch/riscv/include/asm/vendor_extensions.h b/arch/riscv/include/asm/vendor_extensions.h index 0a1955e1c900..33a430cc50cb 100644 --- a/arch/riscv/include/asm/vendor_extensions.h +++ b/arch/riscv/include/asm/vendor_extensions.h @@ -9,6 +9,9 @@ extern const struct riscv_isa_ext_data riscv_isa_vendor_ext_thead[]; extern const size_t riscv_isa_vendor_ext_count_thead;
+extern const struct riscv_isa_ext_data riscv_isa_vendor_ext_andes[]; +extern const size_t riscv_isa_vendor_ext_count_andes; + bool get_isa_vendor_ext(unsigned long vendorid, const struct riscv_isa_ext_data **isa_vendor_ext, size_t *count);
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 799ec2d2e9e0..949c06970c4f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -321,7 +321,6 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_EXT_XANDESPMU), };
const size_t riscv_isa_ext_count = ARRAY_SIZE(riscv_isa_ext); diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c index 3a8a6c6dd34e..c5ca02ce1bb1 100644 --- a/arch/riscv/kernel/vendor_extensions.c +++ b/arch/riscv/kernel/vendor_extensions.c @@ -21,6 +21,10 @@ bool __init get_isa_vendor_ext(unsigned long vendorid, *isa_vendor_ext = riscv_isa_vendor_ext_thead; *count = riscv_isa_vendor_ext_count_thead; break; + case ANDES_VENDOR_ID: + *isa_vendor_ext = riscv_isa_vendor_ext_andes; + *count = riscv_isa_vendor_ext_count_andes; + break; default: *isa_vendor_ext = NULL; *count = 0; diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile index dcf3de8d4658..8014594aafa1 100644 --- a/arch/riscv/kernel/vendor_extensions/Makefile +++ b/arch/riscv/kernel/vendor_extensions/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only
+obj-y += andes_extensions.o obj-y += thead_extensions.o diff --git a/arch/riscv/kernel/vendor_extensions/andes_extensions.c b/arch/riscv/kernel/vendor_extensions/andes_extensions.c new file mode 100644 index 000000000000..b7450f99bfb5 --- /dev/null +++ b/arch/riscv/kernel/vendor_extensions/andes_extensions.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include <asm/cpufeature.h> +#include <asm/hwcap.h> +#include <asm/vendor_extensions.h> + +#include <linux/array_size.h> + +const struct riscv_isa_ext_data riscv_isa_vendor_ext_andes[] = { + __RISCV_ISA_EXT_DATA(xandespmu, RISCV_ISA_VENDOR_EXT_XANDESPMU), +}; + +const size_t riscv_isa_vendor_ext_count_andes = ARRAY_SIZE(riscv_isa_vendor_ext_andes); diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 8cbe6e5f9c39..13e37296cb5f 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -24,6 +24,7 @@ #include <asm/errata_list.h> #include <asm/sbi.h> #include <asm/cpufeature.h> +#include <asm/vendorid_list.h>
#define ALT_SBI_PMU_OVERFLOW(__ovl) \ asm volatile(ALTERNATIVE_2( \ @@ -32,7 +33,7 @@ asm volatile(ALTERNATIVE_2( \ THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ CONFIG_ERRATA_THEAD_PMU, \ "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \ - 0, RISCV_ISA_EXT_XANDESPMU, \ + ANDES_VENDOR_ID, RISCV_ISA_VENDOR_EXT_XANDESPMU, \ CONFIG_ANDES_CUSTOM_PMU) \ : "=r" (__ovl) : \ : "memory") @@ -41,7 +42,7 @@ asm volatile(ALTERNATIVE_2( \ asm volatile(ALTERNATIVE( \ "csrc " __stringify(CSR_IP) ", %0\n\t", \ "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \ - 0, RISCV_ISA_EXT_XANDESPMU, \ + ANDES_VENDOR_ID, RISCV_ISA_VENDOR_EXT_XANDESPMU, \ CONFIG_ANDES_CUSTOM_PMU) \ : : "r"(__irq_mask) \ : "memory") @@ -837,7 +838,7 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde riscv_cached_mimpid(0) == 0) { riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU; riscv_pmu_use_irq = true; - } else if (riscv_isa_extension_available(NULL, XANDESPMU) && + } else if (riscv_isa_vendor_extension_available(NULL, XANDESPMU) && IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) { riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI; riscv_pmu_use_irq = true;