Hi Richard,<br>  As per the discussion at this mornings call; I&#39;ve reread the TRM and I agree with you about the LSLS being the same speed as the TST. (1 cycle)<br><br>However as we agreed, the uxtb does look like 2 cycles v the AND 1 cycle.<br>
<br>On the space v perf theme, one thing that would be interesting to know is whether there are any icache/issue stage limitations;<br>i.e. if I have a stream of 32-bit Thumb-2 instructions that are all listed as 1 cycle and are all in i-cache, can they be fetched<br>
and issued fast enough, or is there a performance advantage to short instructions?<br><br>Dave<br><br>