1 Dec
2010
1 Dec
'10
4:09 p.m.
On Wed, Dec 01, 2010 at 11:24:01AM +0000, Julian Brown wrote:
PowerPC also has load/store multiple, but I guess they are generated in the same phase as for ARM. Maybe there are other architectures that do that allocate contiguous register but earlier?
I don't know about other architectures which do that.
PowerPC essentially restricts load/store multiple instruction use to the prologue/epilogue. There are some tricks it can play with load-string instructions, but those are restricted to hard registers (see movmemsi_$Nreg patterns in rs6000.md). There's also the *ldmsi$N patterns in rs6000.md, but it's not clear to me what conditions those get generated under (combine?).
-Nathan