Hi,<div><br></div><div>I think I have identified some issues with the atomic builtins, but I want your advises.</div><div>For instance :</div><div><br></div><div>A:  __atomic_store_n (addr, val, __ATOMIC_SEQ_CST);</div><div>
<br></div><div>gives the armv7 code:</div><div><br></div><div>DMB     sy<br></div><div>STR     r1, [r0]<br></div><div>DMB     sy<br></div><div><br></div><div>but if I have well understood, the DMBs instructions only provide the property that the</div>
<div>code is sequentially consistent, but not the atomicity for which we have to use the </div><div>LDREX/STREX instructions. Thus I think that the code should be :</div><div><br></div><div>    DMB     sy</div><div>1: LDREX  r2, [r0]<br>
</div><div>    STREX  r1, r2, [r0]</div><div>    TEQ      r1, #0</div><div>    BNE      1b</div><div><br></div><div>B: __atomic_load_n (addr, __ATOMIC_ACQUIRE);</div><div><br></div><div>gives the armv7 code:</div><div><br>
</div><div>DMB     sy</div><div>LDR     r0, [r0]</div><div><br></div><div>but the load-acquire semantique specifies that all loads and stores appearing in program order</div><div>after the load-acquire will be observed after the load-acquire, thus the DMB should be after the</div>
<div>LDR, no ?</div><div><br></div><div>--</div><div>Yvan</div><div><br></div>