== Progress ==
* Zero/sign extension elimination (TCWG-15) (7/10) - regression tested and fixed all the issues - final bootstrap and regression testing for arm and x86_64 are ongoing - will post the patch for comment after checking the results
* benchmarking (TCWG-468) (1/10) - Set-up chrome-book for a15 release benchmarking
* SAH1 performance (TCWG-413) (2/10) - Christophe noted regression for aarch64_be due to clean-up patch. - register_move_cost hook in aarch64 does not handle all the cases (CORE_REGS and POINTER_REGS) and due to this, it calculates FP2FP cost for these classes . With CORE_REGS gone, costs for register classes are now different. Cost table needs adjustment.
* FENV for C11 TCWG-447 - Committed ARM part.
== Plan == * Benchmarking. * Upstream zero/sign extension elimination activities. * sha1 performance.