1 Nov
2019
1 Nov
'19
2:06 p.m.
On Fri, 1 Nov 2019 at 13:52, Richard Henderson richard.henderson@linaro.org wrote:
The case I'm trying to debug, guest EL1 timer, TGE == 0 && IMO == 1. Which, according to D1-10 routes to EL2, and according to D1-13 is not masked by PSTATE.
I really don't understand how this is supposed to work.
The only thing I can imagine is that the guest EL1 timer is not really supposed to generate a real interrupt, but to silently generate a virq, but I don't see anything in section D11 (Generic Timer in AArch64 State) that validates that hypothesis.
OK, how about option B -- have we correctly implemented the new-for-VHE timer, are we mapping the various guest accesses to timer registers to the right underlying QEMU timers ?
thanks -- PMM