On Wednesday 09 February 2011 20:25:32 Will Deacon wrote:
- Why is architecture 0x4 not supported? This seems to be the variant of
the v7 debug architecture with memory-mapped registers. Apparently the IGEP only supports this version ... Do you know what the Beagle-/Pandaboard and other clones do? What would it take to support this architecture variant? Given the widespread use of those boards, it would be really nice if we could support hardware debugging on them ...
The memory-mapped interface is hugely unreliable in real hardware because you have to calculate the address of the memory-mapped debug registers by using a base and offset, which are hardcoded in some information registers. Unfortunately, I've never found a board where these registers have been programmed correctly so (a) I had nothing to test my code with (b) few people would be able to use it and (c) there's not really a safe way to go around poking random areas of memory.
So the only problem is that it's board specific? That's something we know how to deal with -- all I/O components have some random board specific address, and we put them in a platform device that is listed in the board file. This should be easy enough to do for another register area, though it means we have to do it separately for each board.
- Which hardware is supported? Can you recommend a board I should be
using to verify GDB support is working?
The simple rule is Cortex-A8 is unsupported and Cortex-A9 is supported. The A5 should work (untested) and the A15 will need a bit of hacking to get it supported.
Is that because A8 is memory mapped and A9 uses CP14, or is there another problem with A8?
Arnd