Hi Yvan,

There is no issue in the first case. You are correct that the dmb’s there are to ensure the sequential consistency as you’d want to see with __ATOMIC_SEQ_CST in the call to the builtin. However what you must remember is that STRs are guaranteed to be single-copy atomic by the architecture on v7-a. In general on v7-a there is single-copy atomicity with loads and stores to byte, half-words (2 byte aligned) and word  (4 byte aligned) addresses i.e. ldrb, ldrh and ldr.

On systems with LPAE enabled, ldrd and strd are also guaranteed to be atomic copies from 64 bit aligned addresses, thus in general for v7-a you should be using the ldrexd / strexd variant in this particular case. Thus the code for the first example should work correctly as is and *not* require an ldrex / strex implementation.

The second case always hurts my head – the short story is that you are right and it looks like a bug. The barrier needs to be after the load and not before because `Acquire’ semantics imply that no reads in the current thread dependent on the value currently loaded can be reordered before this load. What this means is that loads before this operation can percolate downwards towards the barrier .

The other clue to this is the definition around the `Release’ semantics, where no writes in the current thread can be reordered after this store. This implies that the write operation puts out barriers *before* the write which is what we do with __atomic_store_n (addr, 0, __ATOMIC_RELEASE); and that appears to be correct.

However what’s not clear to me is why there is this deliberate choice in the default implementation of expand_atomic_load to put out a memory fence before the load and that seems to have percolated back down into the backend for atomic_loaddi. We should take this up upstream as a bug.

Regards,

Ramana

P.S.  32 bit v8 would make life oh, so much easier in this area with proper load acquire and store release.

From: linaro-toolchain-bounces@lists.linaro.org [mailto:linaro-toolchain-bounces@lists.linaro.org] On Behalf Of Yvan Roux
Sent: 22 November 2012 17:43
To: linaro-toolchain@lists.linaro.org
Subject: Atomic builtins questions

Hi,

I think I have identified some issues with the atomic builtins, but I want your advises.

For instance :

A:  __atomic_store_n (addr, val, __ATOMIC_SEQ_CST);

gives the armv7 code:

DMB     sy

STR     r1, [r0]

DMB     sy

but if I have well understood, the DMBs instructions only provide the property that the

code is sequentially consistent, but not the atomicity for which we have to use the 

LDREX/STREX instructions. Thus I think that the code should be :

    DMB     sy

1: LDREX  r2, [r0]

    STREX  r1, r2, [r0]

    TEQ      r1, #0

    BNE      1b

B: __atomic_load_n (addr, __ATOMIC_ACQUIRE);

gives the armv7 code:

DMB     sy

LDR     r0, [r0]

but the load-acquire semantique specifies that all loads and stores appearing in program order

after the load-acquire will be observed after the load-acquire, thus the DMB should be after the

LDR, no ?

--

Yvan