On Wed, Dec 8, 2010 at 12:04 PM, Peter Maydell peter.maydell@linaro.org wrote:
Hi. As part of my work on qemu I've written a simplistic random instruction sequence generator and test harness. To quote the README:
risu is a tool intended to assist in testing the implementation of models of the ARM architecture such as qemu and valgrind. In particular it restricts itself to considering the parts of the architecture visible from Linux userspace, so it can be used to test programs which only implement userspace, like valgrind and qemu's linux-user mode.
I'd thought about this sort of thing before, but there were some interesting challenges...
Is it random random, or does it try to mould to the architectural envelope?
For example, randomly choosing opcode and shift operation bits in ALU instructions will exercise the interpreter much more interestingly than randomly choosing the offset bits in a branch instruction; and some potentially highly interesting and error-prone instructions like barriers, WFE/SEV, and all that kind of thing will get basically no testing from a random-number generator, since they tend to map to a single, fixed bit pattern.
I don't particularly expect this tool to be of much general interest outside people developing either qemu or valgrind or similar models, but I have in any case made it publicly available now:
http://git.linaro.org/gitweb?p=people/pmaydell/risu.git%3Ba=tree
Cheers ---Dave