Hi,
Linaro GCC 4.9 2015.01 source package has been respun and deployed on:
http://releases.linaro.org/15.01/components/toolchain/gcc-linaro/4.9
This package release contains two fixes for Linaro bugzilla's PR:
* #1291 - ICE (segmentation fault) on arm-linux-gnueabihf
* #1314 - ICE (in in expand_expr_addr_expr_1, at expr.c:7634) on
arm-linux-gnueabihf
You can find the original 2015.01 announcement below
Regards,
Yvan
---------------------------------------------------------------------------------------------------------------------
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2015.01
engineering release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2015.01 is the tenth Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.3-pre+svn219502 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler. The Linaro TCWG provides
stable[1] quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include
* Linaro bugzilla PR fixed : #902
* Updates to GCC 4.9.3-pre+svn219502
* Backport of [AArch64] Support SISD variants of SCVTF,UCVTF
* Backport of [AArch64] Fix ICE in aarch64_float_const_representable_p
* Backport of [AArch64] Switch to sched-pressure by default.
* Backport of [AArch64] Add scheduler for ThunderX
* Backport of [AArch64] Remove crypto extension from default for cortex-a53,
cortex-a57
* Backport of [AArch64] doloop pattern for -fmodulo-sched
* Backport of [AArch32] Add execution tests of ARM REV intrinsics.
* Backport of [AArch32] Post-indexed addressing for NEON memory access
* Backport of [AArch32] Improve 64 bit division performance (serie)
* Backport of [AArch32] Revert 215321 backport.
* Backport of [AArch32/AArch64] Add ACLE 2.0 predefined macros
* Backport of PR tree-optimization/54742 - extend jump thread for finite state
automata
* Backport of PR target/61997 - cc1plus ICE with aarch64 target using PCH and
builtin functions
* Backport of PR target/63724 - Fix up BSL expander for floating point types
* Backport of [LRA] Relax one gcc_assert in lra-eliminate for fixed register
* Backport of Add clobber_reg function
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the
full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
== Progress ==
* Linaro bugs (6/10)
#1291 #1293, #1314
* Home PC crashed and required hardware upgrade and software
re-installation (2/10)
* Improve register allocation for AArch64 (TCWG-620) - (1/10)
- preparations for benchmarking of proposed changes
* Misc (1/10)
- gcc-patchs and gcc-bugs list
== Plan ==
* TCWG-620 and TCWG-547
* ASAN/TSAN run on 42 bit VA Aarch64 with 64 bit allocator (TCWG-634) (5/10)
* Bug 869 (2/10)
* Bug 1266(1/10)
* Emails, meetings. (2/10)
* Linaro 1-1 with christophe. status call.
* AMD meetings/event, 1-1 with AMD manager, status meeting.
* GCC mailing list.
== Plan ==
* TSAN/ASAN support look why 64 allocator on juno is failing .
* Look at ASAN failures if 64 allocator is enabled on amd-01.
* AMD internal meeting on Tuesday and Wednesday
== Progress ==
* Automation Framework (CARD-1378 5/10)
- Setting up new servers
* Background (5/10)
- Code review, meetings, discussions, etc.
- Updating some LLVM dev scripts
- Adding tools checks to LNT
- EuroLLVM Paper selection
- LLDB/ARM meetings
- Bisecting lots of failures in all bots
== Plan ==
Go back developing LLVM for a change...
Juno cache effects - LDTS-1238 [6/10]
* Ran more experiments
* Cobbled together some gdb/python script to run perf stat within an
address range
* Becoming more confident in my hypotheses
catomics - TCWG-436 [1/10]
* Found and fixed some more sysroot benchmark bugs
* Kicked off a bunch of spec runs, waiting for the results to come back
Benchmark automation - TCWG-360 [1/10]
* A couple of post-lab-maintenance fixups
* Took a first look at result consistency with a broken run intended
for catomics
Misc - [2/10]
* Featuring the start of fixing juno-01
=Plan=
Finish fixing juno-01
Carry on looking at LDTS-1238, hopeful of confirming hypotheses
Analyse catomics results (assuming that they land)
Carry on with Jenkins, if time
== Issue ==
* none
== Progress ==
* Linaro Bugzilla: (5/10)
- #1149: 4.9-2015.01 miscompiles GCC trunk on aarch64-linux-gnu
* Backported upstream bug fix in 2015.01 re-spin branch and our 4.9 one.
- #1291: [4.9 Regression] ICE (segmentation fault) on arm-linux-gnueabihf
* Identified a set of upstream revision that fixe the issue
* Backported them in 2015.01 re-spin branch and our 4.9 one.
- #1314: [4.9 Regression] ICE (in in expand_expr_addr_expr_1, at expr.c:7634)
on arm-linux-gnueabihf
* Identified that it's a duplicate of an upstream bug on 4.9
branch (PR 61207)
which is itself a duplicate of an already fixed bug on trunk (PR 64896)
* Tested backport of the fix on on 4.9 branch.
* Release and Backports (4/10)
- Re-spin 2015.01 source release with fixes for Linaro bugs: #1149 and #1291
- Various supports of backporting activity
- Reviewed some backports
- Discussed our new release/maintenance policy
- Worked on Backflip improvements
* Misc (1/10)
- Various meetings
== Plan ==
* Backport PR 64896 fix into FSF 4.9 branch
* Backport/FSF Merge/Release duty
== Progress ==
Benchmarking 2015.02 [2/10]
. it turns out to be difficult to build previous releases with abe.sh
(bz#776, bz#1307)
. submitted patch to gerrit to improve abe.sh error handling
. benchmarks started on Jenkins
Backports [4/10]
. investigating incorrect merge discovered in review
. resolved... then found more conflicts with other backports
. need to redo backports
bug #1254 [1/10]
. reduced
. started investigating
misc [1/10]
. mailing lists
. meetings
== Plan ==
redo backports of 217440, 217885
start backports of 218021, 218534
bug#1254
vectorization investigation
look at benchmarking results from Jenkins
# Progress #
* aarch64 gdb , TCWG-652, [6/10]
** TCWG-662: Fixed and committed (by Pedro).
** TCWG-660: Rebuild toolchain with ABE.
** TCWG-663: Root cause of fails are known, that test case sets HW
breakpoint on arbitrary address while aarch64 HW breakpoint requires
4-byte align. ARM has the similar HW breakpoint feature, need to
to check on arm target too.
* fsf gdb patch review [2/10]
** Review and approve one patch from IBM which fixes TCWG-669 too.
** Discuss on re-org for syscall catchpoint for different target/arch.
* misc [2/10]
** Meeting.
** Move to the new house.
# Issues #
* Need an ARM board with HW breakpoint support in kernel. I tried
32-bit system on my juno board via schroot, but
PTRACE_SETHBPREGS doesn't work properly.
# Plan #
* TCWG-660: Teach ABE to import systemtap and build glibc with
--enable-systemtap.
* TCWG-663: See how the tests behave on ARM if ARM board is available.
* Other cards under TCWG-652.
--
Yao
== Progress ==
* Validation: (2/10)
- reached a state where Jenkins "green" actually means no regression found
- submitted patches for review
- confirmed that ABE master branch produces results similar to merge branch
- stopped checking the accuracy of report.sh since a few bugzilla
had been submitted, using ST script instead
* Backports (3/10)
- reviews are getting difficult, with lots of conflicts as the 4.9
branch has diverged from trunk quite a lot
* Sanitizers (1/10)
- trying to build LLVM+run the ASAN tests on AArch32
- tried to reconfigure my Hikey 96board with a 42 VA bits enabled
kernel, but it didn't boot: I still don't have access to such a
platform
* GCC FSF trunk/4.9 monitoring
- stopped tracking random "Interrupted system call"
- builds and validations now run faster, but with more frequent such errors
* Misc (4/10)
- meetings, conf-calls, emails, ...
- Release/maintenance branches policy, respin criteria, validation matrix
== Next ==
* Backports: reviews, and improve review-tool
* Sanitizers
Hi,
I have being trying to persuade gcc to generate the ldp instruction without success. I have tried many combinations, below is an example.
--- cut here ---
#define LDP(x,y,p) { \
struct vec { long x, y; } data; \
data = *(struct vec *)p; p += 2; \
x = data.x; y = data.y; \
}
long testp(long *p) {
long x, y;
LDP(x, y, p);
return x+y;
}
--- cut here ---
$ gcc --version
gcc (GCC) 4.9.1
Copyright (C) 2014 Free Software Foundation, Inc.
This is free software; see the source for copying conditions. There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
$ gcc -S -O3 ldp.c
$ cat ldp.s
.cpu generic+fp+simd
.file "ldp.c"
.text
.align 2
.global testp
.type testp, %function
testp:
ldr x1, [x0,8] ;; why not ldp?????
ldr x0, [x0]
add x0, x1, x0
ret
.size testp, .-testp
.ident "GCC: (GNU) 4.9.1"
What can I do do make it generate ldp?
Ed.
