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[weekly][linaro] report week ending 22 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - Implemented Neoverse N2 CPU model (easy as it's very similar to the Cortex-A710 we just implemented; but because it supports 48 bit physical addresses we can use it in the sbsa-ref board, so it's worth having both) - Wrote code to wire up the NS EL2 virtual timer IRQ on the virt board. This is part of FEAT_VHE, and we implemented the timer itself in the CPU ages ago, but forgot to ever wire up the interrupt line on the board models. Unfortunately doing this runs into a bug in EDK2 where it incorrectly asserts when it sees a dtb that reports the interrupt line. Leif Lindholm wrote patches to fix this in EDK2, but we'll need to update the QEMU testsuite and figure out how to communicate the need for an updated EDK2 to users. - Looked again at a long-standing missing feature in the virt board where it only has one UART. The main blocker for adding a second one has been odd EDK2 behaviour when the dtb tells it there are two UARTs. Investigated and wrote up exactly what it does to start a discussion about improving it. - Put together a target-arm pull request - Squashed a few -Wshadow warnings - Looking at a bug involving QEMU's PSCI emulation when QEMU is faking being EL3 firmware for a Linux guest * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - Implemented and sent a patch for FEAT_HPMN0 (a very easy feature that makes MDCR_EL2.HPMN==0 valid) -- PMM

1 year, 2 months

Re: [EXT] [Linaro-TCWG-CI] basepoints/gcc-14-4038-gb975c0dc3be: Failure

by Andrew Pinski

I could not reproduce the bootstrap failure at -O3 on x86_64. I used --with-build-config=bootstrap-O3 . Maybe this is an arm (32?) only issue. Thanks, Andrew ________________________________________ From: ci_notify(a)linaro.org <ci_notify(a)linaro.org> Sent: Saturday, September 16, 2023 5:33 AM To: Andrew Pinski Cc: gcc-regression(a)gcc.gnu.org Subject: [EXT] [Linaro-TCWG-CI] basepoints/gcc-14-4038-gb975c0dc3be: Failure External Email ---------------------------------------------------------------------- Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In CI config tcwg_bootstrap_build/master-arm-bootstrap_O3 after: | commit basepoints/gcc-14-4038-gb975c0dc3be | Author: Andrew Pinski <apinski(a)marvell.com> | Date: Thu Sep 14 14:47:04 2023 -0700 | | MATCH: Improve zero_one_valued_p for cases without range information | | I noticed we sometimes lose range information in forwprop due to a few | match and simplify patterns optimizing away casts. So the easier way | to these cases is to add a match for zero_one_valued_p wich mathes | a cast from another zero_one_valued_p. | This also adds the case of `x & zero_one_valued_p` as being zero_one_valued_p | ... 13 lines of the commit log omitted. Results changed to # reset_artifacts: -10 # true: 0 # build_abe bootstrap_O3: # FAILED # First few build errors in logs: # 00:30:42 xg++: internal compiler error: Segmentation fault signal terminated program cc1plus # 00:30:42 make[3]: *** [Makefile:1184: tree-ssa-loop-niter.o] Error 4 # 00:30:42 make[2]: *** [Makefile:5051: all-stage2-gcc] Error 2 # 00:30:42 make[1]: *** [Makefile:25871: stage2-bubble] Error 2 # 00:30:42 make: *** [Makefile:1090: all] Error 2 # 00:07:25 make[3]: [Makefile:1822: armv8l-unknown-linux-gnueabihf/bits/largefile-config.h] Error 1 (ignored) # 00:25:31 xg++: internal compiler error: Segmentation fault signal terminated program cc1plus # 00:25:31 make[3]: *** [Makefile:1184: tree-ssa-loop-niter.o] Error 4 # 00:30:14 make[2]: *** [Makefile:5051: all-stage2-gcc] Error 2 # 00:30:14 make[1]: *** [Makefile:25871: stage2-bubble] Error 2 # 00:30:14 make: *** [Makefile:1090: all] Error 2 From # reset_artifacts: -10 # true: 0 # build_abe bootstrap_O3: 1 -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg… Reference build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg… Reproduce last good and first bad builds: https://urldefense.proofpoint.com/v2/url?u=https-3A__git.linaro.org_toolcha… Full commit : https://urldefense.proofpoint.com/v2/url?u=https-3A__github.com_gcc-2Dmirro… Latest bug report status : https://urldefense.proofpoint.com/v2/url?u=https-3A__linaro.atlassian.net_b… List of configurations that regressed due to this commit : * tcwg_bootstrap_build ** master-arm-bootstrap_O3 *** Failure *** https://urldefense.proofpoint.com/v2/url?u=https-3A__git.linaro.org_toolcha… *** https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…

1 year, 2 months

[Linaro-TCWG-CI] glibc-2.38.9000-125-g973fe93a56: FAIL: 1 regressions

by ci_notify＠linaro.org

Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In CI config tcwg_glibc_check/master-arm after: | commit glibc-2.38.9000-125-g973fe93a56 | Author: Siddhesh Poyarekar <siddhesh(a)sourceware.org> | Date: Fri Sep 15 13:51:12 2023 -0400 | | getaddrinfo: Fix use after free in getcanonname (CVE-2023-4806) | | When an NSS plugin only implements the _gethostbyname2_r and | _getcanonname_r callbacks, getaddrinfo could use memory that was freed | during tmpbuf resizing, through h_name in a previous query response. | | The backing store for res->at->name when doing a query with | ... 15 lines of the commit log omitted. FAIL: 1 regressions regressions.sum: === glibc tests === Running glibc:nss ... FAIL: nss/tst-nss-gai-hv2-canonname === Results Summary === You can find the failure logs in *.log.1.xz files in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/artifact/a… . The full lists of regressions and progressions are in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/artifact/a… . The list of [ignored] baseline and flaky failures are in - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/artifact/a… . -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/artifact/a… Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/615/artifact/a… Reproduce last good and first bad builds: https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/glibc/sha… Full commit : https://sourceware.org/git/?p=glibc.git;a=commitdiff;h=973fe93a5675c42798b2… Latest bug report status : https://linaro.atlassian.net/browse/GNU-940 List of configurations that regressed due to this commit : * tcwg_glibc_check ** master-arm *** FAIL: 1 regressions *** https://git.linaro.org/toolchain/ci/interesting-commits.git/plain/glibc/sha… *** https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/616/

1 year, 2 months

[ACTIVITY] report week ending 15 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent patches that re-sync our defined set of usermode hwcap bits and ID register bitmasks with what the Linux kernel currently has - code review * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - FEAT_HBC: wrote and sent patch for this very simple feature - FEAT_MOPS: rolled v2 patchset based on review feedback * QEMU-486 [Update QEMU device models for FEAT_RME] - Looked at the SMMU spec to see (a) what realm-management related changes it needs and (b) where we are on the implementation of other features. Closed a few stale JIRA issues for features we've already implemented. - sent a patchset that advertises that we support SMMUv3.1-XNX (this is a no-op for our implementation) - investigated what the "expected" setup is for enforcing GPT checks on the GIC/ITS. Current front-runner is "the SMMU that's already in the system provides 'GPC checks only' for the accesses from these devices, as well as stage1/stage2 + GPT checks for PCI etc devices" (the term in the SMMU spec rev F.a is for a GPC-checks-only client device is "NoStreamID device") -- PMM

1 year, 2 months

Re: [Linaro-TCWG-CI] glibc patch #75959: FAIL: 1 regressions

by Siddhesh Poyarekar

On 2023-09-14 16:32, ci_notify(a)linaro.org wrote: > Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. > > In CI config tcwg_glibc_check/master-arm after: > > | glibc patch https://patchwork.sourceware.org/patch/75959 > | Author: Siddhesh Poyarekar <siddhesh(a)sourceware.org> > | Date: Thu Sep 14 06:13:02 2023 -0400 > | > | getaddrinfo: Fix use after free in getcanonname (CVE-2023-4806) > | > | When an NSS plugin only implements the _gethostbyname2_r and > | _getcanonname_r callbacks, getaddrinfo could use memory that was freed > | during tmpbuf resizing, through h_name in a previous query response. > | Fix this by copying h_name over and freeing it at the end. > | > | ... 3 lines of the commit log omitted. > | ... applied on top of baseline commit: > | 803f4073cc Add MOVE_MOUNT_BENEATH from Linux 6.5 to sys/mount.h > > FAIL: 1 regressions > > regressions.sum: > === glibc tests === > > Running glibc:nss ... > FAIL: nss/tst-nss-gai-hv2-canonname > > === Results Summary === > > You can find the failure logs in *.log.1.xz files in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/703/artifa… . > The full lists of regressions and progressions are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/703/artifa… . > The list of [ignored] baseline and flaky failures are in > - https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/703/artifa… . > > > > -----------------8<--------------------------8<--------------------------8<-------------------------- > The information below can be used to reproduce a debug environment: > > Current build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-precommit/703/artifa… > Reference build : https://ci.linaro.org/job/tcwg_glibc_check--master-arm-build/612/artifact/a… Hello, I'm looking at the logs and all it has is: original exit status 127 running post-clean rsync for the new test. It looks like other NSS tests also fail in the same way. Is this a known issue on arm? Thanks, Sid

1 year, 2 months

Fwd: [Linaro-TCWG-CI] gcc patch #75644: FAIL: 2 regressions

by Jonathan Wakely

I think this is because the patch changes libstdc++-v3/include/bits/version.def which requires version.h to be regenerated, by running 'make update-version' in the objdir/$target/libstdc++-v3/include directory. The patch I sent to gcc-patches (which is archived in patchwork) doesn't have the updates to the generated files, but what I committed to git does have them. ---------- Forwarded message --------- From: <ci_notify(a)linaro.org> Date: Mon, 11 Sept 2023 at 21:00 Subject: [Linaro-TCWG-CI] gcc patch #75644: FAIL: 2 regressions To: <jwakely(a)redhat.com> Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list, Libera's #linaro-tcwg channel, or ping your favourite Linaro toolchain developer on the usual project channel. In CI config tcwg_gcc_check/master-aarch64 after: | gcc patch https://patchwork.sourceware.org/patch/75644 | Author: Jonathan Wakely <jwakely(a)redhat.com> | Date: Mon Sep 11 14:57:08 2023 +0100 | | libstdc++: Formatting std::thread::id and std::stacktrace (P2693R1) | | Tested aarch64-linux. Pushed to trunk. | | -- >8 -- | | New std::formatter specializations for C++23. | ... 18 lines of the commit log omitted. | ... applied on top of baseline commit: | 390fa3a78c8 libstdc++: Fix -Wunused-parameter warnings FAIL: 2 regressions regressions.sum: === libstdc++ tests === Running libstdc++:libstdc++-dg/conformance.exp ... FAIL: 19_diagnostics/stacktrace/output.cc (test for excess errors) FAIL: 19_diagnostics/stacktrace/version.cc (test for excess errors) === Results Summary === You can find the failure logs in *.log.1.xz files in - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/2232/art… . The full lists of regressions and progressions are in - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/2232/art… . The list of [ignored] baseline and flaky failures are in - https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/2232/art… . -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-precommit/2232/art… Reference build : https://ci.linaro.org/job/tcwg_gcc_check--master-aarch64-build/926/artifact…

1 year, 2 months

[ACTIVITY] Report for week #36

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Continuing work on new approach to support changing SVE vector length in remote debugging. Fixed making native GDB work with the new approach using the DWARF location expression. Now porting the same approach to gdbserver, with an ad-hoc minimal location expression. # TCWG CI - Fixed GDB testsuite default timeout value, to make GDB check jobs for 32-bit ARM run in a less unreasonable time again. # Misc - Started preparation for future work on Guarded Control Stack for GDB. -- Thiago

1 year, 2 months

[ACTIVITY] report week ending 8 Sep

by Peter Maydell

Progress: * UM-2 [QEMU upstream maintainership] - sent patch fixing some regexes in our documentation - patch review and queueing up an arm pull request - Investigated the mps3-an536 Cortex-R52 FPGA image to see what work would be required to implement a QEMU model of it, wrote a draft of a jira epic issue for this * QEMU-530 [QEMU ARM v9.4 Baseline CPU for TCG] - FEAT_MOPS: * Implemented and tested the memcpy/memmove insns CPY* * Got the whole patchseries into good enough shape to send out for review -- PMM

1 year, 2 months

[ACTIVITY] Report for week #35

by Thiago Jung Bauermann

Hello, # [GNU-767] Support changing SVE vector length in remote debugging - Resumed working on new approach to support changing SVE vector length in remote debugging. I was able to use DWARF location expressions in the target description to express the SVE vector register sizes in terms of the VG register. Also adapted the regcache to support variable-length registers, and removed the VQ value from the target description and from aarch64_gdbarch_tdep, making GDB use one target description regardless of the vector length size. Still ironing out some bugs, and haven't tackled gdbserver yet. -- Thiago

1 year, 2 months

Re: [EXT] [Linaro-TCWG-CI] 2 patches in gcc: FAIL: 1 regressions

by Andrew Pinski

Just FYI. This test is just bogus and fixing it might be simple as using -fsanitize=undefined to check at runtime there is no undefined behavior being hit. In this case even if we do the comparison in `signed` and do the negate in `unsigned` types. we can still remove the negate in this case since we know the only value that will be still negative in that branch is LONG_MIN. So my patch just simplifies the inner comparison to that instead of `a < 0` and then be able to remove the neg. Someone else will have to fix the testcase since it is a testcase issue ... ________________________________________ From: ci_notify(a)linaro.org <ci_notify(a)linaro.org> Sent: Friday, September 1, 2023 3:07 PM To: Andrew Pinski Subject: [EXT] [Linaro-TCWG-CI] 2 patches in gcc: FAIL: 1 regressions External Email ---------------------------------------------------------------------- Dear contributor, our automatic CI has detected problems related to your patch(es). Please find some details below. If you have any questions, please follow up on linaro-toolchain(a)lists.linaro.org mailing list. In CI config tcwg_gcc_check/master-aarch64 after: | 2 patches in gcc | Patchwork URL: https://urldefense.proofpoint.com/v2/url?u=https-3A__patchwork.sourceware.o… | 504821491ff VR-VALUES: Rewrite test_for_singularity using range_op_handler | f6d1540c3e0 VR-VALUES: Rename op0/op1 to op1/op2 for test_for_singularity | ... applied on top of baseline commit: | b0d75f7d3bb libstdc++: Fix debug-mode tests for constexpr algorithms FAIL: 1 regressions regressions.sum: === gcc tests === Running gcc:gcc.target/aarch64/aarch64.exp ... FAIL: gcc.target/aarch64/vnegd_s64.c scan-assembler-times neg\\tx[0-9]+, x[0-9]+ 1 === Results Summary === -----------------8<--------------------------8<--------------------------8<-------------------------- The information below can be used to reproduce a debug environment: Current build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg… Reference build : https://urldefense.proofpoint.com/v2/url?u=https-3A__ci.linaro.org_job_tcwg…

1 year, 2 months

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