The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2017.07
snapshot of Linaro GCC 6 and 7 source packages.
o The GCC 7 series introduced an ABI change for ARM targets by fixing a bug
(present since GCC 5, see link below) that affects conformance to the procedure
call standard (AAPCS). The bug affects some C++ code where class objects are
passed by value to functions and could result in incorrect or inconsistent code
being generated. If the option -Wpsabi is enabled (on by default) the compiler
will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
o Linaro GCC 7 monthly snapshot[1] is based on FSF GCC 7.1+svn250046 and
includes performance improvements and bug fixes backported from mainline GCC.
The contents of this snapshot will be part of the 2017.08 stable[2] quarterly
release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/7.1-2017.07/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 7.1+svn250046
* Backport of [Bugfix] [AArch32] PR target/71778 ICE using
non-constant argument to Neon intrinsic that requires constant
arguments
* Backport of [Bugfix] [AArch64] PR target/71663 aarch64 Vector
initialization can be improved slightly
* Backport of [AArch32] Enable FP16 vector arithmetic operations
* Backport of [AArch32] Fix ARM bootstrap failure due to an odd warning
* Backport of [AArch32] Modify idiv costs for Cortex-A53
* Backport of [AArch64] Add combine pattern for storing lane zero of a vector
* Backport of [AArch64] Add HF vector modes to lane-to-lane INS pattern
* Backport of [AArch64] Add prefetch configuration to aarch64 backend
* Backport of [AArch64] Adjust costs so udiv is preferred over sdiv
when both are valid
* Backport of [AArch64] Allow CMP+SHIFT when comparing with zero
* Backport of [AArch64] Allow const0_rtx operand for atomic
compare-exchange patterns
* Backport of [AArch64] Emit tighter strong atomic compare-exchange
loop when comparing against zero
* Backport of [AArch64] Enable -fprefetch-loop-arrays at given
optimization level
* Backport of [AArch64] Fix -fstack-check with really big frames on aarch64
* Backport of [AArch64] Fix subreg bug in scalar copysign
* Backport of [AArch64] Peephole for SUBS
* Backport of [AArch64] Simplify call, call_value, sibcall,
sibcall_value patterns
* Backport of [AArch64] Update prefetch tuning parameters for qdf24xx.
* Backport of [AArch64] Use SUBS for parallel subtraction and
comparison with immediate
* Backport of [Misc] Add debug counter for loop array prefetching
* Backport of [Misc] Improve debug output of loop data prefetching
* Backport of [Cleanup] [AArch32] Complete legend for ARM register
allocation in arm.h
* Backport of [Cleanup] [AArch32] Fix comment for
cmse_nonsecure_call_clear_caller_saved
* Backport of [Cleanup] [AArch32] Fix typo in comment in arm_expand_prologue
* Backport of [Testsuite] [AArch32] Add MOVT testing for ARMv8-M Baseline
* Backport of [Testsuite] Add dg-require-stack-check
* Backport of [Testsuite] Fix stack-check-1.c
o Linaro GCC 6 monthly snapshot[1] is based on FSF GCC 6.4+svn250045 and
includes performance improvements and bug fixes backported from mainline GCC.
This snapshot contents will be part of the 2017.08 stable[2] quarterly release.
This snapshot tarball is available on:
http://snapshots.linaro.org/components/toolchain/gcc-linaro/6.4-2017.07/
Interesting changes in this GCC source package snapshot include:
* Updates to GCC 6.4+svn250045
* Linaro BZ #3040 -- CC1 and cc1plus cannot convert UTF-8: Regenerate
intl configure
* Backport of [AArch64] Fix -fstack-check with really big frames on aarch64
* Backport of [Testsuite] Add dg-require-stack-check
* Backport of [Testsuite] Fix stack-check-1.c
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at "Linaro support":
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
Achievements:
Some progress on Range Thunks. [TCWG-614]
- I have all the enabling patches that allow assignAddresses() to be
run multiple times committed.
- Need review for the actual range thunks implementation itself.
Compiler-rt [TCWG-1156]
- Clang (as opposed to llvm) is assuming that all builtins for ARM are
mandated to have a soft-float interface. I have a tentative patch but
need to test it a bit more first.
- Found out a bit more about the structure of how compiler-rt, and why
it behaves differently when I use the default target and
auto-detection of toolkit as opposed to supplying the target via
options.
-- There is quite a bit of hidden magic and hacks going on in the
default case, some of it I don't think is quite right. For example
Compiler-rt seems to conflate architecture with abi.
Set myself the task of getting compiler-rt tests running on v6-m with
testing on qemu.
- v6-m is the only auto-detected default target that I haven't been
able to reproduce results on.
- A review claimed that tests had been run on qemu, and I'm now trying
to work out how to reproduce this with clang and an arm-none-eabi
sysroot.
-- Not having a lot of luck so far, latest qemu only supports
emulation of 2 cortex-m3 dev-boards and I have yet to make a
standalone program that works [*]
-- I'm not looking forward to plumbing in the options to make the
arm-none-eabi testing work.
[*] I thought I would try semi-hosting first, but it turns out the
default semihosting startup code supplied with arm-none-eabi replaces
my heap and stack locations with a semi-hosting call to get top of
memory which qemu gives an inappropriate result for a dev-board
emulation with non contiguous memory. Would like to see if I can get
this working via a quick experiment to rewrite the start-up code,
although for the full tests I may fall back to retargeting the IO via
an emulated serial port.
Plans:
- First priority is range thunks for lld
- Second priority is getting a v6m test of compiler-rt to check for
any latent problems
- Submit clang patch when I know it works for all the supported platforms
- Look into v7-m support, particularly v7-m + single precision floating point.
# Progress #
* TCWG-1159, New design of GDB/GDBserver target description. [7/10]
It takes me a lot of time making the patch series v3 work, to address
review comments, to fix regressions, and to make sure each commit
doesn't break build. Almost done.
Looks 30 patches in one series is my limit, and wonder how does other
people manage large patch series.
* Help people runing GDB tests, and get some fails. It turns out we
encounter PR 21555. [1/10]
* Misc, [2/10]
# Plan #
* TCWG-1159
* PR 21555
* TCWG-561,
--
Yao Qi
== This Week ==
* PR78736 (4/10)
- Improved patch to not warn for enums with equal value ranges
- Caused fallouts in libgomp and libgfortran
- Large kernel fallout!
* type promotion (5/10)
- Looking at interference between path-splitting and type-promotion
optimizations
- miscompilation of memcpy-bi.c on
* Misc (1/10)
- Meetings
== Next Week ==
- Continue ongoing tasks
== Progress ==
* Infrastructure/validation:
- abe patch for bug #3040 committed, now we need to fix
regression-detection because it builds a toolchain that does not
support this fix (lacks a gcc patch)
- upgrade of dejagnu used for binutils validation fixed the random
errors we were seeing
* Benchmarking:
- production scripts were not up-to-date, but the new ones have a
conflict/dependency on ntp
* GCC upstream validation:
- working on further reducing noise ("random" pass/failures)
- reported/fixed a few regressions
- committed testsuite patch with de-require-stack-check
* misc (conf-calls, meetings, emails, ....)
== Progress ==
* TCWG-1155 - Move ASAN 39bit bot to GlobalISel [1/10]
- The bot is finally upstream and working well
* TCWG-1172 - [ARM GlobalISel] Support G_FCMP for s32 [7/10]
- Committed support for 32-bit floating point compares, both
hardware and software
* TCWG-1141 - Add "push" capability [1/10]
- Finally committed llvm-push
* Misc [1/10]
- Mailing lists, meetings, buildbots
== Plan ==
* TCWG-1187 - [ARM GlobalISel] Support G_FCMP for s64
== Activity ==
- Rebased and posted for review all my range-thunks work for LLD as
there had been some interest from some individuals on IRC in trying
out the patch.
-- Seems to work for them
-- Hoped that this might provoke upstream into looking and reviewing
the patches but no such luck.
- Landed the patch that sets _GLOBAL_OFFSET_TABLE_ so that FreeBSD can
link on ARM
- Some other small lld patches
- Investigations into whether an X86 patch might affect CFI generation
for AArch64.
Spent some time banging my head against the compiler-rt build system
to try and see if I can get a cross-compiled build and test run on
Qemu when my compiler-rt target != the default target (i.e. I want to
build clang with ARM and AArch64 targets and cross-build and test all
the ARM compiler-rt targets from that)
- Thwarted by what seems to be inconsistent decisions about
auto-detection of options, what is an architecture, target, sub-target
and abi.
- By passing in all auto-generated options by steam I'm still hitting
some problems with some tests that have an external assembly file.
Found numerous other small inconsistencies that I'll need to write up.
== Plans ==
- Ping the Range Thunks reviews again.
- Compiler-rt
Aim to get to the point where I can write a coherent mail to llvm-dev
explaining what I think is wrong and what I think needs changing.
== Progress ==
o Linaro GCC/Validation (7/10)
* Fixed AArch64 GCC options documentation
ARM part clean-up on-going
* libgomp/mingw patch: Upstream review pending
* pc-relative-literal-loads patch for GCC 6 branch: Upstream review pending
reviewed fxi for trunk.
* Following upstream discussions on stack clash CVE:
- One AArch64 specific commit done (backport in our branch on-going)
- Fix still under discussion upstream, nothing committed yet
* catching-up with re-association work
* libunwind support
o Misc (3/10)
* Various meetings and discussions.
== Plan ==
o backports for 2017.07, CVE, ...
== This Week ==
* Type promotion (6/10)
- Created patch to fix ICE with pr81083.c on ppc64
- Investigated mis-compilation of memcpy-bi.c on ppc64
* Malloc propagation (1/10)
- Working on patch based on feedback received.
* Public Holiday (2/10)
* Misc (1/10)
- Meetings
== Next Week ==
- Type promotion: Look at miscompilation bug, and investigate
performance regression for path
splitting optimization
- Malloc propagation
