Progress:
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Updates for user-only.
Merge bug fixes from eugeni.stepanov(a)gmail.com.
[VIRT-349 # QEMU SVE2 Supprt ]
Convert neon pmul helpers to a form that will be usable for sve2.
[VIRT-327 # Richard's upstream QEMU work ]
Pull for tcg-next.
Review plugins v5.
Update for capstone submodule.
Started reviewing multi-phase reset v5.
[Kernel]
Hacked up a patch for ARMv8.5-RNG.
r~
# Progress #
o Ramp up
* Credentials, machine access and LDAP updates done.
o Qualcomm Landing Team sunsetting
* Returned Qualcomm's Laptop.
o Upstream GDB
* Ramping up on reviews.
* Gathering data on the current state of GDB on ARM.
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- Came up with a little hack/proof-of-concept to get this fixed.
Though ugly, it seems fixing this in the front-end may make more sense,
as the information i need (source line) is easily accessible in there.
- Discussion ongoing with gcc@. GDB clearly needs the compiler to
provide more information.
* Created JIRA cards for all known pending ARM tasks for GDB, based
on Alan's and Joey's input. TODO-ed all of them for the time being.
# Plan #
o GDB:
* GNU-170 - GDB BZ #21221 - gdb hangs while stepping an empty loop
- Continue pursuing a fix.
* Prioritize GDB JIRA cards and start work on them.
[Morello]
- Got static linking support to the point that I can successfully link
with LLD the coremark, dhrystone and EEMBC from the arran-toolchain.
Not got any outstanding failures to investigate.
- Altered LLD so a linker script is no longer necessary for newlib.
- Started the process of rebasing and adding tests for all the
fixes/hacks I needed to make to the linker work.
- Aligned the base and limit of capabilities according to the incoming
CHERI concentrate scheme. Interesting question of what should a linker
do when alignment requirements on the base and limit cross section
boundaries, and what are the responsibilities for an object producer
when creating a section when the length of the capability is known at
compile time.
Planned absences:
Holiday Thursday, Friday (24th, 25th October)
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ finishing off the ptimer API transition work
+ review of rth's "speed up calculation of tbflags" patchset
+ put together and sent an arm pullreq
* VIRT-350 [Update Arm KVM support in QEMU]
+ the patchset for hotpluggable RAM support is now upstream
thanks
-- PMM
== Progress ==
* GCC:
- Work on -mpure-code on v6m. Patches sent for upstream review.
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
== Next ==
* FDPIC: resume work on GDB
* GCC: pure-code/v6m
* Binutils: support non-contiguous memory regions in linker
== Progress ==
* clang-tidy workshop (and associated prep)
- I think this went really well, we got good feedback from some of
the participants
* Trying to setup a build environment on tcwg-sq-02.tcwglab
- Mostly so I can deploy the SVE fuzzer there, but maybe for other things too
- All the compilers that I've tried so far are ICE-ing at some point
or another while building llvm
- Still looking into it but I'm starting to suspect there's
something fishy about this board
* Still no access to Morello docs
* Read a bit more about LLDB
* Finished annual review
== Plan ==
* Maybe THIS time I'll get access to the Morello docs next week
* If not, more SVE fuzzer
* One day off
o LLVM:
* Buildbots babysitting:
- Various breakage on the bots and in the kernel build
* Machine Outliner:
- preparing upstream submission
o Misc
* Various meetings and discussions.
== Progress ==
* GCC:
- Work on -mpure-code on v6m
* GCC upstream validation:
- reported several issues
* misc:
- infra fixes / troubleshooting / reviews
- watched a couple of GNU Cauldron presentations
== Next ==
* FDPIC: resume work on GDB
* GCC: pure-code/v6m
* Binutils: support non-contiguous memory regions in linker
