Progress (short week, 3 days):
* UM-2 [QEMU upstream maintainership]
+ Code review:
- SVE2 series v7 (now finally done)
- RTH's tlb_flush range refactoring
- A few other minor patchsets
+ Arm pullrequest: SVE2 emulation support is now upstream
+ Misc bugs:
- sent some patches fixing a few coverity nits in our test suite code
* QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)]
+ Implemented:
- VQDMULL, VRHADD, VADC, VSBC, VCADD, VHCADD
- LCTP, LETP, WLSTP, DLSTP (the tail-predicating loop insns)
- Progress meter: 73/210 (34%)
-- PMM
== This Week ==
* PR66791 (Replace builtins with C operations in intrinsics)
- vtst: Committed patch to trunk.
- vshl_n: Patch results in worse code-gen, abandoned.
- vmul_n: Created patch, looking into testsuite fallout
* PR97906 (Missed lowering abs(x) >= abs(y) to vcage x, y)
- Investigated PR and have a WIP fix.
== Next Week ==
- Continue with PR66791, PR97906
Progress:
* UM-2 [QEMU upstream maintainership]
+ Code review:
- bfloat16 support patchset
- v3 of ITS emulation patchset
+ Misc bugs:
- sent a patch fixing a bug where we sometimes selected the wrong stack
pointer when doing a v8M exception return in a case involving
tail-chaining (needed by an upcoming Arm TF-M change)
* QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)]
+ Sent a small patchset which implements a few preliminary MVE things
(VPR register, FPSCR.QC bit, fixing checks for existing insns which
now need to be "FP or MVE" rather than just "FP")
+ Implemented:
- VADD VSUB VMULL VHADD VHSUB VQADD VQSUB VQDMULH VQRDMULH scalar
- VBRSR, VPST, VQDMULH, VQRDMULH, VQADD, VQSUB
- VQSHL VQRSHL VSHL VRSHL vector forms
- VQDMLADH, VQRDMLADH, VQDMLSDH, VQRDMLSDH
Progress meter: 63/210 (30%)
-- PMM
VirtIO Initiative ([STR-9])
===========================
- worked with Viresh on getting more reliable Xen up and running
- formally took over Caludio's arm branch as I need it for mine
- preparing [my version] for posting
[my version]
<https://github.com/stsquad/qemu/tree/arm/refactor-tcg-accel-split-v16>
QEMU Upstream Work ([UM-2])
===========================
- finally got [PULL v2 00/29] testing and plugin updates Message-Id:
<20210518090720.21915-1-alex.bennee(a)linaro.org> merged
- posted [PATCH v1 0/8] various misc fixes (gitlab, gdbstub, plugins)
Message-Id: <20210520174303.12310-1-alex.bennee(a)linaro.org>
[UM-2] <https://projects.linaro.org/browse/UM-2>
[testing/next branch]
<https://github.com/stsquad/qemu/tree/testing/next>
Other
=====
- [Blog post on QEMU went live]
[Blog post on QEMU went live]
<https://www.linaro.org/blog/many-uses-of-qemu/>
Current Review Queue
====================
TODO [PATCH v2 00/12] hw: Various Kconfig fixes
Message-Id: <20210515173716.358295-1-philmd(a)redhat.com>
======================================================================================================
TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels'
Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com>
===================================================================================================================================================
TODO [RFC PATCH v2 0/6] hw/arm/virt: Introduce cpu topology support
Message-Id: <20210413080745.33004-1-wangyanan55(a)huawei.com>
==============================================================================================================================
TODO [PATCH v2 00/12] virtio-gpu: Add support for Blob resources feature
Message-Id: <20210420065347.2685768-1-vivek.kasireddy(a)intel.com>
========================================================================================================================================
--
Alex Bennée
== Progress ==
* GCC upstream validation:
- reported a couple of regressions
* GCC
- MVE/vectorization: committed patches for vcmp, waiting for
feedback on the remaining patches for vld2/vst2, vld4/st4
- started work on vaddv support
- committed a few testsuite improvement patches
- committed patch for PR 42579
* Misc
- looking at gdb issue with register names in target description
== Next ==
* MVE auto-vectorization/intrinsics improvements
* GCC/cortex-M testing improvements & fixes
* GDB/cortex-M
Short week (2.5 days off)
== Progress ==
* GCC upstream validation:
- discussing update of the list of configs
* GCC
- MVE/vectorization: committing cleanup patches for vcmp, waiting for
feedback on the remaining patches for vcmp, vld2/vst2, vld4/st4
* Misc
- scripts patch reviews
- looking at gdb issue with register names in target description
== Next ==
* MVE auto-vectorization/intrinsics improvements
* GCC/cortex-M testing improvements & fixes
* GDB/cortex-M
Progress:
* UM-2 [QEMU upstream maintainership]
+ Code review:
- Managed to review all of RTH's 82-patch SVE2 patchset...
+ Misc bugs:
- fixed some errors in modelling of SRAM in AN547 board
- fixed a bug in GICv3 EOI (EL3 should be able to handle
Group 1 NS IRQs)
* QEMU-406 [QEMU support for MVE (M-profile Vector Extension; Helium)]
+ Implemented multiply-add-long-dual-accumulate insns
(VMLALDAV, VMLSLDAV, VRMLALDAVH, VRMLSLDAVH)
Progress meter: 40/210 (19%)
-- PMM
VirtIO Initiative ([STR-9])
===========================
- did some investigation on getting [Gunyah hypervisor] up and running
- debugging xl domU launch under QEMU
- got reverse debugging working on virtio ;-)
[STR-9] <https://projects.linaro.org/browse/STR-9>
[Gunyah hypervisor] <https://github.com/quic/gunyah-hypervisor>
QEMU Upstream Work ([UM-2])
===========================
- reviewed a large chunk of rth's FloatParts opus Message-Id:
<20210508014802.892561-1-richard.henderson(a)linaro.org>
- posted [PATCH v3 00/31] testing/next pre-PR (hexagon, tricore, misc)
Message-Id: <20210512102051.12134-1-alex.bennee(a)linaro.org>
[UM-2] <https://projects.linaro.org/browse/UM-2>
[testing/next branch]
<https://github.com/stsquad/qemu/tree/testing/next>
Other
=====
[Linaro JIRA Issues] Updates for LBO-99: QEMU's usage in Linaro
Message-Id: <01000178a38e5f60-4b7149b0-b71b-4952-869f-cabdfb9078a6-000000(a)email.amazonses.com>
Completed Reviews [1/1]
=======================
[PATCH 00/72] Convert floatx80 and float128 to FloatParts
Message-Id: <20210508014802.892561-1-richard.henderson(a)linaro.org>
Absences
========
- Bank Holiday on Monday
Current Review Queue
====================
TODO [PATCH v3 0/8] GICv3 LPI and ITS feature implementation
Message-Id: <20210429234201.125565-1-shashi.mallela(a)linaro.org>
===========================================================================================================================
TODO [PATCH v8 0/4] aarch64: add support for FEAT_TLBIRANGE and FEAT_TLBIOS
Message-Id: <20210505030443.25310-1-rebecca(a)nuviainc.com>
====================================================================================================================================
TODO [PATCH v6 00/82] target/arm: Implement SVE2
Message-Id: <20210430202610.1136687-1-richard.henderson(a)linaro.org>
===================================================================================================================
TODO [PATCH v4 00/12] qtests: Check accelerator available at runtime via QMP 'query-accels'
Message-Id: <20210415163304.4120052-1-philmd(a)redhat.com>
===================================================================================================================================================
--
Alex Bennée
Hi Richard,
Your patch a076632e274abe344ca7648b7c7f299273d4cbe0 appears to have broken bootstrap-O3 for 32-bit armhf. Do you have an AArch32-capable machine to reproduce/investigate this on? Let me know if not, and I'll make a proper bug report with a testcase.
ICE:
00:33:32 In function ‘syscall.forkExec’:
00:33:32 go1: error: address taken, but ADDRESSABLE bit not set
00:33:32 PHI argument
00:33:32 &go..C479;
00:33:32 for PHI node
00:33:32 err$__object_78 = PHI <err$__object_76(58), &go..C479(59)>
00:33:32 during GIMPLE pass: fre
00:33:32 go1: internal compiler error: verify_ssa failed
00:33:32 0x9c18d7 verify_ssa(bool, bool)
00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/tree-ssa.c:1214
00:33:32 0x6f8d5b execute_function_todo
00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2049
00:33:32 0x6f9abf do_per_function
00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:1687
00:33:32 0x6f9abf execute_todo
00:33:32 /home/tcwg-buildslave/workspace/tcwg_gnu_0/abe/snapshots/gcc.git~master/gcc/passes.c:2096
00:33:32 Please submit a full bug report,
00:33:32 with preprocessed source if appropriate.
00:33:32 Please include the complete backtrace with any bug report.
00:33:32 See <https://gcc.gnu.org/bugs/> for instructions.
00:33:32 Makefile:3001: recipe for target 'syscall.lo' failed
Full build log: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar…
Regards,
--
Maxim Kuvyrkov
https://www.linaro.org
> On May 11, 2021, at 8:15 AM, tcwg-jira (Jira) <projects(a)linaro.org> wrote:
>
> There is 1 comment.
>
>
> GNU Toolchain / <Mail Attachment.png> GNU-692 IN PROGRESS
> Regressions from tcwg_binutils/tcwg_cross/tcwg_gnu CI
>
> View issue · Add comment
>
> 1 comment
>
> tcwg-jira on 11/May/21 5:04 AM
>
> Successfully identified regression in gcc in CI configuration tcwg_gnu/gnu-master-arm-bootstrap_O3. So far, this commit has regressed CI configurations:
> • tcwg_gnu/gnu-master-arm-bootstrap_O3
> Culprit:
> <cut>
> commit a076632e274abe344ca7648b7c7f299273d4cbe0
> Author: Richard Biener <rguenther(a)suse.de>
> Date: Fri May 7 09:51:18 2021 +0200
> middle-end/100464 - avoid spurious TREE_ADDRESSABLE in folding debug stmts
> canonicalize_constructor_val was setting TREE_ADDRESSABLE on bases
> of ADDR_EXPRs but that's futile when we're dealing with CTOR values
> in debug stmts. This rips out the code which was added for Java
> and should have been an assertion when we didn't have debug stmts.
> To not regress g++.dg/tree-ssa/array-temp1.C we have to adjust the
> testcase to not look for a no longer applied invalid optimization.
> 2021-05-10 Richard Biener <rguenther(a)suse.de>
> PR middle-end/100464
> PR c++/100468
> gcc/
> • gimple-fold.c (canonicalize_constructor_val): Do not set
> TREE_ADDRESSABLE.
> gcc/cp/
> • call.c (set_up_extended_ref_temp): Mark the temporary
> addressable if the TARGET_EXPR was.
> gcc/testsuite/
> • gcc.dg/pr100464.c: New testcase.
> • g++.dg/tree-ssa/array-temp1.C: Adjust.
> </cut>
> Details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar…
> Even more details: https://ci.linaro.org/job/tcwg_gcc-bisect-gnu-master-arm-bootstrap_O3/16/ar…
>
>
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