[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Posted a couple of revisions. Good feedback between this
and MemTag, both of which need to adjust the set of TLBs.
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ]
Posted v7.
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ]
Rebased upon current VHE+BTI work. Updated from beta manuals
to the ARM ARM issue E.a manual.
[VIRT-327 # Richard's upstream QEMU work ]
Reviewed v1 x86 gen_sse rewrite.
Reviewed Alex's v4 plugin patchset.
r~
o LLVM:
* Bots babysitting
* Machine Outliner:
- Rebased branch on upstream
- Working on stack fixup limits test cases
o Misc
* Various meetings and discussions.
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ QEMU 4.1.0 rc3 sent out. As usual, we've found some last minute
bugs and we'll need an rc4 next week...
+ patch review:
- series from Philippe making some cleanups to use object_initialize_child()
and friends
- Alex's patch "generate a custom MIDR for -cpu max"
- made a start on reviewing RTH's 32-bit arm decodetree conversion
+ bug fixing:
- LP:1838277 : we were taking exceptions caused by BRK instructions at
EL2 to EL1, rather than to EL2; sent a patch fixing this
- LP:1838475 : FPU register stacking in M-profile CPUs without the
Security Extensions was incorrectly failing an NSACR check and
taking a bogus exception: sent a patch to fix
+ wrote a patchset that converts the sparc target away from the
deprecated and broken do_unassigned_access hook to use the new-in-2017
do_transaction_failure hook instead; one step closer to being able
to remove the old hook entirely...
+ did the same for the mips target
thanks
-- PMM
== This Week ==
* PR86753
- Working on approach suggested by Richard.
* PR90724
- Pinged upstream.
* Validation
- Merged patch to jenkins-scripts to add testsuite comparison to tcwg_gnu.
- Submitted patch for separating build and test steps in tcwg_gnu.
== Next Week ==
- Continue ongoing tasks.
== Progress ==
* LLVM 9.0.0 rc1 binaries uploaded
- Ran into one cross-platform issue (x86, AArch64, ARM etc)
- Opened a bug for libfuzzer tests on AArch64
* Use ninja in release job [LLVM-536]
- Done
* Investigate running benchmarks in containers [TCWG-1513]
- Seems to work, except for mcf which errors out; will investigate next week
* IR SVE reviews [LLVM-545]
- Another round of feedback to D53137
== Plan ==
* Review D47770
* Upcoming vacation: 6 - 13 August
* Friday off
== Progress ==
* GCC:
- FDPIC: started taking feedback into account. Changes under test.
- noinit attribute: posted a new version
* GNU-583 (Fix Linux kernel built for Thumb-2 with GCC using LTO)
- no progress this week
* GCC upstream validation:
- no new issue this week.
* Binutils:
- Non-contiguous memory regions support in the BFD linker: not started
yet. Received a few "warnings" as feedback.
* misc:
- infra fixes / troubleshooting
== Next ==
GCC:
- handle feedback on FDPIC and noinit patches
- binutils/linker support for non-contiguous memory regions
- GNU-583
- GCC upstream validation: Add a config for cortex-m33 (v8-m)
== Holidays ==
Aug 2-11 (next week)
[PR42719] BasicAA UnitTest failure on AArch64 when compiled with GCC
- Patch submitted upstream
[PR42853] LLD support for TPREL_G0 relocations
- In theory a simple change, but llvm-mc seems to be deliberately
doing something strange with MOVZ encodings fixMOVZ and I haven't
worked out why it is needed.
Investigations with respect to inline assembler constraints.
- Some patch review comments for my ABE (Linaro GCC build system)
patch for GCC RM multilibs
- LLD review for smaller AArch64 images.
- Wrote a summary of what TCWG do for the upstream community, may turn
into a Linaro blogpost
- Raised GCC PR91299 to cover incorrect weak definition inlining in
GCC LTO in presence of non-weak definition.
On holiday Friday 2nd August, back in the office on Monday.
