All,
During Connect the suggestion was made that each working group should have
its own IRC Channel for discussions and topics relating to the group in
particular (as opposed to #linaro which is 'generic' Linaro conversations).
Therefore I have just set up #linaro-tcwg on Freenode for the Toolchain
Working Group.
This channel is public and open to anyone who wants to talk with the TCWG
group about anything toolchain related.
Thanks,
Matt
--
Matthew Gretton-Dann
Toolchain Working Group, Linaro
== Progress ==
* PR88836
- I have a patch (for backend and CSE) which now passes bootstrap and
regression except for one testcase failure (which looks like a pattern
issue). Looking into it.
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
- Not convinced that it is a gcc issue. Looking into the dwarf specification.
* PR88838
- Looking at it.
- Also familiarising with auto-vectorisation of SVE
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
[LLVM-158] Monitor and maintain buildbots
- Some work to track down a faulty msan test on AArch64 that was
intermittently failing.
- Spent some time trying to reproduce an intermittent failure in libfuzzer.
[LLVM-523] Synthesise EXIDX_CANTUNWIND entries for sections without tables.
- Not getting much response from upstream beyond a vague suggestion to
rewrite the whole of .ARM.exidx handling as a single custom section. I
may have to go down this path to get the feature accepted, even if it
is to show that it is a bad idea.
[LLVM-496] LLD in linux kernel
- Submitted patch to ignore -p (--no-pipeline-knowledge) which is used
by the AArch32 linux kernel.
- Submitted patch to integrate LLD in TCWG kernel regression test.
- Learned, the hard way, about how the linux kernel build system works
and how to pass extra flags.
Reviews:
Spent an awful long time looking at how clang passes options to GNU as
to try and match the existing clang defaults. I'm not sure I've seen
anything much more confusing than tracing through target features from
clang to llvm and back again.
re-essayer de flash le kernel sur la board (mais est-ce possible vu
qu'il semble plus gros que la flash?)
$ openocd -f /usr/share/openocd/scripts/board/stm32f429discovery.cfg
-f flash-kernel.cfg
[...]
Info : device id = 0x20016419
Info : flash size = 2048kbytes
Info : Dual Bank 2048 kiB STM32F42x/43x/469/479 found
Warn : no flash bank found for address 0
wrote 0 bytes from file
/home/lyon/src/kernel/linux/arch/arm/boot/xipImage in 0.007352s (0.000
KiB/s)
** Programming Finished **
demander de l'aide aux gens de ST?
re-essayer avec un openocd plus recent
== Progress ==
* FDPIC
- (GNU-411) GDB: debugging problems with FDPIC support. Trying to
setup a stm32 board to avoid problems with unsupported configurations
mix between kernel and qemu.
* GCC upstream validation:
- reported a few regressions
* GCC:
- (GNU-99) ubsan / bare-metal. No progress.
* misc (conf-calls, meetings, emails, ....)
- reviewing infra script patches
- debugging new benchmarking round-robin jobs
== Next ==
Holidays, back on March 4th
== Next-next ==
FDPIC:
- GCC: handle feedback on v4 patches
- GDB: update patches
- uclibc-ng: look at how to test fdpic mode with openadk
- complete board setup
Infra:
- benchmarking jobs
Progress:
* VIRT-65 [QEMU upstream maintainership]
+ patch review: RTH's JSConv/FHM patchset
+ sent another arm pull request
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
+ Implemented and wired up the SSE-200 Message Handling Units
+ Implemented the mechanism by which a guest can power up CPU 1
+ Sent out patches for these; this can run the Zephyr MHU/dualcore testcase
+ Started looking at implementing floating point support for M profile
thanks
-- PMM
== Progress ==
* [Thumb GlobalISel] Support control flow [LLVM-530]
- Committed upstream
* [Thumb GlobalISel] Support accessing the stack [LLVM-527]
- Committed upstream
* [Thumb GlobalISel] Support floating point [LLVM-531]
- Committed upstream
* LLVM 8.0.0 Release for ARM & AArch64 [LLVM-526]
- Investigated the release blocker from rc1, turned out to be an
issue with the filesystem used in the container on the APMs
- Changed the release job to run on the D05 instead, where we use a
different container [LLVM-539]
- Testing still in progress
== Plan ==
* [Thumb GlobalISel] Support global variables [LLVM-540]
* Out of office between 4 - 8 March
== Progress ==
* PR88834:
* Have a patch for ivopt and backend that generates the required
addressing mode and code. Still need cleanup and some improvements.
* PR88836
Made the required changes to the backend.
CSE is still not happening. Looked at CSE in detail and made few
changes but still need more work. The issues are:
- Parallel rtx with one setting a register and other using it will
be immediately invalidated as the invalidation happens after
processing both.
- If CSE is such that one instruction is with one constant operand
and other with constant in a register, it will not be detected
- VEC_DUPLICATE is not handled.
- Not sure any other pass like GCSE is a better option
== Plan ==
* Complete above PRs
* Look at GDB BZ #21221 - gdb hangs while stepping an empty loop
