== Progress ==
* [ARM GlobalISel] Select complicated G_CONSTANT [LLVM-491]
- Committed upstream
* [ARM & Thumb GlobalISel] Support calls to vararg functions [LLVM-490]
- This gets rid of all the fallbacks in the test-suite related to
calls to printf (which is a lot)
- Committed upstream
* Use new version of GCC on buildbots [LLVM-515]
- Fiddled with this a bit, but couldn't test much due to dockerd
being broken for a couple of days
- Manual installation of g++-7 from PPA works, but when trying the
same steps in the dockerfile it keeps restarting; need to investigate
why
== Plan ==
* More of the same
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2019.01 snapshot of the Linaro GCC 7 source package.
The GCC 7 series introduced an ABI change for ARM targets by fixing a bug (present since GCC 5, see link below) that affects conformance to the procedure call standard (AAPCS). The bug affects some C++ code where class objects are passed by value to functions and could result in incorrect or inconsistent code being generated. If the option -Wpsabi is enabled (on by default) the compiler will emit a diagnostic note for code that might be affected by this ABI change.
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=77728
For an explanation of the changes please see the following website:
https://gcc.gnu.org/gcc-7/changes.html
This snapshot1 is based on FSF GCC 7.4+svn267072 and includes performance improvements and bug fixes backported from mainline GCC. The contents of this snapshot will be part of the 2019.01 stable2 periodic release.
Interesting changes in this GCC source package snapshot include:
Updates to GCC 7.4+svn267072
Linaro bug 4007: “Internal compiler error with -mcpu=thunderx2t99” is fixed
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development.
o Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development mailing list:
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** Linaro Toolchain IRC channel on irc.freenode.net at #linaro-tcwg
* Bug reports should be filed in Bugzilla against GCC product:
http://bugs.linaro.org/enter_bug.cgi?product=GCC
* Interested in commercial support? inquire at Linaro support:
mailto:support@linaro.org
[1]. Source package snapshots are defined when the compiler is only
put through unit-testing and full validation is not performed.
[2]. Stable source package releases are defined as releases where the
full Linaro Toolchain validation plan is executed.
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== Progress ==
* SVE ACLE
- Revised svmla, svmls, svmad and svmsb and committed after getting ACK
- Revised again posted for review
* svabs, svneg, svnot and svsqrt series
* svdiv series
* svmulh series
* svand, svorr, and sveor series
* svdot series
== Plan ==
* Contine with sve acle
[LLVM-520] LLD Fix movt/movw relocation overflow
Now committed upstream.
[LLVM-521] Taking the address of an ifunc in AArch64
Prompted by a bug report and comment about pointer equivalence, spent
some time looking into gold, lld and bfd behaviour to ensure that LLD
is at least correct.
Other
Some investigation into LLD non-support of common-page-size and
whether this is significant for code-size. Used in response to query
about whether LLD should change default value of max-page-size.
Thoughts about whether a linker must generate cantunwind .ARM.exidx
sections for code sections missing a .ARM.exidx section. If C++ code
with exceptions is interleaved with some assembly code without
.ARM.exidx sections then the assembly code can match the address range
of the C++ code that precedes it.
Progress:
* VIRT-65 [QEMU upstream maintainership]
- code review:
+ rth's pointer-auth emulation patchset
+ more devices for the microbit board model
+ support for u-boot "noload" image type
+ gdbstub multiprocess extension support for use when the board
model has multiple asymmetric clusters (like Xilinx Zynq boards)
- finished debugging patch for aarch64 host linux-user to distinguish
SEGV on read from SEGV on write by looking at the ESR context struct
from the kernel rather than by looking at the faulting insn; sent it.
- sent patch to fix linux-user pread64/pwrite64 with NULL buffer and 0 length
* VIRT-268 [QEMU support for dual-core Cortex-M Musca board]
- Sent out patchset fixing heterogenous CPU support (required a lot
of thought about what we might need to fix and not all that much
code, in the end)
- Started work on refactoring our IoTKit model to also support
the extra pieces required by the SSE-200 subsystem used in the Musca
thanks
-- PMM