Hi Maxim, all,
Alex Matveev and I try to enable LTO optimization for Linux kernel
on ARM64. The work is based on patches from Andi Kleen, and is not
complete yet. Maxim recommended to work tightly with toolchain group
to understand how to fix problems better - on kernel or compiler side.
Links:
My unfinished branch:
https://github.com/norov/linux/tree/lto
Andi Kleen tree:
https://github.com/andikleen/linux-misc/tree/lto-411-1
Sami Tolvanen's recent work for clang:
https://lkml.org/lkml/2017/11/3/606
Question we have for now:
There's mrs_s/msr_s macro that doesn't work with LTO - linker
complains very loudly that macro is either not declared, or declared
multiple times. (To reproduce - try to build my kernel branch w/o last
patch).
The same (?) problem is observed with clang, and people there
considered it as feature, not a bug.
https://bugs.llvm.org/show_bug.cgi?id=19749
We have the fix for both clang and gcc, but it looks hacky. Maybe it
worth to fix mrs/msr issue on toolchain side?
Thanks,
Yury
Short week (off Wed/Thu/Fri)
== Progress ==
* GCC
- FDPIC: looking at patch stacks
* GCC upstream validation:
- got feedback from upstream about qemu and asan interaction since
recent merge: need to disable LSAN on arm.
- using qemu-2.7 again enables to workaround the timeout issues
observed last week
- worked on improving timeout handling
- restarted validations, but....
- validations on-hold since Nov 1st because of an ST-internal
infrastructure problem
* Infrastructure:
* misc (conf-calls, meetings, emails, ....)
== Next ==
* GCC upstream validation
* GCC/ubsan
* GCC/FDPIC
* 3 days off
== Progress ==
o Linaro GCC/Validation
o LLVM
* Continue ramp-up
* Upstream bug 32999:
- Reworked the fix and validate it
- Ready to be submitted upstream
* Start to look at sign-extension elimination status
o Misc
== Plan ==
o Release handover (5 release, 6 and 7 RCs)
o LLVM tasks (Bug 32999, sign-extension)
# Progress #
* TCWG-1040, [6/10]
Update my patches to remove the last use of MAX_REGISTER_SIZE.
Commit clean up and refactor patches. Find more clean up patches
in my tree. Keep upstreaming them. The design and implementation
of removing MAX_REGISTER_SIZE becomes more and more clear.
* TCWG-1125, [2/10] ARMv8 tagged address support in GDB.
v2 patches were posted. No comments yet.
* aarch64: PR 19806: watchpoints: false negatives + PR 20207 contiguous
ones. Patch review. [1/10]
* Think about the TODOs for GDB ILP32 support, write them down, and send
it to Maxim. [1/10]
# Plan #
* TCWG-1040, TCWG-1125.
--
Yao Qi
Hi ,
I am a SW engineer that use Linaro-toolchain to build images,
Recently, I encounter some issue about enable NEON features on ARMv8 processor platform.
I cat cpuinfo, can not find neon and vfp feature enable in list, the image was build with aarch-64 toolchian;
While, the image built by armv7l toolchain can list "neon and vfp" in cpuinfo.
I want to verify from your side,
1. if the toolchain of aarch64 version already enable" neon and vfp " in default, Because I do not find some build items that related with "neon",
2. If not supported defaultly, can you give some suggestion to enable it.
Thanks & B.R.
Joy Deng
