linaro-toolchain July 2014

linaro-toolchain@lists.linaro.org

23 participants
43 discussions

[Weekly] 21-25 JULY 2014

by Michael Collison

== This week == * TCWG Sprint (8/10) - Validation process greatly clarified including roadmap * Launchpad 1318831 - Invalid unpoisoning of stack redzones on ARM (2/10) - Finished validating and working thru git review isses with Launchpad == Next week == * Begin neon intrinsic testing * I will be off on Monday and Tuesday

10 years, 3 months

help, here is a armV8 32bit question for linaro 4.8: the code I given below adopt sembedding ARMV8 assembly , but the compile result with Linaro GCC 4.8 aarch32 is not correct

by Panshilin (Peter)

Hi all concerned: this test code I given below: AARCH32 [https://email-cn04.huawei.com/owa/14.3.158.1/themes/base/pgrs-sm.gif] Test function[X][X] { volatile unsigned int val0 = 0; volatile unsigned int val1 = 0; asm volatile(“mrrc p15, 1, %0, %1, c15” : “=r”(val0), “=r”(val1)) val0 &= ~(1<<6); val1 &= ~(1<<6); asm volatile(“mcrr p15, 1, %0, %1, c15” : “=r”(val0), “=r”(val1)); } After compiling, the result is: mrrc 15, 1, r2, r3, cr15 str r2, [fp, #-28] str r3, [fp, #-24] ldr r3, [fp, #-28] bic r3, r3, #64; str r3, [fp, #-28] ldr r3, [fp, #-24] bic r3, r3, #64 str r3, [fp, #-24] mcrr 15, 1, r2, r3, cr15 obviously , it is not what I expect. I have val0 an vl1 two vars, but the compiling result is only one val takes effect. especia I have to mention is AARCH32. thanks. Peter

10 years, 4 months

FW: Request received: accessing toolchain source releases - Member user

by Scott Douglass

Hi, Do you happen to know the answer to the git/svn questions below? Thanks. -----Original Message----- From: LDTS [mailto:support@linaro.zendesk.com] Sent: 25 July 2014 08:43 To: Scott Douglass Subject: Request received: accessing toolchain source releases - Member user Thank you for contacting Linaro. Your request (#927 <https://support.linaro.org/requests/927> ) has been received and is being reviewed by Linaro Developer Technical Support (LDTS). One of our Support agents will be in contact with you as soon as possible. If you would like our agent to contact you via phone, please include your phone number in the comments. To view your ticket and/or add additional comments, reply to this email or click the link below: http://support.linaro.org/requests/927 Scott Douglass Jul 25 16:43 Hi, I’ve been looking at https://wiki.linaro.org/WorkingGroups/ToolChain (https://wiki.linaro.org/WorkingGroups/ToolChain) and I see the Tree links that give me the git repository and commit id for the current releases of the toolchains (for example, 4.9-2014.06-1 => https://git.linaro.org/toolchain/gcc.git/commit/56d9fd9281e8cef3ea35b7d9ad8… (https://git.linaro.org/toolchain/gcc.git/commit/56d9fd9281e8cef3ea35b7d9ad8… My first question is: is there a straight-forward way (for example, a tag) to find the commit ids of older (4.9) releases? Or is searching the commit messages the best way? Also, is there svn access as well or just git access? (Git access is enough, but svn access would be slightly easier for me.) Also, I has a couple comments on that wiki page: It says “Pre-built versions that run on generic Linux or Windows are available at http://launchpad.net/linaro-toolchain-binaries.”, but it looks like the that Launchpad project is no longer being maintained (no 4.9 and no recent 4.8). Perhaps the wiki page should be updated (and the Launchpad description updated). The wiki page also links to https://wiki.linaro.org/Cycles/Next/Release/Status (https://wiki.linaro.org/Cycles/Next/Release/Status) which seems even more out-of-date than the Launchpad binaries; perhaps that link should be updated/removed, too. Thanks. -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782 ##- Please type your reply above this line -## Message-Id:5EV1YF0A_53d20a9134254_35e73f955b4b3338321343_sprut -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ARM Limited, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2557590 ARM Holdings plc, Registered office 110 Fulbourn Road, Cambridge CB1 9NJ, Registered in England & Wales, Company No: 2548782

10 years, 4 months

[ACTIVITY] 16 - 20 June

by Charles Baylis

* Linaro bugzilla #24 - [6/10] * investigating cause of ICE in Linaro 4.9 * PR61411 [1/10] * Committed patches for division (TCWG-???) and Neon address mode (TCWG-430) [1/10] * Admin [1/10] * Holiday [1/10]

10 years, 4 months

VFP in BE mode - undefined instruction vstmia

by Joel (Xi Zhou) Zhou

Hi all, I'm working on booting Linaro LSK 3.10.40 kernel in be8 mode on our Cortex-A9 system. There is an issue related to VFP instruction. It complain "vstmia" is an undefined instruction. The VFP is supported in CPU and CONFIG_VFP and CONFIG_VFPv3 are enabled in kernel config. Are there any patch need to be done for VFP in BE mode? The booting log show as following: call sys_access(/init) Freeing unused kernel memory: 2832K (c0600000 - c08c4000) kernel_init: try to execute '/init' (ramdisk_execute_command) en->run_init_process(/init) init (1): undefined instruction: pc=0000aab8 Code: f00f dff8 2a20 1268 (acec) 108b Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000004 The disassembly code show the undefined instruction is "vstmia". armeb-linux-gnueabihf-objdump -D busybox_unstripped > busy.asm 0000aa90 <__sigsetjmp>: ... aab6: 6812 ldr r2, [r2, #0] aab8: ecac 8b10 vstmia ip!, {d8-d15} aabc: f412 7f00 tst.w r2, #512 ; 0x200 The rootfs is busybox 1.22.1 compiled by Linaro BE hard floating toolchain. https://releases.linaro.org/14.04/components/toolchain/binaries/gcc-linaro-… Thanks, Joel

10 years, 4 months

[ACTIVITY] 14 - 18 July 2014

by Omair Javaid

== Progress == * On Holiday from 14th to 17th July 2014. * Travel to Cambridge to attend TCWG Sprint and GNU Tools Cauldron on Friday 18th July. == Plan == * Attend GNU Tools Cauldron 18th to 20th July. * Attend TCWG Sprint 21st to 24th July. * Friday 18th July return back after attending TCWG Sprint and GNU Tools Cauldron in UK.

10 years, 4 months

[ACTIVITY] 7 - 11 July 2014

by Omair Javaid

== Progress == * Testing and Analysis of testsuite failures in arm-linux-gdb [TCWG-509] [6/10] -- Run ARM GDB testsuite on local chromebook, remote chrombook and pandaboards. -- Investigation of failures on arm. * AArch64 GDB handling of functions with empty prologue. [TCWG-504] [1/10] -- Short list aarch64 prologue skipping requirements. * Browsing gdb related upstream discussions and reviewing aarch64 regset rework stuff. [1/10] * Preparation for travel to UK, obtaining medical NOC document for international travel. [2/10] == Plan == * On Holiday from 14th to 17th July 2014. * Travel to Cambridge to attend Sprint and Cauldron.

10 years, 4 months

[ACTIVITY] July 14th - 18th

by Bernie Ogden

=Progress= cbuild2 benchmarking - TCWG-360 [7/10] * Much fighting with benchmarking branch on a panda * Ported eembc benchmarking over to my way of doing things * A bit of cleanup around the 'reduce noise by shutting down services' stuff * Slew my ailing Ubuntu VM, started bringing up a beagle as a 2nd sacrificial target lowlevellock.h - TCWG-435 [1/10] * Roland patch review/thinking about how to test a corner case Meetings/mail/etc [2/10] =Plan= Cauldron/TCWG sprint Hopefully some cbuild2 benchmarking progress

10 years, 4 months

[ACTIVITY] 14 - 18 July 2014

by Will Newton

== Progress == * Annual leave Monday to Wednesday (6/10) * Travel to Cauldron/Sprint (2/10) * Catching up on email, pushing patches, bugs etc. (2/10) == Issues == * None == Plan == * GNU Tools Cauldron * Toolchain Sprint -- Will Newton Toolchain Working Group, Linaro

10 years, 4 months

[ANNOUNCE] Linaro GCC 4.9 2014.07 released

by Yvan Roux

The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.07 stable release of the Linaro GCC 4.9 source package. Linaro GCC 4.9 2014.07 is the fourth Linaro GCC source package release in the 4.9 series. It is based on FSF GCC 4.9.1+svn212419 and includes performance improvements and bug fixes. With the imminent release of ARMv8 hardware and the recent release of the GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and performance of the compiler as the FSF GCC compiler approaches version 4.9.1. The Linaro TCWG will provide monthly stable[1] source package releases until FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of stable quarterly releases and monthly engineering[2] releases. Interesting changes in this GCC source package release include: * Updates to GCC 4.9.1-pre+svn212419 * Backport of [AArch32] Wrap long literals in HOST_WIDE_INT_C in aarch-common.c * Backport of [AArch32] Rewrite TLC Intrinsics. * Backport of [AArch32] Remove vzip, vuzp, vtrn builtins and cleanup * Backport of [AArch32] Use enum name instead of integer value for PARAM_SCHED_PRESSURE_ALGORITHM. * Backport of [AArch32] Vectorise bswap* * Backport of [AArch32] Fix PR/61331 * Backport of [AArch32] Fix PR target/61154 * Backport of [AArch32] Use mov_imm type for movw operations consistently * Backport of [AArch32] Remove XFmode from ARM backend. * Backport of [AArch64] Rewrite REV Intrinsics. * Backport of [AArch64] Implement HARD_REGNO_CALLER_SAVE_MODE. * Backport of [AArch64] Support tail indirect function call. * Backport of [AArch64] Fix stack protector for ILP32 * Backport of [AArch64] ILP32 dynamic linker * Backport of [AArch64] Correct signedness of builtins, remove casts from arm_neon.h * Backport of [AArch64] clarify stack layout diagram * Backport of [AArch64] Implement movmem for the benefit of inline memcpy * Backport of [AArch64] Fix REG_CFA_RESTORE mode. * Backport of [AArch64] Fix layout of frame layout code. * Backport of [AArch64] Fix some reg-to-reg move scheduler types. * Backport of [AArch64] Implement CRC32 ACLE intrinsics + testsuite. * Backport of [AArch64] Implement ADD in vector registers for 32-bit scalar values. * Backport of [AArch32/AArch64] TARGET_ATOMIC_ASSIGN_EXPAND_FENV AArch64 * Backport of [AArch32/AArch64] Use signed chars in gcc.dg/pr60114.c. * Backport of [AArch32/AArch64] Rewrite UZP Intrinsics. * Backport of [AArch32/AArch64] Rewrite TRN Intrinsics. * Backport of [AArch32/AArch64] Rewrite EXT Intrinsics. * Backport of [genattrtab] Fix memory corruption, allocate enough memory for all bypassed reservations * Backport of Fix PR c/60114 Feedback and Support Subscribe to the important Linaro mailing lists and join our IRC channels to stay on top of Linaro development. ** Linaro Toolchain Development "mailing list": http://lists.linaro.org/mailman/listinfo/linaro-toolchain ** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@ * Bug reports should be filed in Launchpad against "Linaro GCC project": http://bugs.launchpad.net/gcc-linaro/+filebug. * Questions? "ask Linaro": http://ask.linaro.org/. * Interested in commercial support? inquire at "Linaro support":mailto: support(a)linaro.org [1] Stable source package releases are defined as releases where the full Linaro Toolchain validation plan is executed. [2] Engineering source package releases are defined as releases where the compiler is only put through unit-testing and full validation is not performed.

10 years, 4 months

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linaro-toolchain July 2014