== Issues ==
* None.
== Progress ==
* Work out 4 patches to enhance loop2-invariant heuristics and send
out for community review (TCWG-469, 3/10).
* Test the rebased ccmp patches (TCWG-488, 2/10).
* Investigate how to optimize large constant. Patch is in testing
(TCWG-486, 5/10). Basic idea is:
- Do not split large constant when expanding.
- Improve cprop pass to check the rtx_cost when propagating constants.
== Plans ==
* Ping pending patches.
* Send out ccmp patches for review.
* Send out patches to optimize constant.
== Progress ==
* Kernel (CARD-1246 1/10)
- Helping LLVMLinux to test in LAVA
* Background (9/10)
- Code review, meetings, discussions, etc.
- Setting up Chromebooks again (up, crouton)
- Setting up APM boards (up)
- Setting up D01 boards (bricked 2)
== Plan ==
* work with guodong, fabo, tyler, to revive the D01s
* put crouton on llvm-chrome-test to be ready for release 3.5
* have a look at compiler-rt autoconf build
* keep helping LLVMLinux with LAVA
Monday off. (2/10)
== Progress ==
* GCC trunk cross-validation (CARD-647) (3/10)
- improved scripts to avoid consuming to much memory
- improved kill signals handling when generating reports
- back to normal
- started looking at adding libstdc++ in the reports
- started looking at adding aarch32/armv8 configuration
- email-driven robot looks operational. Started testing with Kugan
* GCC 4.9 branch cross-validation (CARD-647)
- it's now running
* Neon intrinsic tests (CARD-???) (2/10)
- discussion started: scan-assembler directives may be difficult to maintain
- original testsuite maintenance: preparing aarch64 support
* AArch64 libsanitizer support (TCWG-58)
- Venkat tested my patch on HW, need to study the results and
compare with qemu
* Misc (meetings, conf-calls, ...) (3/10)
- 4.7-2014.06 branch merge prepared, validation started
== Next ==
* GCC cross-validation
- check patch to add libstdc++ in the reports
- define configuration for aarch32/armv8
- continue testing of the email robot
* Neon intrinsics tests:
- handle feedback
- original testsuite: continue aarch64 support, investigate output
formatting problems
* AArch64 libsanitizer support:
- analyze results
- use cbuild2 + tcwgbuild configs to run the tests myself on HW
* Backports reviews
The Linaro Toolchain Working Group (TCWG) is pleased to announce the 2014.06
stable release of the Linaro GCC 4.9 source package.
Linaro GCC 4.9 2014.06 is the third Linaro GCC source package release in the
4.9 series. It is based on FSF GCC 4.9.1+svn211054 and includes performance
improvements and bug fixes.
With the imminent release of ARMv8 hardware and the recent release of the
GCC 4.9 compiler the Linaro TCWG will be focusing on stabilization and
performance of the compiler as the FSF GCC compiler approaches version 4.9.1.
The Linaro TCWG will provide monthly stable[1] source package releases until
FSF GCC 4.9.1 is released. At that point Linaro GCC 4.9 will merge in
FSF GCC 4.9.1 and, release Linaro GCC 4.9.1, and then return to a schedule of
stable quarterly releases and monthly engineering[2] releases.
Interesting changes in this GCC source package release include:
* Updates to GCC 4.9.1+svn211054
* Backport of [AArch32] PR rtl-optimization/60663
* Backport of [AArch32] Suppress Redundant Flag Setting for Cortex-A15.
* Backport of [AArch32] Support ORN for DIMode.
* Backport of [AArch32] Optimise NotDI AND/OR ZeroExtendSI for ARMv7A.
* Backport of [AArch32] Allow any register for DImode values in Thumb2.
* Backport of [AArch32] Initialize new tune_params values.
* Backport of [AArch32] Initialise T16-related fields in Cortex-A8
tuning struct.
* Backport of [AArch32] Enable tail call optimization for long call.
* Backport of [AArch64] TRY_EMPTY_VM_SPACE Change for ILP32.
* Backport of [AArch64] Fix TLS for ILP32.
* Backport of [AArch64] vrnd<*>_f64 patch.
* Backport of [AArch64] Fix possible wrong code generation when
comparing DImode values.
* Backport of [AArch64] Add a space to memory asm code between base
register and offset.
* Backport of [AArch64] Fix aarch64_initial_elimination_offset calculation.
* Backport of [AArch64] vqneg and vqabs intrinsics implementation.
* Backport of [AArch64] Vreinterpret re-implemention.
* Backport of [AArch64] Define TARGET_FLAGS_REGNUM.
* Backport of [AArch64] Merge longlong.h from glibc tree.
* Backport of [AArch64] add, sub, mul in TImode.
* Backport of [AArch64] Add handling of bswap operations in rtx costs.
* Backport of [AArch64] Fully support rotate on logical operations.
* Backport of [AArch64] Use standard patterns for stack protection.
* Backport of [AArch64] VDUP Testcases.
* Backport of [AArch64] Vectorise bswap[16,32,64].
* Backport of [AArch64] Enable TBL for big-endian.
* Backport of [AArch64] Reverse TBL indices for big-endian.
* Backport of [AArch64] Relax modes_tieable_p and cannot_change_mode_class.
* Backport of [AArch64] Improve vst4_lane intrinsics.
* Backport of [AArch64] Rewrite and tests ZIP Intrinsics.
* Backport of [AArch64] libitm Enabled.
* Backport of [AArch64] Support full addressing modes for ldr/str in
vectorization scenarios
* Backport of [AArch32/AArch64] rtx costs (FMA, Cortex-A8, ...).
* Backport of Fix warning in libgfortran configure script.
* Backport of Remove PUSH_ARGS_REVERSED from the RTL expander
Feedback and Support
Subscribe to the important Linaro mailing lists and join our IRC channels to
stay on top of Linaro development.
** Linaro Toolchain Development "mailing list":
http://lists.linaro.org/mailman/listinfo/linaro-toolchain
** Linaro Toolchain IRC channel on irc.freenode.net at @#linaro-tcwg@
* Bug reports should be filed in Launchpad against "Linaro GCC project":
http://bugs.launchpad.net/gcc-linaro/+filebug.
* Questions? "ask Linaro":
http://ask.linaro.org/.
* Interested in commercial support? inquire at "Linaro support":mailto:
support(a)linaro.org
[1] Stable source package releases are defined as releases where the full Linaro
Toolchain validation plan is executed.
[2] Engineering source package releases are defined as releases where the
compiler is only put through unit-testing and full validation is not
performed.
== Progress ==
* GDB arm v8 record/replay
-- Fixed issues showing up when building code with default
optimization. [TCWG-484] [3/10]
-- Fixed failures in until-reverse test cases. [TCWG-484] [1/10]
-- Investigation of failures in watchpoint-reverse and solib test
cases. [TCWG-484] [2/10]
-- Writing NEWS and changelog entries for all patches. [1/10]
* GDB Remote vs Native feature parity (GDB on Android improvements)
[2/10] [CARD-321]
-- Scored through recently submitted patches.
-- Ran testsuite in native and remote modes.
-- Started review of related open jira cards
* Miscellaneous
-- Visit uk visa office for passport collection. [1/10]
== Plan ==
* GDB arm v8 record/replay
-- Update all patches after upstream comments.
-- Investigate all remaining testsuite failures.
-- Update all related jira cards and create new for persisting test failures.
* GDB arm v7 record/replay
-- Update and resubmit upstream.
* GDB Remote vs Native feature parity (GDB on Android improvements) [CARD-321]
-- Further progress towards creating a tasks list and timeline.
* Miscellaneous
-- Finalize travel and obtain health certificate for travel to UK.
== Progress ==
* Zero/sign extension elimination (TCWG-15) (2/10)
- Posted patch for comment
* benchmarking (TCWG-468) (1/10)
- Ran a53 benchmarks
* regressions (7/10)
- THUMB1 regression for ARM fenv
* Issue due to thumb1 not supporting mrc/mcr. Patch to fix this is
posted for review.
- Regression when allocating 128bit integer to VFP register
* When LRA assigns DImode value to TImode register, it is not
setting up it in the right place of TImode. Due to this, one of the
moves becomes dead. Patterns needs to be checked.
* VFP registers store big-endian values in little-endian format.
Hence, subreg for mode greater than word has to
be aware of this. As it is, aarch64_cannot_change_mode_class will need
the fix like done in ARM.
== Plan ==
* Benchmarking.
* Upstream zero/sign extension elimination activities.
= Progress ==
* LTO experiments (3/10)
Tested with various compiler revisions and in native X86 machines. Compare
errors in gcc 4.9 Linaro 14.05 version. Aarch64, LTO bootstrap passes in
trunk. On FSF GCC 4.9 branch encountering ICE. Opened PRs in GCC Bugzilla.
* Misc (2/10)
- 1-1 meetings (Ryan, Christophe and Maxim) (0.5/10)
- AMD internal support work and meetings (0.5/10)
Sick Leave on 2nd June (2/10)
UK VISA application processing (3/10)
== Plan ==
* UK VISA processing attend interview, biometrics.
* Continue bug fixing.
* LTO bootstrap failure
* Test libsanitizer patch for christophe.
=Progress=
lowlevellock performance bugs - TCWG-435 [1/10]
* All ready to go
cbuild benchmarking - TCWG-360 [4/10]
* Completed a draft implementation for spec2k
* Parked pending review
Meetings/mail/etc [5/10]
=Plan=
Send lowlevellock patches to list
Get back to benchmarking/improving cortex-strings memset
