== Progress ==
* GDB arm v8 record/replay
-- Completed implementation of system call recording [TCWG-409] [4/10]
-- Support for recording A64 Loads and stores [TCWG-409] [2/10]
-- Bug Fixing to reduce failures in gdb.reverse testsuite [TCWG-484] [2/10]
* Miscellaneous
-- Day off on Friday [2/10]
== Plan ==
* GDB arm v8 record/replay
-- Submission of patches upstream.
-- Bug fixing to reduce failures.
-- Advance SIMD load/store instruction recording support.
== Issue ==
* None.
== Progress ==
* Investigate PR61220, 61225 and 61278, which are triggered by my
previous commits. Patches are in review. (9/10)
* Investigate codes generated by shrink-wrapping interrupt routes. It
seams no dwarf info issue.
* Misc update for Linaro crosstool-ng to make the build work in case
someone wants to use it.
- Down grade gdb to 7.6.
- Disable multilib for 4.9.
- Move local patches at binutils/linaro-2.24.0-2014.03 to
binutils/linaro-2.24.0-2014.05.
== Plans ==
* Push pending patches.
== Planed leaves ==
* June. 2.
Hi,
I've run into some compile errors after updating to 4.9 -- usually getting
undefined references to symbols defined in helper static libraries.
It turns out this is triggered by gcc -flto now creating slim object files
by default (-ffat-lto-objects "fixes" it) - but I think it is actually an
ld bug that should be fixed at some point. ld (regardless of whether I use
-fuse-linker-plugin, -fuse-ld=gold or -fuse-ld=bfd) doesn't seem to see LTO
bytecode in object files that are inside an ar wrapper.
It deals with the library just fine if I use "ar x" to extract its object
files and link to them individually as opposed to the .a file.
I've attached a small test case to demonstrate ("make broken" shows the
error, "make works" shows the workaround).
Is there any reason why ld should behave the way it does, or is this a bug
that needs fixing?
ttyl
bero
== Progress ==
* Reload - IRA bug fix (3/10)
Not able to reproduce in trunk, r210538 masks the bug again :(
Discussed with maxim on extending the macro ,Likely spilled class for thumb2.
Decided that it will lead to performance regressions. Conservative fix
is to allow the pattern for ARM target alone. Verfying the fix by on
armhf schroot
* Testing GCC Linaro compiler on Hardware (4/10)
Completed GCC Linaro compiler 4.8 and 4.9 correctness tests on
hardware. Completed running SPEC 2006 for -O3. Completed running
SPEC2006 for -O3 -ftlo and -mcpu=cortex-a57. Triggered PGO runs on
hardware.
Looked at bootstrap failure with BOOT_CFLAGS="-mcpu=cortex-a57".
Changed from system assembler to Linaro assembler solved it as system
assembler is old.
* Misc (3/10)
- Completed installing ubuntu, set up chroot and migrate to toolchain
64 environment. (2/10)
- 1-1 meetings (Ryan, Christophe and Maxim) (1/10)
- AMD internal support work and meetings
== Plan ==
* Continue bug fixing.
* LTO bootstrap failure
* Testing GCC Linaro compiler on hardware.
* UK VISA processing.
== Issues ==
* None
== Progress ==
* CARD-1162 : Linaro GCC 4.9 and CARD-1355 : stabilization and
optimization effort for ARMv8-a (8/10)
- Looked at Jenkins build/failures/reportin
- Review the backporting process and scripted it
- 40 backports are in review and need validation
* LP #1169164 : including signal.h exposes various PSR_MODE #defines
- Committed upstream.
* Misc:
o Various meetings (2/10)
o LCU'14: Register and booked flights
== Next ==
* Child care today
* Improve the backport script and document it's usage
* Continue backports
* Continue feedback and help with the validation
== Progress ==
* GCC trunk cross-validation (4/10)
- build broken last week-end, because of a
new optimization that broke glibc build.
- glibc fixed by Joseph mid-week, updated
- to help diagnose build failures earlier, I have setup
a reduced version of the validation framework,
which only performs a build of binutils+glibc+gcc,
at every commit on gcc trunk for 16 arm+aarch64
configurations. [ yes, another buildbot of sorts ]
- restarted builds+validations to last known successful
status (i.e. before last week-end)
- builds are catching up
* Neon intrinsics tests (3/10)
- continuing conversion (about 40 files done, out of ~140)
* Misc (meetings, conf-calls, ...) (3/10)
* Backports for 4.9:
- started reviewing candidate backports
== Next ==
* GCC trunk cross-build/cross-validation:
- monitor and report regressions
* Neon intrinsics tests:
- continue conversion
- prepare a cleaner branch for upstream submission
* Backports:
- more reviews
- process improvements
== Progress ==
* Kernel (CARD-1246 4/10)
- Named registers committed in Clang
- GCC seems to break on local named regs, too.
- Trying to change the kernel code to use only globals for non-GPRs
- Adding support for pointer types, and structure fields in GNRVs
* Benchmarks (CARD-716 0/10)
- Re-enabling perf reports for LNT bot (ARM fixed reporting)
* Background (6/10)
- Code review, meetings, discussions, etc.
- Removing *all* buildbots' batteries after failure
- Testing D01 box, not stable yet for toolchain testing
- Moving development to git.linaro.org (for backup)
- Planning TCWG rack migration
- Drafting an LLVM white paper
== Plan ==
* Continue with named register extra work (http://llvm.org/PR19837)
* Start TCWG rack migration
* Discussions about LLVM white paper
== Progress ==
* Investigate and fix building glibc for ARM with -mtls-dialect=gnu2 (3/10)
* Investigate ld TLS behaviour for Huawei (1/10)
* Refactor scripts to enable benchmarking postgresql malloc
performance (2/10, TCWG-441)
* Patch review and testing (1/10)
* Diagnose and fix glibc testsuite failures on aarch64 (2/10)
* Meetings, admin (1/10)
== Issues ==
* None
== Plan ==
* More malloc application benchmarking
--
Will Newton
Toolchain Working Group, Linaro
== Progress==
lowlevellock performance bugs - TCWG-435 [5/10]
* Tried various methods to build/test glibc for aarch64
* Eventually succeeded (tests passed)
cbuild benchmarking - TCWG-360 [3/10]
* cbuildized spec2xxx scripts working as far as 'run'
Meetings/mail/etc [2/10]
== Plan ==
Holiday for one week
After that:
* Clean up cbuildized spec2xxx scripts, cbuildize them some more &
discuss with Rob
* Send lowlevellock patch upstream
* If time, put together some more experimental memset implementations
