linaro-toolchain January 2011

linaro-toolchain@lists.linaro.org

23 participants
53 discussions

Backporting a patch from upstream and bzr workflows.

by Ramana Radhakrishnan

Hi , So rather than manually backporting a patch from upstream "trunk" I decided to try using bzr for this yesterday. Even though this was a slow process and thanks to some help from Michael on IRC last night I think I got it right finally. However I can't get bzr visualize to show me the revision history correctly with the merge from the upstream repository. So what I did was to do the following bzr branch 4.5 new-branch cd new-branch bzr merge -c XXX lp:gcc where XXX is the bzr revision number of the svn commit that I'm tracking upstream. gcc/Changelog merge fails - there is a conflict. Expected because you are merging trunk's gcc/Changelog into a version of the Changelog file in our tree Thus I reverted changes that were brought in by copying in a backup of gcc/Changelog that I had made before the merge bzr resolved gcc/Changelog edit Changelog.linaro Add changelog entry bzr commit bzr push lp:gcc private repository Create merge request upstream. Does this look sensible to people or do folks follow other recipes? cheers Ramana

13 years, 10 months

Fwd: RE: [RFC][PATCH] ARM: ptrace: remove single-step emulation code

by Loïc Minier

Hey I think we need to keep an eye on this and be ready to check ltrace if this gets merged Cheers -- Loïc Minier

13 years, 10 months

Monday's meeting

by Michael Hope

Hi there. I've cancelled Monday's meeting as the CodeSourcery people are at their annual meeting and others are travelling back from the sprint. Please come to the Wednesday stand up call if you are available. -- Michael

13 years, 10 months

[ACTIVITY] 2011-01-14

by David Gilbert

Got a complete run of SPEC Train on Orion board - all working. Kicked off a SPEC ref run - canis1 died. Gathered a full set of 'perf record's for all of SPEC on silverbell; and had a quick look through them; there aren't too many surprises; a few things that might be worth a look at though. (Not as much using libc functions as I hoped). There are some odd bits - chunks of samples landing apparently outside libraries that aren't obvious what's going on. Sent tentative patch for Thumb perf annotate issue (bug 677547) to lkml for comments. Started on libffi variadic fixing. Caught the qemu pbx-a9 testing from PM; got qemu built and getting a handful of lines of output both from a kernel from arm.com's site and a linaro-2.6.37 that I built for it. Dave

13 years, 10 months

[ACTIVITY] report week 02

by Peter Maydell

RAG: Red: Amber: Green: issues I wanted to nail at this sprint all handled; a couple of blueprints handed off to other people Milestones: | Planned | Estimate | Actual | finish virtio-system | 2010-08-27 | postponed | | finish testing PCI patches | 2010-10-01 | 2010-10-22 | 2010-10-18 | successful ARM qemu pull req | 2010-12-16 | 2010-12-16 | 2010-12-16 | finish qemu-cont-integration | 2010-01-25 | 2010-01-25 | | At the Linaro/Ubuntu sprint/rally in Dallas this week * qemu-continuous-integration ** spoke to Paul Larson (in Linaro Validation team) and handed this blueprint off to him (with a clarification of the requirements from qemu's point of view) * maintain-beagle-models ** we've agreed to start doing official "Linaro Qemu" releases which are essentially going to be the meego tree plus point fixes for things. These will be every month with the rest of the toolchain group releases. Ubuntu will also take these releases to replace the current use of the qemu-kvm tree to provide ARM models * verify-a9-pbx-support ** this blueprint has been handed off to David Gilbert * merge-correctness-fixes ** wrote and posted patches: *** to restore IT bits after unexpected exceptions (including fix of Linux usermode bug where it wasn't clearing the IT bits when entering a signal handler) *** to include opcode hex in disassembly of ARM insns *** fixing a compile failure for a previous change when the host linux system didn't have linux/fiemap.h ** I have managed to split the huge "lots of ARM TCG fixes" commit in the meego tree up into 65 more self-contained commits. These now need reordering and possibly some may be recombined. Current qemu patch status is tracked here: https://wiki.linaro.org/PeterMaydell/QemuPatchStatus Absences: 2011: Holiday 21 Jan, 22 Apr - 2 May.

13 years, 10 months

x86_64 bootstrap failure in the 2011.01 release

by Michael Hope

Hi there. Unfortunately the Linaro GCC 4.5 2011.01-0 release has a failure in the x86_64 compiler causing it to fail during the initial build. We're working on triaging the problem at the moment. ARM and i386 targets are not affected. I'll send a new announcement when the problem has been fixed and the replacement 2011.01-1 release is available. -- Michael

13 years, 10 months

Linaro GCC 4.4 and 4.5 2011.01-0 released

by Andrew Stubbs

The Linaro Toolchain Working Group is pleased to announce the release of both Linaro GCC 4.4 and Linaro GCC 4.5. The Linaro Toolchain Working Group is pleased to announce the release of both Linaro GCC 4.4 and Linaro GCC 4.5. Linaro GCC 4.4 is the sixth release in the 4.4 series. Based off the latest GCC 4.4.5, it is a maintenance release that fixes one problem found through use. Linaro GCC 4.5 is the sixth release in the 4.5 series. Based off the official GCC 4.5.2 release, it includes many ARM-focused performance improvements and bug fixes. Interesting changes include: * Improved optimization of multiple load instructions, and multiply-and-accumulate. * -fshrink-wrap optimization for better use of function prologues and epilogues. * plus, various other bug fixes, and minor improvements. The source tarballs are available from: https://launchpad.net/gcc-linaro/+milestone/4.5-2011.01-0 and https://launchpad.net/gcc-linaro/+milestone/4.4-2011.01-0 Downloads are available from the Linaro GCC page on Launchpad: https://launchpad.net/gcc-linaro

13 years, 10 months

[ACTIVITY] January 9-13

by Ira Rosen

Hi, * Continued with testing and implementation of reduction support in SLP * Found a major problem in vectorization of if-converted data accesses. Looked into other ways to solve the problem. * Spent some time on non-Linaro vectorization plans * Unsuccessfully tried to make the board work Ira

13 years, 10 months

[ACTIVITY] Jan. 3rd -- Jan. 9th

by Yao Qi

== Last Week == * Displaced stepping support for 32-bit Thumb insns are done, unless new bugs are found. Decode writeback for str/ldr in Thumb 32-bit. Fix bugs in supporting LDR/STR/LDRH/STRH in both ARM and Thumb. Test GDB to handle various 32-bit Thumb insns in displaced stepping. Code cleanup and write some new test cases. * One day New Year holiday on Jan. 3rd. == This Week == * Linaro Sprint. * Get patches for Linaro GDB bugs approved on upstreams as many as possible. -- Yao Qi

13 years, 10 months

A question about instructions latencies in Crotex-A9

by Revital1 Eres

Hello, While testing SMS on Crotex-A9 I see that the latency of load instruction is 1 cycle when compiling with -mcpu=cortex-a9 -mthumb -mtune=cortex-a9 -O3. Below is a snippet from the SMS dump file showing the DDG, created for the loop in foo function, which depicts the edge between the load of input[i] (insn 181) and the mult instruction (insn 184). [181 -(T,1,0)-> 184] is the true dependence edge created between the two insns; with latency of 1. On Crotex-A8 the latency of the load is 3 as expected. I've read in crotex-a9.md file that loads should have a latency of 4 cycles so I just wanted to check if I should have used other combination of flags for Crotex-A9 or the load latency should indeed be of 1 cycle here. Thanks, Revital int foo (int max, signed short *input, int y) { int i, accum; for (i = 0; i < max; i++) { accum += (signed int) input[i] * (signed int) input[i+y]; } return accum; } The snippet from the DDG: Node num: 2 (insn 181 178 184 13 (set (reg:SI 216 [ D.2019 ]) (zero_extend:SI (mem:HI (plus:SI (reg:SI 319 [ ivtmp.34 ]) (reg:SI 345)) [2 MEM[base: D.2076_257, index: D.2079_226, offset: 0B]+0 S2 A16]))) tmp.c:7 714 {*thumb2_zero_extendhisi2_v6} (nil)) OUT ARCS: [181 -(A,0,1)-> 176] [181 -(T,1,0)-> 184] IN ARCS: [184 -(A,0,1)-> 181] [176 -(T,1,0)-> 181] Node num: 3 (insn 184 181 234 13 (set (reg/v:SI 209 [ accum ]) (plus:SI (mult:SI (sign_extend:SI (subreg/s/u:HI (reg:SI 212 [ D.2013 ]) 0)) (sign_extend:SI (subreg/s/u:HI (reg:SI 216 [ D.2019 ]) 0))) (reg/v:SI 209 [ accum ]))) tmp.c:7 64 {maddhisi4} (expr_list:REG_DEAD (reg:SI 216 [ D.2019 ]) (expr_list:REG_DEAD (reg:SI 212 [ D.2013 ]) (nil))))

13 years, 10 months

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linaro-toolchain January 2011