On Monday 02 May 2011, David Brown wrote:
I'll confirm this from the Qualcomm side as well. You cannot have multiple inconsistent mappings of the same page without having difficult to find problems.
I believe Catalin was referring to the case where you have only one nonconsistent (cacheable) mapping plus multiple consistent (cacheable) mappings. I don't think anyone has suggested doing DMA to a page that has multiple nonconsistent mappings with virtually indexed caches.
The spec clarifications appear to give ways of dealing with it if it happens, and bounds on what can go wrong, but I wouldn't call it something we want to do normally. Corrupt data is arguably less of a problem than nasal demons, but still a problem.
Anything that has a theoretical chance of corrupting data is not an option, but I'd really like to see what the clarified spec says about this. Even if there is a way to legally leave a page for dma_alloc_coherent in the linear mapping, it might turn out to be harder to do than using highmem pages or unmapping supersections at run time as was suggested.
Arnd