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TOP 4 BEST GOOD CRYPTOCURRENCY RECOVERY SPECIALIST FOR LEGITIMATE CRYPTO RECOVERY IN 2026

by angelaasher62＠gmail.com

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1 month

Re: [PATCH RFC 12/18] accel/qda: Add PRIME dma-buf import support

by Christian König

On 2/23/26 20:09, Ekansh Gupta wrote: > [Sie erhalten nicht häufig E-Mails von ekansh.gupta(a)oss.qualcomm.com. Weitere Informationen, warum dies wichtig ist, finden Sie unter https://aka.ms/LearnAboutSenderIdentification ] > > Add PRIME dma-buf import support for QDA GEM buffer objects and integrate > it with the existing per-process memory manager and IOMMU device model. > > The implementation extends qda_gem_obj to represent imported dma-bufs, > including dma_buf references, attachment state, scatter-gather tables > and an imported DMA address used for DSP-facing book-keeping. The > qda_gem_prime_import() path handles reimports of buffers originally > exported by QDA as well as imports of external dma-bufs, attaching them > to the assigned IOMMU device That is usually an absolutely clear NO-GO for DMA-bufs. Where exactly in the code is that? > and mapping them through the memory manager > for DSP access. The GEM free path is updated to unmap and detach > imported buffers while preserving the existing behaviour for locally > allocated memory. > > The PRIME fd-to-handle path is implemented in qda_prime_fd_to_handle(), > which records the calling drm_file in a driver-private import context > before invoking the core DRM helpers. The GEM import callback retrieves > this context to ensure that an IOMMU device is assigned to the process > and that imported buffers follow the same per-process IOMMU selection > rules as natively allocated GEM objects. > > This patch prepares the driver for interoperable buffer sharing between > QDA and other dma-buf capable subsystems while keeping IOMMU mapping and > lifetime handling consistent with the existing GEM allocation flow. > > Signed-off-by: Ekansh Gupta <ekansh.gupta(a)oss.qualcomm.com> ... > @@ -15,23 +16,29 @@ static int validate_gem_obj_for_mmap(struct qda_gem_obj *qda_gem_obj) > qda_err(NULL, "Invalid GEM object size\n"); > return -EINVAL; > } > - if (!qda_gem_obj->iommu_dev || !qda_gem_obj->iommu_dev->dev) { > - qda_err(NULL, "Allocated buffer missing IOMMU device\n"); > - return -EINVAL; > - } > - if (!qda_gem_obj->iommu_dev->dev) { > - qda_err(NULL, "Allocated buffer missing IOMMU device\n"); > - return -EINVAL; > - } > - if (!qda_gem_obj->virt) { > - qda_err(NULL, "Allocated buffer missing virtual address\n"); > - return -EINVAL; > - } > - if (qda_gem_obj->dma_addr == 0) { > - qda_err(NULL, "Allocated buffer missing DMA address\n"); > - return -EINVAL; > + if (qda_gem_obj->is_imported) { Absolutely clear NAK to that. Imported buffers *can't* be mmaped through the importer! Userspace needs to mmap() them through the exporter. If you absolutely have to map them through the importer for uAPI backward compatibility then there is dma_buf_mmap() for that, but this is clearly not the case here. ... > +static int qda_memory_manager_map_imported(struct qda_memory_manager *mem_mgr, > + struct qda_gem_obj *gem_obj, > + struct qda_iommu_device *iommu_dev) > +{ > + struct scatterlist *sg; > + dma_addr_t dma_addr; > + int ret = 0; > + > + if (!gem_obj->is_imported || !gem_obj->sgt || !iommu_dev) { > + qda_err(NULL, "Invalid parameters for imported buffer mapping\n"); > + return -EINVAL; > + } > + > + gem_obj->iommu_dev = iommu_dev; > + > + sg = gem_obj->sgt->sgl; > + if (sg) { > + dma_addr = sg_dma_address(sg); > + dma_addr += ((u64)iommu_dev->sid << 32); > + > + gem_obj->imported_dma_addr = dma_addr; Well that looks like you are only using the first DMA address from the imported sgt. What about the others? Regards, Christian.

1 month

Re: [PATCH RFC 11/18] accel/qda: Add GEM_CREATE and GEM_MMAP_OFFSET IOCTLs

by Christian König

On 2/23/26 20:09, Ekansh Gupta wrote: ... > +int qda_ioctl_gem_mmap_offset(struct drm_device *dev, void *data, struct drm_file *file_priv) > +{ > + struct drm_qda_gem_mmap_offset *args = data; > + struct drm_gem_object *gem_obj; > + int ret; > + > + gem_obj = qda_gem_lookup_object(file_priv, args->handle); > + if (IS_ERR(gem_obj)) > + return PTR_ERR(gem_obj); > + > + ret = drm_gem_create_mmap_offset(gem_obj); > + if (ret == 0) > + args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node); > + > + drm_gem_object_put(gem_obj); > + return ret; You should probably use drm_gem_dumb_map_offset() instead of open coding this. Otherwise you allow mmap() of imported objects which is not allowed at all. Regards, Christian.

1 month

Re: [PATCH RFC 06/18] accel/qda: Add memory manager for CB devices

by Bjorn Andersson

On Tue, Feb 24, 2026 at 12:39:00AM +0530, Ekansh Gupta wrote: > Introduce a per-device memory manager for the QDA driver that tracks > IOMMU-capable compute context-bank (CB) devices. Each CB device is > represented by a qda_iommu_device and registered with a central > qda_memory_manager instance owned by qda_dev. > The name makes me expect that this manages memory, but it seems to manage devices and context banks... > The memory manager maintains an xarray of devices and assigns a > unique ID to each CB. It also provides basic lifetime management > and a workqueue for deferred device removal. qda_cb_setup_device() > now allocates a qda_iommu_device for each CB and registers it with > the memory manager after DMA configuration succeeds. > > qda_init_device() is extended to allocate and initialize the memory > manager, while qda_deinit_device() will tear it down in later > patches. "in later patches" makes this extremely hard to review. I had to apply the series to try to navigate the code... > This prepares the QDA driver for fine-grained memory and > IOMMU domain management tied to individual CB devices. > > Signed-off-by: Ekansh Gupta <ekansh.gupta(a)oss.qualcomm.com> [..] > obj-$(CONFIG_DRM_ACCEL_QDA_COMPUTE_BUS) += qda_compute_bus.o > diff --git a/drivers/accel/qda/qda_cb.c b/drivers/accel/qda/qda_cb.c [..] > @@ -46,6 +52,18 @@ static int qda_cb_setup_device(struct qda_dev *qdev, struct device *cb_dev) > rc = dma_set_mask(cb_dev, DMA_BIT_MASK(pa_bits)); > if (rc) { > qda_err(qdev, "%d bit DMA enable failed: %d\n", pa_bits, rc); > + kfree(iommu_dev); > + return rc; > + } > + > + iommu_dev->dev = cb_dev; > + iommu_dev->sid = sid; > + snprintf(iommu_dev->name, sizeof(iommu_dev->name), "qda_iommu_dev_%u", sid); It's not easy to follow, when you have scattered the code across so many patches and so many files. But I don't think iommu_dev->name is ever used. > + > + rc = qda_memory_manager_register_device(qdev->iommu_mgr, iommu_dev); > + if (rc) { > + qda_err(qdev, "Failed to register IOMMU device: %d\n", rc); > + kfree(iommu_dev); > return rc; > } > > @@ -127,6 +145,8 @@ int qda_create_cb_device(struct qda_dev *qdev, struct device_node *cb_node) > void qda_destroy_cb_device(struct device *cb_dev) > { > struct iommu_group *group; > + struct qda_iommu_device *iommu_dev; > + struct qda_dev *qdev; > > if (!cb_dev) { > qda_dbg(NULL, "NULL CB device passed to destroy\n"); > @@ -135,6 +155,18 @@ void qda_destroy_cb_device(struct device *cb_dev) > > qda_dbg(NULL, "Destroying CB device %s\n", dev_name(cb_dev)); > > + iommu_dev = dev_get_drvdata(cb_dev); I'm not sure, but I think cb_dev is the struct device allocated in qda_create_cb_device(), but I can not find a place where you set drvdata for this device. > + if (iommu_dev) { > + if (cb_dev->parent) { > + qdev = dev_get_drvdata(cb_dev->parent); > + if (qdev && qdev->iommu_mgr) { > + qda_dbg(NULL, "Unregistering IOMMU device for %s\n", > + dev_name(cb_dev)); > + qda_memory_manager_unregister_device(qdev->iommu_mgr, iommu_dev); > + } > + } > + } > + > group = iommu_group_get(cb_dev); > if (group) { > qda_dbg(NULL, "Removing %s from IOMMU group\n", dev_name(cb_dev)); > diff --git a/drivers/accel/qda/qda_drv.c b/drivers/accel/qda/qda_drv.c [..] > @@ -25,12 +37,46 @@ static void init_device_resources(struct qda_dev *qdev) > atomic_set(&qdev->removing, 0); > } > > +static int init_memory_manager(struct qda_dev *qdev) > +{ > + int ret; > + > + qda_dbg(qdev, "Initializing IOMMU manager\n"); > + > + qdev->iommu_mgr = kzalloc_obj(*qdev->iommu_mgr, GFP_KERNEL); > + if (!qdev->iommu_mgr) > + return -ENOMEM; > + > + ret = qda_memory_manager_init(qdev->iommu_mgr); > + if (ret) { > + qda_err(qdev, "Failed to initialize memory manager: %d\n", ret); qda_memory_manager_init() already logged 1 error and 1 debug prints if you get here. > + kfree(qdev->iommu_mgr); > + qdev->iommu_mgr = NULL; We're going to fail probe, you shouldn't have to clear this. > + return ret; > + } > + > + qda_dbg(qdev, "IOMMU manager initialized successfully\n"); > + return 0; > +} > + > int qda_init_device(struct qda_dev *qdev) > { > + int ret; > + > init_device_resources(qdev); > > + ret = init_memory_manager(qdev); > + if (ret) { > + qda_err(qdev, "IOMMU manager initialization failed: %d\n", ret); And now we have 2 debug prints and two error prints in the log. > + goto err_cleanup_resources; > + } > + > qda_dbg(qdev, "QDA device initialized successfully\n"); Or, if we get here, you have 8 debug prints. Please learn how to use kprobe/kretprobe instead of reimplementing it using printk(). > return 0; > + > +err_cleanup_resources: > + cleanup_device_resources(qdev); > + return ret; > } > > static int __init qda_core_init(void) > diff --git a/drivers/accel/qda/qda_drv.h b/drivers/accel/qda/qda_drv.h > index eb732b7d8091..2cb97e4eafbf 100644 > --- a/drivers/accel/qda/qda_drv.h > +++ b/drivers/accel/qda/qda_drv.h > @@ -11,6 +11,7 @@ > #include <linux/mutex.h> > #include <linux/rpmsg.h> > #include <linux/xarray.h> > +#include "qda_memory_manager.h" > > /* Driver identification */ > #define DRIVER_NAME "qda" > @@ -23,6 +24,8 @@ struct qda_dev { > struct device *dev; > /* Mutex protecting device state */ > struct mutex lock; > + /* IOMMU/memory manager */ > + struct qda_memory_manager *iommu_mgr; > /* Flag indicating device removal in progress */ > atomic_t removing; > /* Name of the DSP (e.g., "cdsp", "adsp") */ > diff --git a/drivers/accel/qda/qda_memory_manager.c b/drivers/accel/qda/qda_memory_manager.c [..] > +int qda_memory_manager_register_device(struct qda_memory_manager *mem_mgr, > + struct qda_iommu_device *iommu_dev) > +{ > + int ret; > + u32 id; > + > + if (!mem_mgr || !iommu_dev || !iommu_dev->dev) { How could this happen? You call this function from one place, that looks like this: iommu_dev->dev = cb_dev; iommu_dev->sid = sid; rc = qda_memory_manager_register_device(qdev->iommu_mgr, iommu_dev); You just allocated in filled out iommu_dev. Looking up the callstack, we're coming from qda_rpmsg_probe() which just did qda_init_device() which created the qsdev->iommu_mgr. In other words, these can't possibly be NULL. > + qda_err(NULL, "Invalid parameters for device registration\n"); > + return -EINVAL; > + } > + > + init_iommu_device_fields(iommu_dev, mem_mgr); > + > + ret = allocate_device_id(mem_mgr, iommu_dev, &id); > + if (ret) { > + qda_err(NULL, "Failed to allocate device ID: %d (sid=%u)\n", ret, iommu_dev->sid); > + return ret; > + } > + > + iommu_dev->id = id; > + > + qda_dbg(NULL, "Registered device id=%u (sid=%u)\n", id, iommu_dev->sid); > + > + return 0; > +} > + > +void qda_memory_manager_unregister_device(struct qda_memory_manager *mem_mgr, > + struct qda_iommu_device *iommu_dev) > +{ > + if (!mem_mgr || !iommu_dev) { The one call to this function is wrapped in: if (iommu_dev) { if (qdev->iommu_mgr) { qda_dbg(NULL, ...); qda_memory_manager_unregister_device(qdev->iommu_mgr, iommu_dev); } } > + qda_err(NULL, "Attempted to unregister invalid device/manager\n"); > + return; > + } > + > + qda_dbg(NULL, "Unregistering device id=%u (refcount=%u)\n", iommu_dev->id, > + refcount_read(&iommu_dev->refcount)); And just before the call to qda_memory_manager_unregister_device() you print a debug log, saying you will call this function. > + > + if (refcount_read(&iommu_dev->refcount) == 0) { > + xa_erase(&mem_mgr->device_xa, iommu_dev->id); > + kfree(iommu_dev); > + return; > + } > + > + if (refcount_dec_and_test(&iommu_dev->refcount)) { > + qda_info(NULL, "Device id=%u refcount reached zero, queuing removal\n", > + iommu_dev->id); > + queue_work(mem_mgr->wq, &iommu_dev->remove_work); > + } > +} > + [..] > diff --git a/drivers/accel/qda/qda_memory_manager.h b/drivers/accel/qda/qda_memory_manager.h [..] > + > +/** This says "kernel-doc" > + * struct qda_iommu_device - IOMMU device instance for memory management > + * > + * This structure represents a single IOMMU-enabled device managed by the > + * memory manager. Each device can be assigned to a specific process. > + */ > +struct qda_iommu_device { > + /* Unique identifier for this IOMMU device */ But this doesn't follow kernel-doc style. At the end of the series, ./scripts/kernel-doc -none -vv -Wall drivers/accel/qda/ reports 270 warnings. > + u32 id; > + /* Pointer to the underlying device */ > + struct device *dev; > + /* Name for the device */ > + char name[32]; > + /* Spinlock protecting concurrent access to device */ > + spinlock_t lock; > + /* Reference counter for device */ > + refcount_t refcount; > + /* Work structure for deferred device removal */ > + struct work_struct remove_work; > + /* Stream ID for IOMMU transactions */ > + u32 sid; > + /* Pointer to parent memory manager */ > + struct qda_memory_manager *manager; > +}; Regards, Bjorn

1 month

Re: [PATCH RFC 03/18] accel/qda: Add RPMsg transport for Qualcomm DSP accelerator

by Bjorn Andersson

On Tue, Feb 24, 2026 at 12:12:32AM +0200, Dmitry Baryshkov wrote: > On Mon, Feb 23, 2026 at 03:50:32PM -0600, Bjorn Andersson wrote: > > On Mon, Feb 23, 2026 at 11:23:13PM +0200, Dmitry Baryshkov wrote: > > > On Tue, Feb 24, 2026 at 12:38:57AM +0530, Ekansh Gupta wrote: > > [..] > > > > diff --git a/drivers/accel/qda/qda_drv.h b/drivers/accel/qda/qda_drv.h > > [..] > > > > +/* Error logging - always logs and tracks errors */ > > > > +#define qda_err(qdev, fmt, ...) do { \ > > > > + struct device *__dev = qda_get_log_device(qdev); \ > > > > + if (__dev) \ > > > > + dev_err(__dev, "[%s] " fmt, __func__, ##__VA_ARGS__); \ > > > > + else \ > > > > + pr_err(DRIVER_NAME ": [%s] " fmt, __func__, ##__VA_ARGS__); \ > > > > > > What /why? You are under drm, so you can use drm_* helpers instead. > > > > > > > In particular, rather than rolling our own wrappers around standard > > functions, just use dev_err() whenever you have a struct device. And for > > something like fastrpc - life starts at some probe() and ends at some > > remove() so that should be always. > > I'd say differently. For the DRM devices the life cycle is centered > around the DRM device (which can outlive platform device for multiple > reasons). So, please start by registering the DRM accel device and using > it for all the logging (and btw for private data management too). > There are no platform_devices here, but tomato tomato... What defines the life cycle of the DRM device then? Might it linger because clients are holding open handles to it? Note that the fastrpc service is coming and going, as the remoteproc starts and stops. Regards, Bjorn > > > > Regards, > > Bjorn > > -- > With best wishes > Dmitry

1 month

Re: [PATCH RFC 00/18] accel/qda: Introduce Qualcomm DSP Accelerator driver

by Bjorn Andersson

On Tue, Feb 24, 2026 at 12:38:54AM +0530, Ekansh Gupta wrote: > This patch series introduces the Qualcomm DSP Accelerator (QDA) driver, > a modern DRM-based accelerator implementation for Qualcomm Hexagon DSPs. > The driver provides a standardized interface for offloading computational > tasks to DSPs found on Qualcomm SoCs, supporting all DSP domains (ADSP, > CDSP, SDSP, GDSP). > > The QDA driver is designed as an alternative for the FastRPC driver > in drivers/misc/, offering improved resource management, better integration > with standard kernel subsystems, and alignment with the Linux kernel's > Compute Accelerators framework. > If I understand correctly, this is just the same FastRPC protocol but in the accel framework, and hence with a new userspace ABI? I don't fancy the name "QDA" as an acronym for "FastRPC Accel". I would much prefer to see this living in drivers/accel/fastrpc and be named some variation of "fastrpc" (e.g. fastrpc_accel). (Driver name can be "fastrpc" as the other one apparently is named "qcom,fastrpc"). > User-space staging branch > ============ > https://github.com/qualcomm/fastrpc/tree/accel/staging > > Key Features > ============ > > * Standard DRM accelerator interface via /dev/accel/accelN > * GEM-based buffer management with DMA-BUF import/export support > * IOMMU-based memory isolation using per-process context banks > * FastRPC protocol implementation for DSP communication > * RPMsg transport layer for reliable message passing > * Support for all DSP domains (ADSP, CDSP, SDSP, GDSP) > * Comprehensive IOCTL interface for DSP operations > > High-Level Architecture Differences with Existing FastRPC Driver > ================================================================= > > The QDA driver represents a significant architectural departure from the > existing FastRPC driver (drivers/misc/fastrpc.c), addressing several key > limitations while maintaining protocol compatibility: > > 1. DRM Accelerator Framework Integration > - FastRPC: Custom character device (/dev/fastrpc-*) > - QDA: Standard DRM accel device (/dev/accel/accelN) > - Benefit: Leverages established DRM infrastructure for device > management. > > 2. Memory Management > - FastRPC: Custom memory allocator with ION/DMA-BUF integration > - QDA: Native GEM objects with full PRIME support > - Benefit: Seamless buffer sharing using standard DRM mechanisms > > 3. IOMMU Context Bank Management > - FastRPC: Direct IOMMU domain manipulation, limited isolation > - QDA: Custom compute bus (qda_cb_bus_type) with proper device model > - Benefit: Each CB device is a proper struct device with IOMMU group > support, enabling better isolation and resource tracking. > - https://lore.kernel.org/all/245d602f-3037-4ae3-9af9-d98f37258aae@oss.qualco… > > 4. Memory Manager Architecture > - FastRPC: Monolithic allocator > - QDA: Pluggable memory manager with backend abstraction > - Benefit: Currently uses DMA-coherent backend, easily extensible for > future memory types (e.g., carveout, CMA) > > 5. Transport Layer > - FastRPC: Direct RPMsg integration in core driver > - QDA: Abstracted transport layer (qda_rpmsg.c) > - Benefit: Clean separation of concerns, easier to add alternative > transports if needed > > 8. Code Organization > - FastRPC: ~3000 lines in single file > - QDA: Modular design across multiple files (~4600 lines total) "Now 50% more LOC and you need 6 tabs open in your IDE!" Might be better, but in itself it provides no immediate value. > * qda_drv.c: Core driver and DRM integration > * qda_gem.c: GEM object management > * qda_memory_manager.c: Memory and IOMMU management > * qda_fastrpc.c: FastRPC protocol implementation > * qda_rpmsg.c: Transport layer > * qda_cb.c: Context bank device management > - Benefit: Better maintainability, clearer separation of concerns > > 9. UAPI Design > - FastRPC: Custom IOCTL interface > - QDA: DRM-style IOCTLs with proper versioning support > - Benefit: Follows DRM conventions, easier userspace integration > > 10. Documentation > - FastRPC: Minimal in-tree documentation > - QDA: Comprehensive documentation in Documentation/accel/qda/ > - Benefit: Better developer experience, clearer API contracts > > 11. Buffer Reference Mechanism > - FastRPC: Uses buffer file descriptors (FDs) for all book-keeping > in both kernel and DSP > - QDA: Uses GEM handles for kernel-side management, providing better > integration with DRM subsystem > - Benefit: Leverages DRM GEM infrastructure for reference counting, > lifetime management, and integration with other DRM components > This is all good, but what is the plan regarding /dev/fastrpc-*? The idea here clearly is to provide an alternative implementation, and they seem to bind to the same toplevel compatible - so you can only compile one into your kernel at any point in time. So if I understand correctly, at some point in time we need to say CONFIG_DRM_ACCEL_QDA=m and CONFIG_QCOM_FASTRPC=n, which will break all existing user space applications? That's not acceptable. Would it be possible to have a final driver that is implemented as a accel, but provides wrappers for the legacy misc and ioctl interface to the applications? Regards, Bjorn > Key Technical Improvements > =========================== > > * Proper device model: CB devices are real struct device instances on a > custom bus, enabling proper IOMMU group management and power management > integration > > * Reference-counted IOMMU devices: Multiple file descriptors from the same > process share a single IOMMU device, reducing overhead > > * GEM-based buffer lifecycle: Automatic cleanup via DRM GEM reference > counting, eliminating many resource leak scenarios > > * Modular memory backends: The memory manager supports pluggable backends, > currently implementing DMA-coherent allocations with SID-prefixed > addresses for DSP firmware > > * Context-based invocation tracking: XArray-based context management with > proper synchronization and cleanup > > Patch Series Organization > ========================== > > Patches 1-2: Driver skeleton and documentation > Patches 3-6: RPMsg transport and IOMMU/CB infrastructure > Patches 7-9: DRM device registration and basic IOCTL > Patches 10-12: GEM buffer management and PRIME support > Patches 13-17: FastRPC protocol implementation (attach, invoke, create, > map/unmap) > Patch 18: MAINTAINERS entry > > Open Items > =========== > > The following items are identified as open items: > > 1. Privilege Level Management > - Currently, daemon processes and user processes have the same access > level as both use the same accel device node. This needs to be > addressed as daemons attach to privileged DSP PDs and require > higher privilege levels for system-level operations > - Seeking guidance on the best approach: separate device nodes, > capability-based checks, or DRM master/authentication mechanisms > > 2. UAPI Compatibility Layer > - Add UAPI compat layer to facilitate migration of client applications > from existing FastRPC UAPI to the new QDA accel driver UAPI, > ensuring smooth transition for existing userspace code > - Seeking guidance on implementation approach: in-kernel translation > layer, userspace wrapper library, or hybrid solution > > 3. Documentation Improvements > - Add detailed IOCTL usage examples > - Document DSP firmware interface requirements > - Create migration guide from existing FastRPC > > 4. Per-Domain Memory Allocation > - Develop new userspace API to support memory allocation on a per > domain basis, enabling domain-specific memory management and > optimization > > 5. Audio and Sensors PD Support > - The current patch series does not handle Audio PD and Sensors PD > functionalities. These specialized protection domains require > additional support for real-time constraints and power management > > Interface Compatibility > ======================== > > The QDA driver maintains compatibility with existing FastRPC infrastructure: > > * Device Tree Bindings: The driver uses the same device tree bindings as > the existing FastRPC driver, ensuring no changes are required to device > tree sources. The "qcom,fastrpc" compatible string and child node > structure remain unchanged. > > * Userspace Interface: While the driver provides a new DRM-based UAPI, > the underlying FastRPC protocol and DSP firmware interface remain > compatible. This ensures that DSP firmware and libraries continue to > work without modification. > > * Migration Path: The modular design allows for gradual migration, where > both drivers can coexist during the transition period. Applications can > be migrated incrementally to the new UAPI with the help of the planned > compatibility layer. > > References > ========== > > Previous discussions on this migration: > - https://lkml.org/lkml/2024/6/24/479 > - https://lkml.org/lkml/2024/6/21/1252 > > Testing > ======= > > The driver has been tested on Qualcomm platforms with: > - Basic FastRPC attach/release operations > - DSP process creation and initialization > - Memory mapping/unmapping operations > - Dynamic invocation with various buffer types > - GEM buffer allocation and mmap > - PRIME buffer import from other subsystems > > Signed-off-by: Ekansh Gupta <ekansh.gupta(a)oss.qualcomm.com> > --- > Ekansh Gupta (18): > accel/qda: Add Qualcomm QDA DSP accelerator driver docs > accel/qda: Add Qualcomm DSP accelerator driver skeleton > accel/qda: Add RPMsg transport for Qualcomm DSP accelerator > accel/qda: Add built-in compute CB bus for QDA and integrate with IOMMU > accel/qda: Create compute CB devices on QDA compute bus > accel/qda: Add memory manager for CB devices > accel/qda: Add DRM accel device registration for QDA driver > accel/qda: Add per-file DRM context and open/close handling > accel/qda: Add QUERY IOCTL and basic QDA UAPI header > accel/qda: Add DMA-backed GEM objects and memory manager integration > accel/qda: Add GEM_CREATE and GEM_MMAP_OFFSET IOCTLs > accel/qda: Add PRIME dma-buf import support > accel/qda: Add initial FastRPC attach and release support > accel/qda: Add FastRPC dynamic invocation support > accel/qda: Add FastRPC DSP process creation support > accel/qda: Add FastRPC-based DSP memory mapping support > accel/qda: Add FastRPC-based DSP memory unmapping support > MAINTAINERS: Add MAINTAINERS entry for QDA driver > > Documentation/accel/index.rst | 1 + > Documentation/accel/qda/index.rst | 14 + > Documentation/accel/qda/qda.rst | 129 ++++ > MAINTAINERS | 9 + > arch/arm64/configs/defconfig | 2 + > drivers/accel/Kconfig | 1 + > drivers/accel/Makefile | 2 + > drivers/accel/qda/Kconfig | 35 ++ > drivers/accel/qda/Makefile | 19 + > drivers/accel/qda/qda_cb.c | 182 ++++++ > drivers/accel/qda/qda_cb.h | 26 + > drivers/accel/qda/qda_compute_bus.c | 23 + > drivers/accel/qda/qda_drv.c | 375 ++++++++++++ > drivers/accel/qda/qda_drv.h | 171 ++++++ > drivers/accel/qda/qda_fastrpc.c | 1002 ++++++++++++++++++++++++++++++++ > drivers/accel/qda/qda_fastrpc.h | 433 ++++++++++++++ > drivers/accel/qda/qda_gem.c | 211 +++++++ > drivers/accel/qda/qda_gem.h | 103 ++++ > drivers/accel/qda/qda_ioctl.c | 271 +++++++++ > drivers/accel/qda/qda_ioctl.h | 118 ++++ > drivers/accel/qda/qda_memory_dma.c | 91 +++ > drivers/accel/qda/qda_memory_dma.h | 46 ++ > drivers/accel/qda/qda_memory_manager.c | 382 ++++++++++++ > drivers/accel/qda/qda_memory_manager.h | 148 +++++ > drivers/accel/qda/qda_prime.c | 194 +++++++ > drivers/accel/qda/qda_prime.h | 43 ++ > drivers/accel/qda/qda_rpmsg.c | 327 +++++++++++ > drivers/accel/qda/qda_rpmsg.h | 57 ++ > drivers/iommu/iommu.c | 4 + > include/linux/qda_compute_bus.h | 22 + > include/uapi/drm/qda_accel.h | 224 +++++++ > 31 files changed, 4665 insertions(+) > --- > base-commit: d4906ae14a5f136ceb671bb14cedbf13fa560da6 > change-id: 20260223-qda-firstpost-4ab05249e2cc > > Best regards, > -- > Ekansh Gupta <ekansh.gupta(a)oss.qualcomm.com> > >

1 month

Re: [PATCH RFC 02/18] accel/qda: Add Qualcomm DSP accelerator driver skeleton

by Bjorn Andersson

On Tue, Feb 24, 2026 at 12:38:56AM +0530, Ekansh Gupta wrote: [..] > diff --git a/drivers/accel/qda/qda_drv.c b/drivers/accel/qda/qda_drv.c > new file mode 100644 > index 000000000000..18b0d3fb1598 > --- /dev/null > +++ b/drivers/accel/qda/qda_drv.c > @@ -0,0 +1,22 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +// Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > +#include <linux/module.h> > +#include <linux/kernel.h> > + > +static int __init qda_core_init(void) > +{ > + pr_info("QDA: driver initialization complete\n"); This print is useless as soon as you make the driver do anything, please don't include developmental debug logs. In fact, this patch doesn't actually do anything, please squash things a bit to give it some meat. Regards, Bjorn > + return 0; > +} > + > +static void __exit qda_core_exit(void) > +{ > + pr_info("QDA: driver exit complete\n"); > +} > + > +module_init(qda_core_init); > +module_exit(qda_core_exit); > + > +MODULE_AUTHOR("Qualcomm AI Infra Team"); > +MODULE_DESCRIPTION("Qualcomm DSP Accelerator Driver"); > +MODULE_LICENSE("GPL"); > > -- > 2.34.1 > >

1 month

Re: [PATCH RFC 03/18] accel/qda: Add RPMsg transport for Qualcomm DSP accelerator

by Bjorn Andersson

On Mon, Feb 23, 2026 at 11:23:13PM +0200, Dmitry Baryshkov wrote: > On Tue, Feb 24, 2026 at 12:38:57AM +0530, Ekansh Gupta wrote: [..] > > diff --git a/drivers/accel/qda/qda_drv.h b/drivers/accel/qda/qda_drv.h [..] > > +/* Error logging - always logs and tracks errors */ > > +#define qda_err(qdev, fmt, ...) do { \ > > + struct device *__dev = qda_get_log_device(qdev); \ > > + if (__dev) \ > > + dev_err(__dev, "[%s] " fmt, __func__, ##__VA_ARGS__); \ > > + else \ > > + pr_err(DRIVER_NAME ": [%s] " fmt, __func__, ##__VA_ARGS__); \ > > What /why? You are under drm, so you can use drm_* helpers instead. > In particular, rather than rolling our own wrappers around standard functions, just use dev_err() whenever you have a struct device. And for something like fastrpc - life starts at some probe() and ends at some remove() so that should be always. Regards, Bjorn

1 month

How can I recover my Cryptocurrency sent to a wrong wallet address? -Visit Autopsy Mainnet Recovery

by masoncaleb2a＠gmail.com

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1 month

Legitimate Cryptocurrency Recovery Company Expert Service | Hire a Hacker to Recover Lost Crypto | Company to Recover Crypto After Scam

by Jane Pamela

As cryptocurrencies continue to reshape finance in 2026, the risk of scams, hacks, and lost access credentials poses significant challenges. Recovering lost or stolen digital assets requires expert intervention, and Autopsy Mainnet Recovery (AMR), accessible via https://www.autopsymainnetsolutions.com / info(a)autopsymainnetsolutions.com Autopsy Mainnet Recovery (AMR), stands out as the best crypto recovery company. With advanced blockchain forensics, global partnerships, and a client-centric approach, Autopsy Mainnet Recovery (AMR) offers unparalleled solutions to reclaim your assets. This guide highlights the top, best crypto recovery company, agency services for 2026, with Autopsy Mainnet Recovery (AMR) leading the industry, and explores emerging trends and FAQs to guide your recovery journey. Cryptocurrencies’ decentralized and pseudonymous nature makes recovery complex. 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Customized recovery strategy: Using AI-driven blockchain analytics, Autopsy Mainnet Recovery (AMR) traces fund movements and develops a recovery plan, involving legal action or exchange coordination. Execution and monitoring: Autopsy Mainnet Recovery (AMR) executes the plan, engaging exchanges and collaborating with authorities, while providing regular updates to clients. Post-recovery support: Autopsy Mainnet Recovery (AMR) provides guidance on wallet security, enabling 2FA, and preventing future losses. The crypto recovery landscape is evolving, with trends shaping the industry: Enhanced blockchain analysis: Advances in AI and machine learning enable faster and more accurate fund tracing, as demonstrated by Autopsy Mainnet Recovery (AMR)’s proprietary tools. Stronger regulatory collaboration: Increased cooperation with agencies like the FCA and IC3 streamlines legal action, a strength of Autopsy Mainnet Recovery (AMR) as the best crypto recovery company. Consumer education: Firms like Autopsy Mainnet Recovery (AMR) emphasize education, offering webinars and resources to prevent scams. Prevention is key to safeguarding assets. Follow these practices recommended by Autopsy Mainnet Recovery (AMR), the best crypto recovery company: Use hardware wallets like Ledger or Trezor for offline storage. Enable multi-factor authentication (MFA) on all accounts. Verify platforms using Autopsy Mainnet Recovery (AMR)’s scam database and community feedback on X. Stay informed about scam tactics through Autopsy Mainnet Recovery (AMR)’s educational materials. Q1: Does working with a recovery service guarantee the return of assets? A1: No, recovery is not guaranteed due to blockchain complexity. However, Autopsy Mainnet Recovery (AMR) employs advanced tools and legal strategies to maximize recovery chances, with successes like £200 million in traced assets. Q2: What types of situations do recovery services help with? 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Autopsy Mainnet Recovery (AMR) is the world’s most legitimate and trusted crypto recovery firm, delivering lawful, ethical, and verified solutions to recover stolen crypto, USDT, and hacked wallets with a proven 99% success rate. https://www.autopsymainnetsolutions.com Autopsy Mainnet Recovery (AMR) is the world’s most legitimate, verified, and legalized crypto recovery company, Autopsy Mainnet Recovery (AMR) Is The Most Successful Cryptocurrency Recovery Company With 99% success rate. Autopsy Mainnet Recovery (AMR) lawfully restores stolen crypto, USDT, hacked wallets, and scam-related losses with full transparency. Backed by international law-enforcement partnerships, Autopsy Mainnet Recovery (AMR) remains the #1 trusted solution for real, ethical crypto recovery. Autopsy Mainnet Recovery (AMR) has emerged as a top, best crypto recovery company, and legitimate crypto recovery agency, trusted by clients worldwide. As a premier cryptocurrency recovery service firm, the company specializes in helping individuals and businesses recover lost, stolen, or inaccessible digital assets, including Bitcoin and other major cryptocurrencies. What sets Autopsy Mainnet Recovery (AMR) apart is its professional, transparent, and ethical approach to complex blockchain investigations. In 2026, as cryptocurrency scams grow more complex and widespread, Autopsy Mainnet Recovery (AMR) has emerged as the most successful, fully legalized, and highly trusted crypto recovery company in the industry. Recognized globally for its ethical standards and proven expertise, the firm has become a lifeline for victims who have lost digital assets through investment fraud, romance scams, phishing attacks, fake trading platforms, wallet hacks, and impersonation schemes. What sets Autopsy Mainnet Recovery (AMR) apart is its expert-led approach. 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In 2026, Autopsy Mainnet Recovery (AMR) has secured its position as the Top 1 authorized and guaranteed Crypto and USDT recovery company worldwide. Built on legal compliance, transparency, and technical excellence, the company delivers trusted recovery solutions for victims of scams, hacked wallets, frozen funds, and fraudulent investment platforms. Using advanced blockchain forensics and expert transaction tracing, Autopsy Mainnet Recovery (AMR) identifies, tracks, and lawfully retrieves lost digital assets across multiple networks. Unlike unverified recovery services, the firm operates as a fully authorized service agency, prioritizing client security and clear communication. Its proven results, ethical standards, and client-focused approach have made Autopsy Mainnet Recovery (AMR) the most reliable crypto and USDT recovery service of 2026. Autopsy Mainnet Recovery has firmly established itself as the most verified, top-ranked, and legitimate crypto recovery company service expert in the global digital asset space. Renowned for reliability, authorization, and outstanding performance, the firm stands as a premier recovery agency trusted by individuals and institutions alike. Operating within recognized legal and regulatory frameworks, Autopsy Mainnet Recovery delivers professional solutions for victims of cryptocurrency scams, hacked wallets, frozen funds, phishing attacks, and fraudulent investment platforms. Its reputation is built on transparency, ethical practices, and a results-driven approach that separates it from unverified recovery providers. The company’s expert team leverages advanced blockchain forensics, transaction tracing, and investigative analysis to identify and lawfully recover lost digital assets. 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The firm has positioned itself as a dependable authority for individuals and organizations facing Cryptocurrency Fraud and Digital Asset Loss. Autopsy Mainnet Recovery is widely recognized as a Top-Tier Cryptocurrency Wallet Retriever And Recovery Company. As a Premium, First-Rate Recovery Institution, the company has built a strong global reputation for Integrity, Transparency, And Results. Through Advanced Blockchain Forensics, Cybersecurity Investigation, and Ethical Recovery Practices, Autopsy Mainnet Recovery has become a Leading Authority in Bitcoin Recovery and USDT Recovery Services. Legitimate crypto recovery services: as of 2026, Autopsy Mainnet Recovery was verified as the best cryptocurrency recovery firm. Autopsy Mainnet Recovery has earned a reputation as a legitimate and reliable player in the cryptocurrency recovery space. Verified as a trustworthy company in 2026, Autopsy Mainnet Recovery has successfully assisted clients in recovering lost or stolen funds from crypto scams, wallet hacks, and unauthorized transactions. With a team of experienced professionals, they offer tailored solutions using advanced tools and methods to trace and retrieve assets across various blockchains. Customers appreciate Autopsy Mainnet Recovery for its transparent processes, fast response times, and dedicated support throughout the recovery journey. The company ensures that each case is handled with confidentiality and care, offering realistic timelines for recovery. Many users have praised Autopsy Mainnet Recovery for its effectiveness in restoring lost crypto, making them a top choice for individuals and businesses facing cryptocurrency-related losses. Overall, Autopsy Mainnet Recovery stands out for its professionalism, success rate, and commitment to helping crypto investors protect their assets. Email: info(a)autopsymainnetsolutions.com Website: https://autospyrec.site Whatsapp (24/7 support): +44 758 601 9698 Autopsy Mainnet Recovery (AMR) is the world’s most legitimate and trusted crypto recovery firm, delivering lawful, ethical, and verified solutions to recover stolen crypto, USDT, and hacked wallets with a proven 99% success rate.

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