Linaro-mm-sig

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2910 discussions

[PATCH 1/3] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

tldr; DMA buffers aren't normal memory, expecting that you can use them like that (like calling get_user_pages works, or that they're accounting like any other normal memory) cannot be guaranteed. Since some userspace only runs on integrated devices, where all buffers are actually all resident system memory, there's a huge temptation to assume that a struct page is always present and useable like for any more pagecache backed mmap. This has the potential to result in a uapi nightmare. To stop this gap require that DMA buffer mmaps are VM_PFNMAP, which blocks get_user_pages and all the other struct page based infrastructure for everyone. In spirit this is the uapi counterpart to the kernel-internal CONFIG_DMABUF_DEBUG. Motivated by a recent patch which wanted to swich the system dma-buf heap to vm_insert_page instead of vm_insert_pfn. v2: Jason brought up that we also want to guarantee that all ptes have the pte_special flag set, to catch fast get_user_pages (on architectures that support this). Allowing VM_MIXEDMAP (like VM_SPECIAL does) would still allow vm_insert_page, but limiting to VM_PFNMAP will catch that. >From auditing the various functions to insert pfn pte entires (vm_insert_pfn_prot, remap_pfn_range and all it's callers like dma_mmap_wc) it looks like VM_PFNMAP is already required anyway, so this should be the correct flag to check for. References: https://lore.kernel.org/lkml/CAKMK7uHi+mG0z0HUmNt13QCCvutuRVjpcR0NjRL12k-Wb… Acked-by: Christian König <christian.koenig(a)amd.com> Cc: Jason Gunthorpe <jgg(a)ziepe.ca> Cc: Suren Baghdasaryan <surenb(a)google.com> Cc: Matthew Wilcox <willy(a)infradead.org> Cc: John Stultz <john.stultz(a)linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org -- Resending this so I can test the next two patches for vgem/shmem in intel-gfx-ci. Last round failed somehow, but I can't repro that at all locally here. No immediate plans to merge this patch here since ttm isn't addressed yet (and there we have the hugepte issue, for which I don't think we have a clear consensus yet). -Daniel --- drivers/dma-buf/dma-buf.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index eadd1eaa2fb5..dda583fb1f03 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -127,6 +127,7 @@ static struct file_system_type dma_buf_fs_type = { static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma) { struct dma_buf *dmabuf; + int ret; if (!is_dma_buf_file(file)) return -EINVAL; @@ -142,7 +143,11 @@ static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma) dmabuf->size >> PAGE_SHIFT) return -EINVAL; - return dmabuf->ops->mmap(dmabuf, vma); + ret = dmabuf->ops->mmap(dmabuf, vma); + + WARN_ON(!(vma->vm_flags & VM_PFNMAP)); + + return ret; } static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence) @@ -1244,6 +1249,8 @@ EXPORT_SYMBOL_GPL(dma_buf_end_cpu_access); int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma, unsigned long pgoff) { + int ret; + if (WARN_ON(!dmabuf || !vma)) return -EINVAL; @@ -1264,7 +1271,11 @@ int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma, vma_set_file(vma, dmabuf->file); vma->vm_pgoff = pgoff; - return dmabuf->ops->mmap(dmabuf, vma); + ret = dmabuf->ops->mmap(dmabuf, vma); + + WARN_ON(!(vma->vm_flags & VM_PFNMAP)); + + return ret; } EXPORT_SYMBOL_GPL(dma_buf_mmap); -- 2.31.0

4 years, 1 month

[PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

by Daniel Vetter

Docs for struct dma_resv are fairly clear: "A reservation object can have attached one exclusive fence (normally associated with write operations) or N shared fences (read operations)." https://dri.freedesktop.org/docs/drm/driver-api/dma-buf.html#reservation-ob… Furthermore a review across all of upstream. First of render drivers and how they set implicit fences: - nouveau follows this contract, see in validate_fini_no_ticket() nouveau_bo_fence(nvbo, fence, !!b->write_domains); and that last boolean controls whether the exclusive or shared fence slot is used. - radeon follows this contract by setting p->relocs[i].tv.num_shared = !r->write_domain; in radeon_cs_parser_relocs(), which ensures that the call to ttm_eu_fence_buffer_objects() in radeon_cs_parser_fini() will do the right thing. - vmwgfx seems to follow this contract with the shotgun approach of always setting ttm_val_buf->num_shared = 0, which means ttm_eu_fence_buffer_objects() will only use the exclusive slot. - etnaviv follows this contract, as can be trivially seen by looking at submit_attach_object_fences() - i915 is a bit a convoluted maze with multiple paths leading to i915_vma_move_to_active(). Which sets the exclusive flag if EXEC_OBJECT_WRITE is set. This can either come as a buffer flag for softpin mode, or through the write_domain when using relocations. It follows this contract. - lima follows this contract, see lima_gem_submit() which sets the exclusive fence when the LIMA_SUBMIT_BO_WRITE flag is set for that bo - msm follows this contract, see msm_gpu_submit() which sets the exclusive flag when the MSM_SUBMIT_BO_WRITE is set for that buffer - panfrost follows this contract with the shotgun approach of just always setting the exclusive fence, see panfrost_attach_object_fences(). Benefits of a single engine I guess - v3d follows this contract with the same shotgun approach in v3d_attach_fences_and_unlock_reservation(), but it has at least an XXX comment that maybe this should be improved - v4c uses the same shotgun approach of always setting an exclusive fence, see vc4_update_bo_seqnos() - vgem also follows this contract, see vgem_fence_attach_ioctl() and the VGEM_FENCE_WRITE. This is used in some igts to validate prime sharing with i915.ko without the need of a 2nd gpu - vritio follows this contract again with the shotgun approach of always setting an exclusive fence, see virtio_gpu_array_add_fence() This covers the setting of the exclusive fences when writing. Synchronizing against the exclusive fence is a lot more tricky, and I only spot checked a few: - i915 does it, with the optional EXEC_OBJECT_ASYNC to skip all implicit dependencies (which is used by vulkan) - etnaviv does this. Implicit dependencies are collected in submit_fence_sync(), again with an opt-out flag ETNA_SUBMIT_NO_IMPLICIT. These are then picked up in etnaviv_sched_dependency which is the drm_sched_backend_ops->dependency callback. - v4c seems to not do much here, maybe gets away with it by not having a scheduler and only a single engine. Since all newer broadcom chips than the OG vc4 use v3d for rendering, which follows this contract, the impact of this issue is fairly small. - v3d does this using the drm_gem_fence_array_add_implicit() helper, which then it's drm_sched_backend_ops->dependency callback v3d_job_dependency() picks up. - panfrost is nice here and tracks the implicit fences in panfrost_job->implicit_fences, which again the drm_sched_backend_ops->dependency callback panfrost_job_dependency() picks up. It is mildly questionable though since it only picks up exclusive fences in panfrost_acquire_object_fences(), but not buggy in practice because it also always sets the exclusive fence. It should pick up both sets of fences, just in case there's ever going to be a 2nd gpu in a SoC with a mali gpu. Or maybe a mali SoC with a pcie port and a real gpu, which might actually happen eventually. A bug, but easy to fix. Should probably use the drm_gem_fence_array_add_implicit() helper. - lima is nice an easy, uses drm_gem_fence_array_add_implicit() and the same schema as v3d. - msm is mildly entertaining. It also supports MSM_SUBMIT_NO_IMPLICIT, but because it doesn't use the drm/scheduler it handles fences from the wrong context with a synchronous dma_fence_wait. See submit_fence_sync() leading to msm_gem_sync_object(). Investing into a scheduler might be a good idea. - all the remaining drivers are ttm based, where I hope they do appropriately obey implicit fences already. I didn't do the full audit there because a) not follow the contract would confuse ttm quite well and b) reading non-standard scheduler and submit code which isn't based on drm/scheduler is a pain. Onwards to the display side. - Any driver using the drm_gem_plane_helper_prepare_fb() helper will correctly. Overwhelmingly most drivers get this right, except a few totally dont. I'll follow up with a patch to make this the default and avoid a bunch of bugs. - I didn't audit the ttm drivers, but given that dma_resv started there I hope they get this right. In conclusion this IS the contract, both as documented and overwhelmingly implemented, specically as implemented by all render drivers except amdgpu. Amdgpu tried to fix this already in commit 049aca4363d8af87cab8d53de5401602db3b9999 Author: Christian König <christian.koenig(a)amd.com> Date: Wed Sep 19 16:54:35 2018 +0200 drm/amdgpu: fix using shared fence for exported BOs v2 but this fix falls short on a number of areas: - It's racy, by the time the buffer is shared it might be too late. To make sure there's definitely never a problem we need to set the fences correctly for any buffer that's potentially exportable. - It's breaking uapi, dma-buf fds support poll() and differentitiate between, which was introduced in commit 9b495a5887994a6d74d5c261d012083a92b94738 Author: Maarten Lankhorst <maarten.lankhorst(a)canonical.com> Date: Tue Jul 1 12:57:43 2014 +0200 dma-buf: add poll support, v3 - Christian König wants to nack new uapi building further on this dma_resv contract because it breaks amdgpu, quoting "Yeah, and that is exactly the reason why I will NAK this uAPI change. "This doesn't works for amdgpu at all for the reasons outlined above." https://lore.kernel.org/dri-devel/f2eb6751-2f82-9b23-f57e-548de5b729de@gmai… Rejecting new development because your own driver is broken and violates established cross driver contracts and uapi is really not how upstream works. Now this patch will have a severe performance impact on anything that runs on multiple engines. So we can't just merge it outright, but need a bit a plan: - amdgpu needs a proper uapi for handling implicit fencing. The funny thing is that to do it correctly, implicit fencing must be treated as a very strange IPC mechanism for transporting fences, where both setting the fence and dependency intercepts must be handled explicitly. Current best practices is a per-bo flag to indicate writes, and a per-bo flag to to skip implicit fencing in the CS ioctl as a new chunk. - Since amdgpu has been shipping with broken behaviour we need an opt-out flag from the butchered implicit fencing model to enable the proper explicit implicit fencing model. - for kernel memory fences due to bo moves at least the i915 idea is to use ttm_bo->moving. amdgpu probably needs the same. - since the current p2p dma-buf interface assumes the kernel memory fence is in the exclusive dma_resv fence slot we need to add a new fence slot for kernel fences, which must never be ignored. Since currently only amdgpu supports this there's no real problem here yet, until amdgpu gains a NO_IMPLICIT CS flag. - New userspace needs to ship in enough desktop distros so that users wont notice the perf impact. I think we can ignore LTS distros who upgrade their kernels but not their mesa3d snapshot. - Then when this is all in place we can merge this patch here. What is not a solution to this problem here is trying to make the dma_resv rules in the kernel more clever. The fundamental issue here is that the amdgpu CS uapi is the least expressive one across all drivers (only equalled by panfrost, which has an actual excuse) by not allowing any userspace control over how implicit sync is conducted. Until this is fixed it's completely pointless to make the kernel more clever to improve amdgpu, because all we're doing is papering over this uapi design issue. amdgpu needs to attain the status quo established by other drivers first, once that's achieved we can tackle the remaining issues in a consistent way across drivers. Cc: mesa-dev(a)lists.freedesktop.org Cc: Bas Nieuwenhuizen <bas(a)basnieuwenhuizen.nl> Cc: Dave Airlie <airlied(a)gmail.com> Cc: Rob Clark <robdclark(a)chromium.org> Cc: Kristian H. Kristensen <hoegsberg(a)google.com> Cc: Michel Dänzer <michel(a)daenzer.net> Cc: Daniel Stone <daniels(a)collabora.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: Daniel Vetter <daniel.vetter(a)ffwll.ch> Cc: Deepak R Varma <mh12gx2825(a)gmail.com> Cc: Chen Li <chenli(a)uniontech.com> Cc: Kevin Wang <kevin1.wang(a)amd.com> Cc: Dennis Li <Dennis.Li(a)amd.com> Cc: Luben Tuikov <luben.tuikov(a)amd.com> Cc: linaro-mm-sig(a)lists.linaro.org Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 88a24a0b5691..cc8426e1e8a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -617,8 +617,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, amdgpu_bo_list_for_each_entry(e, p->bo_list) { struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); - /* Make sure we use the exclusive slot for shared BOs */ - if (bo->prime_shared_count) + /* Make sure we use the exclusive slot for all potentially shared BOs */ + if (!(bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)) e->tv.num_shared = 0; e->bo_va = amdgpu_vm_bo_find(vm, bo); } -- 2.31.0

4 years, 1 month

[PATCH] drm/amdgpu: remove unreachable code

by Jiapeng Chong

In the function amdgpu_uvd_cs_msg(), every branch in the switch statement will have a return, so the code below the switch statement will not be executed. Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:845 amdgpu_uvd_cs_msg() warn: ignoring unreachable code. Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> --- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 82f0542..375b346 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -842,8 +842,6 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); return -EINVAL; } - BUG(); - return -EINVAL; } /** -- 1.8.3.1

4 years, 1 month

[PATCH v2] amdgpu: remove unreachable code

by Jiapeng Chong

In the function amdgpu_uvd_cs_msg(), every branch in the switch statement will have a return, so the code below the switch statement will not be executed. Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:845 amdgpu_uvd_cs_msg() warn: ignoring unreachable code. Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> --- Changes in v2: -For the follow advice: https://lore.kernel.org/patchwork/patch/1435074/ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 82f0542..b32ed85 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -840,7 +840,6 @@ static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, default: DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); - return -EINVAL; } BUG(); return -EINVAL; -- 1.8.3.1

4 years, 1 month

[PATCH -next] media: staging: tegra-vde: Fix error return code in tegra_vde_probe()

by Wei Yongjun

Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: dc8276b78917 ("staging: media: tegra-vde: use pm_runtime_resume_and_get()") Reported-by: Hulk Robot <hulkci(a)huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1(a)huawei.com> --- drivers/staging/media/tegra-vde/vde.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/staging/media/tegra-vde/vde.c b/drivers/staging/media/tegra-vde/vde.c index e025b69776f2..321d14ba2e56 100644 --- a/drivers/staging/media/tegra-vde/vde.c +++ b/drivers/staging/media/tegra-vde/vde.c @@ -1071,7 +1071,8 @@ static int tegra_vde_probe(struct platform_device *pdev) * power-cycle it in order to put hardware into a predictable lower * power state. */ - if (pm_runtime_resume_and_get(dev) < 0) + err = pm_runtime_resume_and_get(dev); + if (err < 0) goto err_pm_runtime; pm_runtime_put(dev);

4 years, 1 month

[PATCH] drm/amdgpu: Fix inconsistent indenting

by Jiapeng Chong

Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c:449 sdma_v5_0_ring_emit_mem_sync() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 75d7310..c45e1b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -440,20 +440,19 @@ static void sdma_v5_0_ring_emit_ib(struct amdgpu_ring *ring, */ static void sdma_v5_0_ring_emit_mem_sync(struct amdgpu_ring *ring) { - uint32_t gcr_cntl = - SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | - SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | - SDMA_GCR_GLI_INV(1); + uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV | + SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV | + SDMA_GCR_GLI_INV(1); /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */ amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ)); amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0)); amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) | - SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); + SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0)); amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) | - SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); + SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16)); amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) | - SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); + SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0)); } /** -- 1.8.3.1

4 years, 1 month

[PATCH] drm/doc: Includ fence chain api

by Daniel Vetter

We have this nice kerneldoc, but forgot to include it. Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org --- Documentation/driver-api/dma-buf.rst | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index 7f37ec30d9fd..7f21425d9435 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -178,6 +178,15 @@ DMA Fence Array .. kernel-doc:: include/linux/dma-fence-array.h :internal: +DMA Fence Chain +~~~~~~~~~~~~~~~ + +.. kernel-doc:: drivers/dma-buf/dma-fence-chain.c + :export: + +.. kernel-doc:: include/linux/dma-fence-chain.h + :internal: + DMA Fence uABI/Sync File ~~~~~~~~~~~~~~~~~~~~~~~~ -- 2.31.0

4 years, 1 month

[RFC 0/3] dma-fence: Add a "boost" mechanism

by Rob Clark

From: Rob Clark <robdclark(a)chromium.org> In some cases, like double-buffered rendering, missing vblanks can trick the GPU into running at a lower frequence, when really we want to be running at a higher frequency to not miss the vblanks in the first place. This is partially inspired by a trick i915 does, but implemented via dma-fence for a couple of reasons: 1) To continue to be able to use the atomic helpers 2) To support cases where display and gpu are different drivers The last patch is just proof of concept, in reality I think it may want to be a bit more clever. But sending this out as it is as an RFC to get feedback. Rob Clark (3): dma-fence: Add boost fence op drm/atomic: Call dma_fence_boost() when we've missed a vblank drm/msm: Wire up gpu boost drivers/gpu/drm/drm_atomic_helper.c | 11 +++++++++++ drivers/gpu/drm/msm/msm_fence.c | 10 ++++++++++ drivers/gpu/drm/msm/msm_gpu.c | 13 +++++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 2 ++ include/linux/dma-fence.h | 26 ++++++++++++++++++++++++++ 5 files changed, 62 insertions(+) -- 2.30.2

4 years, 1 month

[PATCH 00/38] Rid W=1 warnings from GPU

by Lee Jones

This set is part of a larger effort attempting to clean-up W=1 kernel builds, which are currently overwhelmingly riddled with niggly little warnings. Lee Jones (38): drm/mediatek/mtk_disp_color: Strip incorrect doc and demote header drm/mediatek/mtk_disp_gamma: Strip and demote non-conformant kernel-doc header drm/radeon/radeon_cs: Fix incorrectly documented function 'radeon_cs_parser_fini' drm/mediatek/mtk_disp_ovl: Strip and demote non-conformant header drm/mediatek/mtk_disp_rdma: Strip and demote non-conformant kernel-doc header drm/sti/sti_hdmi_tx3g4c28phy: Provide function names for kernel-doc headers drm/sti/sti_hda: Provide missing function names drm/sti/sti_tvout: Provide a bunch of missing function names drm/sti/sti_hqvdp: Fix incorrectly named function 'sti_hqvdp_vtg_cb()' drm/amd/amdgpu/amdgpu_ids: Correct some function name disparity drm/amd/amdgpu/amdgpu_debugfs: Fix a couple of misnamed functions drm/amd/amdgpu/amdgpu_gmc: Fix a little naming related doc-rot drm/amd/amdgpu/cik_sdma: Fix a few incorrectly named functions drm/amd/amdgpu/gfx_v7_0: Repair function names in the documentation drm/msm/disp/dpu1/dpu_encoder_phys_cmd: Remove unused variable 'cmd_enc' drm/amd/amdgpu/si_dma: Fix some function name disparity drm/amd/amdgpu/dce_v6_0: Repair function name of 'si_get_number_of_dram_channels()' drm/msm/disp/dpu1/dpu_hw_interrupts: Demote a bunch of kernel-doc abuses drm/radeon/cik: Fix incorrectly named function 'cik_irq_suspend()' drm/radeon/radeon_vm: Fix function naming disparities drm/amd/include/aldebaran_ip_offset: Mark top-level IP_BASE as __maybe_unused drm/msm/disp/dpu1/dpu_plane: Fix a couple of naming issues drm/amd/amdgpu/gmc_v7_0: Fix potential copy/paste issue drm/amd/amdgpu/mmhub_v9_4: Fix naming disparity with 'mmhub_v9_4_set_fault_enable_default()' drm/msm/msm_gem: Demote kernel-doc abuses drm/amd/amdgpu/gmc_v10_0: Fix potential copy/paste issue drm/msm/dp/dp_catalog: Correctly document param 'dp_catalog' drm/msm/dp/dp_link: Fix some potential doc-rot drm/radeon/r100: Realign doc header with function 'r100_cs_packet_parse_vline()' drm/amd/amdgpu/gfx_v9_4_2: Mark functions called by reference as static drm/amd/amdgpu/sdma_v2_4: Correct misnamed function 'sdma_v2_4_ring_emit_hdp_flush()' drm/amd/amdgpu/sdma_v4_0: Realign functions with their headers drm/amd/amdgpu/sdma_v5_0: Fix typo in function name drm/amd/amdgpu/amdgpu_vce: Fix a few incorrectly named functions drm/amd/amdgpu/sdma_v5_2: Repair typo in function name drm/amd/amdgpu/vcn_v1_0: Fix some function naming disparity drm/amd/amdgpu/gfx_v10_0: Demote kernel-doc abuse drm/amd/amdgpu/smuio_v13_0: Realign 'smuio_v13_0_is_host_gpu_xgmi_supported()' header drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 8 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 10 +++--- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 ++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 14 ++++---- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/smuio_v13_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 +-- .../gpu/drm/amd/include/aldebaran_ip_offset.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_color.c | 3 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 +-- drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 3 +- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 4 +-- .../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 --- .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 32 +++++++++---------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 +-- drivers/gpu/drm/msm/dp/dp_catalog.c | 2 +- drivers/gpu/drm/msm/dp/dp_link.c | 6 ++-- drivers/gpu/drm/msm/msm_gem.c | 4 +-- drivers/gpu/drm/radeon/cik.c | 2 +- drivers/gpu/drm/radeon/r100.c | 2 +- drivers/gpu/drm/radeon/radeon_cs.c | 2 +- drivers/gpu/drm/radeon/radeon_vm.c | 4 +-- drivers/gpu/drm/sti/sti_hda.c | 6 ++-- drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c | 4 +-- drivers/gpu/drm/sti/sti_hqvdp.c | 2 +- drivers/gpu/drm/sti/sti_tvout.c | 18 +++++------ 38 files changed, 92 insertions(+), 102 deletions(-) Cc: Alex Deucher <alexander.deucher(a)amd.com> Cc: amd-gfx(a)lists.freedesktop.org Cc: AngeloGioacchino Del Regno <angelogioacchino.delregno(a)somainline.org> Cc: Benjamin Gaignard <benjamin.gaignard(a)linaro.org> Cc: Chandan Uddaraju <chandanu(a)codeaurora.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: Chun-Kuang Hu <chunkuang.hu(a)kernel.org> Cc: Daniel Vetter <daniel(a)ffwll.ch> Cc: David Airlie <airlied(a)linux.ie> Cc: dri-devel(a)lists.freedesktop.org Cc: Evan Quan <evan.quan(a)amd.com> Cc: Fabien Dessenne <fabien.dessenne(a)st.com> Cc: freedreno(a)lists.freedesktop.org Cc: Hawking Zhang <Hawking.Zhang(a)amd.com> Cc: Jerome Glisse <glisse(a)freedesktop.org> Cc: Krishna Manikandan <mkrishn(a)codeaurora.org> Cc: Kuogee Hsieh <khsieh(a)codeaurora.org> Cc: linaro-mm-sig(a)lists.linaro.org Cc: linux-arm-kernel(a)lists.infradead.org Cc: linux-arm-msm(a)vger.kernel.org Cc: linux-mediatek(a)lists.infradead.org Cc: linux-media(a)vger.kernel.org Cc: Luben Tuikov <luben.tuikov(a)amd.com> Cc: Matthias Brugger <matthias.bgg(a)gmail.com> Cc: Philipp Zabel <p.zabel(a)pengutronix.de> Cc: Rob Clark <robdclark(a)gmail.com> Cc: Sean Paul <sean(a)poorly.run> Cc: Stephen Boyd <swboyd(a)chromium.org> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: Vincent Abriou <vincent.abriou(a)st.com> -- 2.31.1

4 years, 1 month

Re: [Linaro-mm-sig] [PATCH v2] drm/amd/amdgpu: Fix errors in documentation of function parameters

by Felix Kuehling

On 2021-04-27 7:27, Fabio M. De Francesco wrote: > In the documentation of functions, removed excess parameters, described > undocumented ones, and fixed syntax errors. > > Signed-off-by: Fabio M. De Francesco <fmdefrancesco(a)gmail.com> > --- > > Changes from v1: Cc'ed all the maintainers. Looks like Alex already applied V1. So this one doesn't apply. "git am -3" tells me: Applying: drm/amd/amdgpu: Fix errors in documentation of function parameters Using index info to reconstruct a base tree... M drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c M drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c M drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c Falling back to patching base and 3-way merge... No changes -- Patch already applied. Regards, Felix > > drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 12 ++++++------ > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 4 +++- > drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 8 ++++---- > 3 files changed, 13 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c > index 2e9b16fb3fcd..bf2939b6eb43 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c > @@ -76,7 +76,7 @@ struct amdgpu_atif { > /** > * amdgpu_atif_call - call an ATIF method > * > - * @handle: acpi handle > + * @atif: acpi handle > * @function: the ATIF function to execute > * @params: ATIF function params > * > @@ -166,7 +166,6 @@ static void amdgpu_atif_parse_functions(struct amdgpu_atif_functions *f, u32 mas > /** > * amdgpu_atif_verify_interface - verify ATIF > * > - * @handle: acpi handle > * @atif: amdgpu atif struct > * > * Execute the ATIF_FUNCTION_VERIFY_INTERFACE ATIF function > @@ -240,8 +239,7 @@ static acpi_handle amdgpu_atif_probe_handle(acpi_handle dhandle) > /** > * amdgpu_atif_get_notification_params - determine notify configuration > * > - * @handle: acpi handle > - * @n: atif notification configuration struct > + * @atif: acpi handle > * > * Execute the ATIF_FUNCTION_GET_SYSTEM_PARAMETERS ATIF function > * to determine if a notifier is used and if so which one > @@ -304,7 +302,7 @@ static int amdgpu_atif_get_notification_params(struct amdgpu_atif *atif) > /** > * amdgpu_atif_query_backlight_caps - get min and max backlight input signal > * > - * @handle: acpi handle > + * @atif: acpi handle > * > * Execute the QUERY_BRIGHTNESS_TRANSFER_CHARACTERISTICS ATIF function > * to determine the acceptable range of backlight values > @@ -363,7 +361,7 @@ static int amdgpu_atif_query_backlight_caps(struct amdgpu_atif *atif) > /** > * amdgpu_atif_get_sbios_requests - get requested sbios event > * > - * @handle: acpi handle > + * @atif: acpi handle > * @req: atif sbios request struct > * > * Execute the ATIF_FUNCTION_GET_SYSTEM_BIOS_REQUESTS ATIF function > @@ -899,6 +897,8 @@ void amdgpu_acpi_fini(struct amdgpu_device *adev) > /** > * amdgpu_acpi_is_s0ix_supported > * > + * @adev: amdgpu_device_pointer > + * > * returns true if supported, false if not. > */ > bool amdgpu_acpi_is_s0ix_supported(struct amdgpu_device *adev) > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c > index 5af464933976..98d31ebad9ce 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c > @@ -111,6 +111,8 @@ static const char *amdkfd_fence_get_timeline_name(struct dma_fence *f) > * a KFD BO and schedules a job to move the BO. > * If fence is already signaled return true. > * If fence is not signaled schedule a evict KFD process work item. > + * > + * @f: dma_fence > */ > static bool amdkfd_fence_enable_signaling(struct dma_fence *f) > { > @@ -131,7 +133,7 @@ static bool amdkfd_fence_enable_signaling(struct dma_fence *f) > /** > * amdkfd_fence_release - callback that fence can be freed > * > - * @fence: fence > + * @f: dma_fence > * > * This function is called when the reference count becomes zero. > * Drops the mm_struct reference and RCU schedules freeing up the fence. > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > index b43e68fc1378..ed3014fbb563 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c > @@ -719,7 +719,7 @@ static void unlock_spi_csq_mutexes(struct amdgpu_device *adev) > } > > /** > - * @get_wave_count: Read device registers to get number of waves in flight for > + * get_wave_count: Read device registers to get number of waves in flight for > * a particular queue. The method also returns the VMID associated with the > * queue. > * > @@ -755,19 +755,19 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, > } > > /** > - * @kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each > + * kgd_gfx_v9_get_cu_occupancy: Reads relevant registers associated with each > * shader engine and aggregates the number of waves that are in flight for the > * process whose pasid is provided as a parameter. The process could have ZERO > * or more queues running and submitting waves to compute units. > * > * @kgd: Handle of device from which to get number of waves in flight > * @pasid: Identifies the process for which this query call is invoked > - * @wave_cnt: Output parameter updated with number of waves in flight that > + * @pasid_wave_cnt: Output parameter updated with number of waves in flight that > * belong to process with given pasid > * @max_waves_per_cu: Output parameter updated with maximum number of waves > * possible per Compute Unit > * > - * @note: It's possible that the device has too many queues (oversubscription) > + * Note: It's possible that the device has too many queues (oversubscription) > * in which case a VMID could be remapped to a different PASID. This could lead > * to an iaccurate wave count. Following is a high-level sequence: > * Time T1: vmid = getVmid(); vmid is associated with Pasid P1

4 years, 2 months

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