Linaro-mm-sig

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Re: [Linaro-mm-sig] [PATCH 3/3] RFC: dma-buf: Add an API for importing and exporting sync files (v5)

by Daniel Vetter

On Wed, Sep 30, 2020 at 11:39:06AM +0200, Michel Dänzer wrote: > On 2020-03-17 10:21 p.m., Jason Ekstrand wrote: > > Explicit synchronization is the future. At least, that seems to be what > > most userspace APIs are agreeing on at this point. However, most of our > > Linux APIs (both userspace and kernel UAPI) are currently built around > > implicit synchronization with dma-buf. While work is ongoing to change > > many of the userspace APIs and protocols to an explicit synchronization > > model, switching over piecemeal is difficult due to the number of > > potential components involved. On the kernel side, many drivers use > > dma-buf including GPU (3D/compute), display, v4l, and others. In > > userspace, we have X11, several Wayland compositors, 3D drivers, compute > > drivers (OpenCL etc.), media encode/decode, and the list goes on. > > > > This patch provides a path forward by allowing userspace to manually > > manage the fences attached to a dma-buf. Alternatively, one can think > > of this as making dma-buf's implicit synchronization simply a carrier > > for an explicit fence. This is accomplished by adding two IOCTLs to > > dma-buf for importing and exporting a sync file to/from the dma-buf. > > This way a userspace component which is uses explicit synchronization, > > such as a Vulkan driver, can manually set the write fence on a buffer > > before handing it off to an implicitly synchronized component such as a > > Wayland compositor or video encoder. In this way, each of the different > > components can be upgraded to an explicit synchronization model one at a > > time as long as the userspace pieces connecting them are aware of it and > > import/export fences at the right times. > > > > There is a potential race condition with this API if userspace is not > > careful. A typical use case for implicit synchronization is to wait for > > the dma-buf to be ready, use it, and then signal it for some other > > component. Because a sync_file cannot be created until it is guaranteed > > to complete in finite time, userspace can only signal the dma-buf after > > it has already submitted the work which uses it to the kernel and has > > received a sync_file back. There is no way to atomically submit a > > wait-use-signal operation. This is not, however, really a problem with > > this API so much as it is a problem with explicit synchronization > > itself. The way this is typically handled is to have very explicit > > ownership transfer points in the API or protocol which ensure that only > > one component is using it at any given time. Both X11 (via the PRESENT > > extension) and Wayland provide such ownership transfer points via > > explicit present and idle messages. > > > > The decision was intentionally made in this patch to make the import and > > export operations IOCTLs on the dma-buf itself rather than as a DRM > > IOCTL. This makes it the import/export operation universal across all > > components which use dma-buf including GPU, display, v4l, and others. > > It also means that a userspace component can do the import/export > > without access to the DRM fd which may be tricky to get in cases where > > the client communicates with DRM via a userspace API such as OpenGL or > > Vulkan. At a future date we may choose to add direct import/export APIs > > to components such as drm_syncobj to avoid allocating a file descriptor > > and going through two ioctls. However, that seems to be something of a > > micro-optimization as import/export operations are likely to happen at a > > rate of a few per frame of rendered or decoded video. > > > > v2 (Jason Ekstrand): > > - Use a wrapper dma_fence_array of all fences including the new one > > when importing an exclusive fence. > > > > v3 (Jason Ekstrand): > > - Lock around setting shared fences as well as exclusive > > - Mark SIGNAL_SYNC_FILE as a read-write ioctl. > > - Initialize ret to 0 in dma_buf_wait_sync_file > > > > v4 (Jason Ekstrand): > > - Use the new dma_resv_get_singleton helper > > > > v5 (Jason Ekstrand): > > - Rename the IOCTLs to import/export rather than wait/signal > > - Drop the WRITE flag and always get/set the exclusive fence > > > > Signed-off-by: Jason Ekstrand <jason(a)jlekstrand.net> > > What's the status of this? DMA_BUF_IOCTL_EXPORT_SYNC_FILE would be useful > for Wayland compositors to wait for client buffers to become ready without > being prone to getting delayed by later HW access to them, so it would be > nice to merge that at least (if DMA_BUF_IOCTL_IMPORT_SYNC_FILE is still > controversial). I think the missing bits are just the usual stuff - igt testcases - userspace using the new ioctls - review of the entire pile I don't think there's any fundamental objections aside from "no one ever pushed this over the finish line". Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

3 years, 10 months

[PATCH] dma-fence: Document recoverable page fault implications

by Daniel Vetter

Recently there was a fairly long thread about recoreable hardware page faults, how they can deadlock, and what to do about that. While the discussion is still fresh I figured good time to try and document the conclusions a bit. This documentation section explains what's the potential problem, and the remedies we've discussed, roughly ordered from best to worst. v2: Linus -> Linux typoe (Dave) v3: - Make it clear drivers only need to implement one option (Christian) - Make it clearer that implicit sync is out the window with exclusive fences (Christian) - Add the fairly theoretical option of segementing the memory (either statically or through dynamic checks at runtime for which piece of memory is managed how) and explain why it's not a great idea (Felix) References: https://lore.kernel.org/dri-devel/20210107030127.20393-1-Felix.Kuehling@amd… Cc: Dave Airlie <airlied(a)gmail.com> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Thomas Hellström <thomas.hellstrom(a)intel.com> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: Jerome Glisse <jglisse(a)redhat.com> Cc: Felix Kuehling <felix.kuehling(a)amd.com> Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org --- Documentation/driver-api/dma-buf.rst | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index a2133d69872c..7f37ec30d9fd 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -257,3 +257,79 @@ fences in the kernel. This means: userspace is allowed to use userspace fencing or long running compute workloads. This also means no implicit fencing for shared buffers in these cases. + +Recoverable Hardware Page Faults Implications +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Modern hardware supports recoverable page faults, which has a lot of +implications for DMA fences. + +First, a pending page fault obviously holds up the work that's running on the +accelerator and a memory allocation is usually required to resolve the fault. +But memory allocations are not allowed to gate completion of DMA fences, which +means any workload using recoverable page faults cannot use DMA fences for +synchronization. Synchronization fences controlled by userspace must be used +instead. + +On GPUs this poses a problem, because current desktop compositor protocols on +Linux rely on DMA fences, which means without an entirely new userspace stack +built on top of userspace fences, they cannot benefit from recoverable page +faults. Specifically this means implicit synchronization will not be possible. +The exception is when page faults are only used as migration hints and never to +on-demand fill a memory request. For now this means recoverable page +faults on GPUs are limited to pure compute workloads. + +Furthermore GPUs usually have shared resources between the 3D rendering and +compute side, like compute units or command submission engines. If both a 3D +job with a DMA fence and a compute workload using recoverable page faults are +pending they could deadlock: + +- The 3D workload might need to wait for the compute job to finish and release + hardware resources first. + +- The compute workload might be stuck in a page fault, because the memory + allocation is waiting for the DMA fence of the 3D workload to complete. + +There are a few options to prevent this problem, one of which drivers need to +ensure: + +- Compute workloads can always be preempted, even when a page fault is pending + and not yet repaired. Not all hardware supports this. + +- DMA fence workloads and workloads which need page fault handling have + independent hardware resources to guarantee forward progress. This could be + achieved through e.g. through dedicated engines and minimal compute unit + reservations for DMA fence workloads. + +- The reservation approach could be further refined by only reserving the + hardware resources for DMA fence workloads when they are in-flight. This must + cover the time from when the DMA fence is visible to other threads up to + moment when fence is completed through dma_fence_signal(). + +- As a last resort, if the hardware provides no useful reservation mechanics, + all workloads must be flushed from the GPU when switching between jobs + requiring DMA fences or jobs requiring page fault handling: This means all DMA + fences must complete before a compute job with page fault handling can be + inserted into the scheduler queue. And vice versa, before a DMA fence can be + made visible anywhere in the system, all compute workloads must be preempted + to guarantee all pending GPU page faults are flushed. + +- Only a fairly theoretical option would be to untangle these dependencies when + allocating memory to repair hardware page faults, either through separate + memory blocks or runtime tracking of the full dependency graph of all DMA + fences. This results very wide impact on the kernel, since resolving the page + on the CPU side can itself involve a page fault. It is much more feasible and + robust to limit the impact of handling hardware page faults to the specific + driver. + +Note that workloads that run on independent hardware like copy engines or other +GPUs do not have any impact. This allows us to keep using DMA fences internally +in the kernel even for resolving hardware page faults, e.g. by using copy +engines to clear or copy memory needed to resolve the page fault. + +In some ways this page fault problem is a special case of the `Infinite DMA +Fences` discussions: Infinite fences from compute workloads are allowed to +depend on DMA fences, but not the other way around. And not even the page fault +problem is new, because some other CPU thread in userspace might +hit a page fault which holds up a userspace fence - supporting page faults on +GPUs doesn't anything fundamentally new. -- 2.30.0

3 years, 10 months

Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Thu, Mar 11, 2021 at 2:12 PM Thomas Hellström (Intel) <thomas_os(a)shipmail.org> wrote: > > Hi! > > On 3/11/21 2:00 PM, Daniel Vetter wrote: > > On Thu, Mar 11, 2021 at 11:22:06AM +0100, Thomas Hellström (Intel) wrote: > >> On 3/1/21 3:09 PM, Daniel Vetter wrote: > >>> On Mon, Mar 1, 2021 at 11:17 AM Christian König > >>> <christian.koenig(a)amd.com> wrote: > >>>> > >>>> Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): > >>>>> On 3/1/21 10:05 AM, Daniel Vetter wrote: > >>>>>> On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) > >>>>>> wrote: > >>>>>>> Hi, > >>>>>>> > >>>>>>> On 3/1/21 9:28 AM, Daniel Vetter wrote: > >>>>>>>> On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > >>>>>>>> <thomas_os(a)shipmail.org> wrote: > >>>>>>>>> On 2/26/21 2:28 PM, Daniel Vetter wrote: > >>>>>>>>>> So I think it stops gup. But I haven't verified at all. Would be > >>>>>>>>>> good > >>>>>>>>>> if Christian can check this with some direct io to a buffer in > >>>>>>>>>> system > >>>>>>>>>> memory. > >>>>>>>>> Hmm, > >>>>>>>>> > >>>>>>>>> Docs (again vm_normal_page() say) > >>>>>>>>> > >>>>>>>>> * VM_MIXEDMAP mappings can likewise contain memory with or > >>>>>>>>> without "struct > >>>>>>>>> * page" backing, however the difference is that _all_ pages > >>>>>>>>> with a struct > >>>>>>>>> * page (that is, those where pfn_valid is true) are refcounted > >>>>>>>>> and > >>>>>>>>> considered > >>>>>>>>> * normal pages by the VM. The disadvantage is that pages are > >>>>>>>>> refcounted > >>>>>>>>> * (which can be slower and simply not an option for some PFNMAP > >>>>>>>>> users). The > >>>>>>>>> * advantage is that we don't have to follow the strict > >>>>>>>>> linearity rule of > >>>>>>>>> * PFNMAP mappings in order to support COWable mappings. > >>>>>>>>> > >>>>>>>>> but it's true __vm_insert_mixed() ends up in the insert_pfn() > >>>>>>>>> path, so > >>>>>>>>> the above isn't really true, which makes me wonder if and in that > >>>>>>>>> case > >>>>>>>>> why there could any longer ever be a significant performance > >>>>>>>>> difference > >>>>>>>>> between MIXEDMAP and PFNMAP. > >>>>>>>> Yeah it's definitely confusing. I guess I'll hack up a patch and see > >>>>>>>> what sticks. > >>>>>>>> > >>>>>>>>> BTW regarding the TTM hugeptes, I don't think we ever landed that > >>>>>>>>> devmap > >>>>>>>>> hack, so they are (for the non-gup case) relying on > >>>>>>>>> vma_is_special_huge(). For the gup case, I think the bug is still > >>>>>>>>> there. > >>>>>>>> Maybe there's another devmap hack, but the ttm_vm_insert functions do > >>>>>>>> use PFN_DEV and all that. And I think that stops gup_fast from trying > >>>>>>>> to find the underlying page. > >>>>>>>> -Daniel > >>>>>>> Hmm perhaps it might, but I don't think so. The fix I tried out was > >>>>>>> to set > >>>>>>> > >>>>>>> PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be > >>>>>>> true, and > >>>>>>> then > >>>>>>> > >>>>>>> follow_devmap_pmd()->get_dev_pagemap() which returns NULL and > >>>>>>> gup_fast() > >>>>>>> backs off, > >>>>>>> > >>>>>>> in the end that would mean setting in stone that "if there is a huge > >>>>>>> devmap > >>>>>>> page table entry for which we haven't registered any devmap struct > >>>>>>> pages > >>>>>>> (get_dev_pagemap returns NULL), we should treat that as a "special" > >>>>>>> huge > >>>>>>> page table entry". > >>>>>>> > >>>>>>> From what I can tell, all code calling get_dev_pagemap() already > >>>>>>> does that, > >>>>>>> it's just a question of getting it accepted and formalizing it. > >>>>>> Oh I thought that's already how it works, since I didn't spot anything > >>>>>> else that would block gup_fast from falling over. I guess really would > >>>>>> need some testcases to make sure direct i/o (that's the easiest to test) > >>>>>> fails like we expect. > >>>>> Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. > >>>>> Otherwise pmd_devmap() will not return true and since there is no > >>>>> pmd_special() things break. > >>>> Is that maybe the issue we have seen with amdgpu and huge pages? > >>> Yeah, essentially when you have a hugepte inserted by ttm, and it > >>> happens to point at system memory, then gup will work on that. And > >>> create all kinds of havoc. > >>> > >>>> Apart from that I'm lost guys, that devmap and gup stuff is not > >>>> something I have a good knowledge of apart from a one mile high view. > >>> I'm not really better, hence would be good to do a testcase and see. > >>> This should provoke it: > >>> - allocate nicely aligned bo in system memory > >>> - mmap, again nicely aligned to 2M > >>> - do some direct io from a filesystem into that mmap, that should trigger gup > >>> - before the gup completes free the mmap and bo so that ttm recycles > >>> the pages, which should trip up on the elevated refcount. If you wait > >>> until the direct io is completely, then I think nothing bad can be > >>> observed. > >>> > >>> Ofc if your amdgpu+hugepte issue is something else, then maybe we have > >>> another issue. > >>> > >>> Also usual caveat: I'm not an mm hacker either, so might be completely wrong. > >>> -Daniel > >> So I did the following quick experiment on vmwgfx, and it turns out that > >> with it, > >> fast gup never succeeds. Without the "| PFN_MAP", it typically succeeds > >> > >> I should probably craft an RFC formalizing this. > > Yeah I think that would be good. Maybe even more formalized if we also > > switch over to VM_PFNMAP, since afaiui these pte flags here only stop the > > fast gup path. And slow gup can still peak through VM_MIXEDMAP. Or > > something like that. > > > > Otoh your description of when it only sometimes succeeds would indicate my > > understanding of VM_PFNMAP vs VM_MIXEDMAP is wrong here. > > My understanding from reading the vmf_insert_mixed() code is that iff > the arch has pte_special(), VM_MIXEDMAP should be harmless. But that's > not consistent with the vm_normal_page() doc. For architectures without > pte_special, VM_PFNMAP must be used, and then we must also block COW > mappings. > > If we can get someone can commit to verify that the potential PAT WC > performance issue is gone with PFNMAP, I can put together a series with > that included. Iirc when I checked there's not much archs without pte_special, so I guess that's why we luck out. Hopefully. > As for existing userspace using COW TTM mappings, I once had a couple of > test cases to verify that it actually worked, in particular together > with huge PMDs and PUDs where breaking COW would imply splitting those, > but I can't think of anything else actually wanting to do that other > than by mistake. Yeah disallowing MAP_PRIVATE mappings would be another good thing to lock down. Really doesn't make much sense. -Daniel > /Thomas > > > > > > Christian, what's your take? > > -Daniel > > > >> /Thomas > >> > >> diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c > >> b/drivers/gpu/drm/ttm/ttm_bo_vm.c > >> index 6dc96cf66744..72b6fb17c984 100644 > >> --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c > >> +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c > >> @@ -195,6 +195,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > >> *vmf, > >> pfn_t pfnt; > >> struct ttm_tt *ttm = bo->ttm; > >> bool write = vmf->flags & FAULT_FLAG_WRITE; > >> + struct dev_pagemap *pagemap; > >> > >> /* Fault should not cross bo boundary. */ > >> page_offset &= ~(fault_page_size - 1); > >> @@ -210,6 +211,17 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > >> *vmf, > >> if ((pfn & (fault_page_size - 1)) != 0) > >> goto out_fallback; > >> > >> + /* > >> + * Huge entries must be special, that is marking them as devmap > >> + * with no backing device map range. If there is a backing > >> + * range, Don't insert a huge entry. > >> + */ > >> + pagemap = get_dev_pagemap(pfn, NULL); > >> + if (pagemap) { > >> + put_dev_pagemap(pagemap); > >> + goto out_fallback; > >> + } > >> + > >> /* Check that memory is contiguous. */ > >> if (!bo->mem.bus.is_iomem) { > >> for (i = 1; i < fault_page_size; ++i) { > >> @@ -223,7 +235,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > >> *vmf, > >> } > >> } > >> > >> - pfnt = __pfn_to_pfn_t(pfn, PFN_DEV); > >> + pfnt = __pfn_to_pfn_t(pfn, PFN_DEV | PFN_MAP); > >> if (fault_page_size == (HPAGE_PMD_SIZE >> PAGE_SHIFT)) > >> ret = vmf_insert_pfn_pmd_prot(vmf, pfnt, pgprot, write); > >> #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD > >> @@ -236,6 +248,21 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > >> *vmf, > >> if (ret != VM_FAULT_NOPAGE) > >> goto out_fallback; > >> > >> +#if 1 > >> + { > >> + int npages; > >> + struct page *page; > >> + > >> + npages = get_user_pages_fast_only(vmf->address, 1, 0, > >> &page); > >> + if (npages == 1) { > >> + DRM_WARN("Fast gup succeeded. Bad.\n"); > >> + put_page(page); > >> + } else { > >> + DRM_INFO("Fast gup failed. Good.\n"); > >> + } > >> + } > >> +#endif > >> + > >> return VM_FAULT_NOPAGE; > >> out_fallback: > >> count_vm_event(THP_FAULT_FALLBACK); > >> > >> > >> > >> > >> -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

3 years, 10 months

Re: [Linaro-mm-sig] [PATCH]] drm/amdgpu/gfx9: add gfxoff quirk

by Alex Deucher

On Thu, Mar 11, 2021 at 10:02 AM Alexandre Desnoyers <alex(a)qtec.com> wrote: > > On Thu, Mar 11, 2021 at 2:49 PM Daniel Gomez <daniel(a)qtec.com> wrote: > > > > On Thu, 11 Mar 2021 at 10:09, Daniel Gomez <daniel(a)qtec.com> wrote: > > > > > > On Wed, 10 Mar 2021 at 18:06, Alex Deucher <alexdeucher(a)gmail.com> wrote: > > > > > > > > On Wed, Mar 10, 2021 at 11:37 AM Daniel Gomez <daniel(a)qtec.com> wrote: > > > > > > > > > > Disabling GFXOFF via the quirk list fixes a hardware lockup in > > > > > Ryzen V1605B, RAVEN 0x1002:0x15DD rev 0x83. > > > > > > > > > > Signed-off-by: Daniel Gomez <daniel(a)qtec.com> > > > > > --- > > > > > > > > > > This patch is a continuation of the work here: > > > > > https://lkml.org/lkml/2021/2/3/122 where a hardware lockup was discussed and > > > > > a dma_fence deadlock was provoke as a side effect. To reproduce the issue > > > > > please refer to the above link. > > > > > > > > > > The hardware lockup was introduced in 5.6-rc1 for our particular revision as it > > > > > wasn't part of the new blacklist. Before that, in kernel v5.5, this hardware was > > > > > working fine without any hardware lock because the GFXOFF was actually disabled > > > > > by the if condition for the CHIP_RAVEN case. So this patch, adds the 'Radeon > > > > > Vega Mobile Series [1002:15dd] (rev 83)' to the blacklist to disable the GFXOFF. > > > > > > > > > > But besides the fix, I'd like to ask from where this revision comes from. Is it > > > > > an ASIC revision or is it hardcoded in the VBIOS from our vendor? From what I > > > > > can see, it comes from the ASIC and I wonder if somehow we can get an APU in the > > > > > future, 'not blacklisted', with the same problem. Then, should this table only > > > > > filter for the vendor and device and not the revision? Do you know if there are > > > > > any revisions for the 1002:15dd validated, tested and functional? > > > > > > > > The pci revision id (RID) is used to specify the specific SKU within a > > > > family. GFXOFF is supposed to be working on all raven variants. It > > > > was tested and functional on all reference platforms and any OEM > > > > platforms that launched with Linux support. There are a lot of > > > > dependencies on sbios in the early raven variants (0x15dd), so it's > > > > likely more of a specific platform issue, but there is not a good way > > > > to detect this so we use the DID/SSID/RID as a proxy. The newer raven > > > > variants (0x15d8) have much better GFXOFF support since they all > > > > shipped with newer firmware and sbios. > > > > > > We took one of the first reference platform boards to design our > > > custom board based on the V1605B and I assume it has one of the early 'unstable' > > > raven variants with RID 0x83. Also, as OEM we are in control of the bios > > > (provided by insyde) but I wasn't sure about the RID so, thanks for the > > > clarification. Is there anything we can do with the bios to have the GFXOFF > > > enabled and 'stable' for this particular revision? Otherwise we'd need to add > > > the 0x83 RID to the table. Also, there is an extra ']' in the patch > > > subject. Sorry > > > for that. Would you need a new patch in case you accept it with the ']' removed? > > > > > > Good to hear that the newer raven versions have better GFXOFF support. > > > > Adding Alex Desnoyer to the loop as he is the electronic/hardware and > > bios responsible so, he can > > provide more information about this. > > Hello everyone, > > We, Qtechnology, are the OEM of the hardware platform where we > originally discovered the bug. Our platform is based on the AMD > Dibbler V-1000 reference design, with the latest Insyde BIOS release > available for the (now unsupported) Dibbler platform. We have the > Insyde BIOS source code internally, so we can make some modifications > as needed. > > The last test that Daniel and myself performed was on a standard > Dibbler PCB rev.B1 motherboard (NOT our platform), and using the > corresponding latest AMD released BIOS "RDB1109GA". As Daniel wrote, > the hardware lockup can be reproduced on the Dibbler, even if it has a > different RID that our V1605B APU. > > We also have a Neousys Technology POC-515 embedded computer (V-1000, > V1605B) in our office. The Neousys PC also uses Insyde BIOS. This > computer is also locking-up in the test. > https://www.neousys-tech.com/en/product/application/rugged-embedded/poc-500… > > > Digging into the BIOS source code, the only reference to GFXOFF is in > the SMU and PSP firmware release notes, where some bug fixes have been > mentioned for previous SMU/PSP releases. After a quick "git grep -i > gfx | grep -i off", there seems to be no mention of GFXOFF in the > Insyde UEFI (inluding AMD PI) code base. I would appreciate any > information regarding BIOS modification needed to make the GFXOFF > feature stable. As you (Alex Deucher) mentionned, it should be > functional on all AMD Raven reference platforms. > It's handled by the firmwares carried by the sbios. I'm not sure what versions off hand. Probably want to make sure you have the latest ones. Do you have an AMD partner contact? It might be best to bring this up with them. Regarding the issues you are seeing is this a general issue with all workloads that use the GFX shader cores? Or just specific workloads? If it's just compute workloads, you might try this patch. It may fix the issue for you. Alex > > Regards, > > Alexandre Desnoyers > > > > > > I've now done a test on the reference platform (dibbler) with the > > latest bios available > > and the hw lockup can be also reproduced with the same steps. > > > > For reference, I'm using mainline kernel 5.12-rc2. > > > > [ 5.938544] [drm] initializing kernel modesetting (RAVEN > > 0x1002:0x15DD 0x1002:0x15DD 0xC1). > > [ 5.939942] amdgpu: ATOM BIOS: 113-RAVEN-11 > > > > As in the previous cases, the clocks go to 100% of usage when the hang occurs. > > > > However, when the gpu hangs, dmesg output displays the following: > > > > [ 1568.279847] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx > > timeout, signaled seq=188, emitted seq=191 > > [ 1568.434084] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process > > information: process Xorg pid 311 thread Xorg:cs0 pid 312 > > [ 1568.279847] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx > > timeout, signaled seq=188, emitted seq=191 > > [ 1568.434084] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process > > information: process Xorg pid 311 thread Xorg:cs0 pid 312 > > [ 1568.507000] amdgpu 0000:01:00.0: amdgpu: GPU reset begin! > > [ 1628.491882] rcu: INFO: rcu_sched self-detected stall on CPU > > [ 1628.491882] rcu: 3-...!: (665 ticks this GP) > > idle=f9a/1/0x4000000000000000 softirq=188533/188533 fqs=15 > > [ 1628.491882] rcu: rcu_sched kthread timer wakeup didn't happen for > > 58497 jiffies! g726761 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 > > [ 1628.491882] rcu: Possible timer handling issue on cpu=2 > > timer-softirq=55225 > > [ 1628.491882] rcu: rcu_sched kthread starved for 58500 jiffies! > > g726761 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=2 > > [ 1628.491882] rcu: Unless rcu_sched kthread gets sufficient CPU > > time, OOM is now expected behavior. > > [ 1628.491882] rcu: RCU grace-period kthread stack dump: > > [ 1628.491882] rcu: Stack dump where RCU GP kthread last ran: > > [ 1808.518445] rcu: INFO: rcu_sched self-detected stall on CPU > > [ 1808.518445] rcu: 3-...!: (2643 ticks this GP) > > idle=f9a/1/0x4000000000000000 softirq=188533/188533 fqs=15 > > [ 1808.518445] rcu: rcu_sched kthread starved for 238526 jiffies! > > g726761 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x0 ->cpu=2 > > [ 1808.518445] rcu: Unless rcu_sched kthread gets sufficient CPU > > time, OOM is now expected behavior. > > [ 1808.518445] rcu: RCU grace-period kthread stack dump: > > [ 1808.518445] rcu: Stack dump where RCU GP kthread last ran: > > > > > > > > Daniel > > > > > > > > > > > Alex > > > > > > > > > > > > > > > > > > Logs: > > > > > [ 27.708348] [drm] initializing kernel modesetting (RAVEN > > > > > 0x1002:0x15DD 0x1002:0x15DD 0x83). > > > > > [ 27.789156] amdgpu: ATOM BIOS: 113-RAVEN-115 > > > > > > > > > > Thanks in advance, > > > > > Daniel > > > > > > > > > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ > > > > > 1 file changed, 2 insertions(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > > > index 65db88bb6cbc..319d4b99aec8 100644 > > > > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > > > @@ -1243,6 +1243,8 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { > > > > > { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, > > > > > /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ > > > > > { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, > > > > > + /* GFXOFF provokes a hw lockup on 83 parts with a VBIOS 113-RAVEN-115 */ > > > > > + { 0x1002, 0x15dd, 0x1002, 0x15dd, 0x83 }, > > > > > { 0, 0, 0, 0, 0 }, > > > > > }; > > > > > > > > > > -- > > > > > 2.30.1 > > > > > > > > > > _______________________________________________ > > > > > dri-devel mailing list > > > > > dri-devel(a)lists.freedesktop.org > > > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel

3 years, 10 months

Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Thu, Mar 11, 2021 at 11:22:06AM +0100, Thomas Hellström (Intel) wrote: > > On 3/1/21 3:09 PM, Daniel Vetter wrote: > > On Mon, Mar 1, 2021 at 11:17 AM Christian König > > <christian.koenig(a)amd.com> wrote: > > > > > > > > > Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): > > > > On 3/1/21 10:05 AM, Daniel Vetter wrote: > > > > > On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) > > > > > wrote: > > > > > > Hi, > > > > > > > > > > > > On 3/1/21 9:28 AM, Daniel Vetter wrote: > > > > > > > On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > > > > > > > <thomas_os(a)shipmail.org> wrote: > > > > > > > > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > > > > > > > > So I think it stops gup. But I haven't verified at all. Would be > > > > > > > > > good > > > > > > > > > if Christian can check this with some direct io to a buffer in > > > > > > > > > system > > > > > > > > > memory. > > > > > > > > Hmm, > > > > > > > > > > > > > > > > Docs (again vm_normal_page() say) > > > > > > > > > > > > > > > > * VM_MIXEDMAP mappings can likewise contain memory with or > > > > > > > > without "struct > > > > > > > > * page" backing, however the difference is that _all_ pages > > > > > > > > with a struct > > > > > > > > * page (that is, those where pfn_valid is true) are refcounted > > > > > > > > and > > > > > > > > considered > > > > > > > > * normal pages by the VM. The disadvantage is that pages are > > > > > > > > refcounted > > > > > > > > * (which can be slower and simply not an option for some PFNMAP > > > > > > > > users). The > > > > > > > > * advantage is that we don't have to follow the strict > > > > > > > > linearity rule of > > > > > > > > * PFNMAP mappings in order to support COWable mappings. > > > > > > > > > > > > > > > > but it's true __vm_insert_mixed() ends up in the insert_pfn() > > > > > > > > path, so > > > > > > > > the above isn't really true, which makes me wonder if and in that > > > > > > > > case > > > > > > > > why there could any longer ever be a significant performance > > > > > > > > difference > > > > > > > > between MIXEDMAP and PFNMAP. > > > > > > > Yeah it's definitely confusing. I guess I'll hack up a patch and see > > > > > > > what sticks. > > > > > > > > > > > > > > > BTW regarding the TTM hugeptes, I don't think we ever landed that > > > > > > > > devmap > > > > > > > > hack, so they are (for the non-gup case) relying on > > > > > > > > vma_is_special_huge(). For the gup case, I think the bug is still > > > > > > > > there. > > > > > > > Maybe there's another devmap hack, but the ttm_vm_insert functions do > > > > > > > use PFN_DEV and all that. And I think that stops gup_fast from trying > > > > > > > to find the underlying page. > > > > > > > -Daniel > > > > > > Hmm perhaps it might, but I don't think so. The fix I tried out was > > > > > > to set > > > > > > > > > > > > PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be > > > > > > true, and > > > > > > then > > > > > > > > > > > > follow_devmap_pmd()->get_dev_pagemap() which returns NULL and > > > > > > gup_fast() > > > > > > backs off, > > > > > > > > > > > > in the end that would mean setting in stone that "if there is a huge > > > > > > devmap > > > > > > page table entry for which we haven't registered any devmap struct > > > > > > pages > > > > > > (get_dev_pagemap returns NULL), we should treat that as a "special" > > > > > > huge > > > > > > page table entry". > > > > > > > > > > > > From what I can tell, all code calling get_dev_pagemap() already > > > > > > does that, > > > > > > it's just a question of getting it accepted and formalizing it. > > > > > Oh I thought that's already how it works, since I didn't spot anything > > > > > else that would block gup_fast from falling over. I guess really would > > > > > need some testcases to make sure direct i/o (that's the easiest to test) > > > > > fails like we expect. > > > > Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. > > > > Otherwise pmd_devmap() will not return true and since there is no > > > > pmd_special() things break. > > > Is that maybe the issue we have seen with amdgpu and huge pages? > > Yeah, essentially when you have a hugepte inserted by ttm, and it > > happens to point at system memory, then gup will work on that. And > > create all kinds of havoc. > > > > > Apart from that I'm lost guys, that devmap and gup stuff is not > > > something I have a good knowledge of apart from a one mile high view. > > I'm not really better, hence would be good to do a testcase and see. > > This should provoke it: > > - allocate nicely aligned bo in system memory > > - mmap, again nicely aligned to 2M > > - do some direct io from a filesystem into that mmap, that should trigger gup > > - before the gup completes free the mmap and bo so that ttm recycles > > the pages, which should trip up on the elevated refcount. If you wait > > until the direct io is completely, then I think nothing bad can be > > observed. > > > > Ofc if your amdgpu+hugepte issue is something else, then maybe we have > > another issue. > > > > Also usual caveat: I'm not an mm hacker either, so might be completely wrong. > > -Daniel > > So I did the following quick experiment on vmwgfx, and it turns out that > with it, > fast gup never succeeds. Without the "| PFN_MAP", it typically succeeds > > I should probably craft an RFC formalizing this. Yeah I think that would be good. Maybe even more formalized if we also switch over to VM_PFNMAP, since afaiui these pte flags here only stop the fast gup path. And slow gup can still peak through VM_MIXEDMAP. Or something like that. Otoh your description of when it only sometimes succeeds would indicate my understanding of VM_PFNMAP vs VM_MIXEDMAP is wrong here. Christian, what's your take? -Daniel > > /Thomas > > diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c > b/drivers/gpu/drm/ttm/ttm_bo_vm.c > index 6dc96cf66744..72b6fb17c984 100644 > --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c > +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c > @@ -195,6 +195,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > *vmf, > pfn_t pfnt; > struct ttm_tt *ttm = bo->ttm; > bool write = vmf->flags & FAULT_FLAG_WRITE; > + struct dev_pagemap *pagemap; > > /* Fault should not cross bo boundary. */ > page_offset &= ~(fault_page_size - 1); > @@ -210,6 +211,17 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > *vmf, > if ((pfn & (fault_page_size - 1)) != 0) > goto out_fallback; > > + /* > + * Huge entries must be special, that is marking them as devmap > + * with no backing device map range. If there is a backing > + * range, Don't insert a huge entry. > + */ > + pagemap = get_dev_pagemap(pfn, NULL); > + if (pagemap) { > + put_dev_pagemap(pagemap); > + goto out_fallback; > + } > + > /* Check that memory is contiguous. */ > if (!bo->mem.bus.is_iomem) { > for (i = 1; i < fault_page_size; ++i) { > @@ -223,7 +235,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > *vmf, > } > } > > - pfnt = __pfn_to_pfn_t(pfn, PFN_DEV); > + pfnt = __pfn_to_pfn_t(pfn, PFN_DEV | PFN_MAP); > if (fault_page_size == (HPAGE_PMD_SIZE >> PAGE_SHIFT)) > ret = vmf_insert_pfn_pmd_prot(vmf, pfnt, pgprot, write); > #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD > @@ -236,6 +248,21 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > *vmf, > if (ret != VM_FAULT_NOPAGE) > goto out_fallback; > > +#if 1 > + { > + int npages; > + struct page *page; > + > + npages = get_user_pages_fast_only(vmf->address, 1, 0, > &page); > + if (npages == 1) { > + DRM_WARN("Fast gup succeeded. Bad.\n"); > + put_page(page); > + } else { > + DRM_INFO("Fast gup failed. Good.\n"); > + } > + } > +#endif > + > return VM_FAULT_NOPAGE; > out_fallback: > count_vm_event(THP_FAULT_FALLBACK); > > > > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

3 years, 10 months

Re: [Linaro-mm-sig] [PATCH]] drm/amdgpu/gfx9: add gfxoff quirk

by Alex Deucher

On Wed, Mar 10, 2021 at 11:37 AM Daniel Gomez <daniel(a)qtec.com> wrote: > > Disabling GFXOFF via the quirk list fixes a hardware lockup in > Ryzen V1605B, RAVEN 0x1002:0x15DD rev 0x83. > > Signed-off-by: Daniel Gomez <daniel(a)qtec.com> > --- > > This patch is a continuation of the work here: > https://lkml.org/lkml/2021/2/3/122 where a hardware lockup was discussed and > a dma_fence deadlock was provoke as a side effect. To reproduce the issue > please refer to the above link. > > The hardware lockup was introduced in 5.6-rc1 for our particular revision as it > wasn't part of the new blacklist. Before that, in kernel v5.5, this hardware was > working fine without any hardware lock because the GFXOFF was actually disabled > by the if condition for the CHIP_RAVEN case. So this patch, adds the 'Radeon > Vega Mobile Series [1002:15dd] (rev 83)' to the blacklist to disable the GFXOFF. > > But besides the fix, I'd like to ask from where this revision comes from. Is it > an ASIC revision or is it hardcoded in the VBIOS from our vendor? From what I > can see, it comes from the ASIC and I wonder if somehow we can get an APU in the > future, 'not blacklisted', with the same problem. Then, should this table only > filter for the vendor and device and not the revision? Do you know if there are > any revisions for the 1002:15dd validated, tested and functional? The pci revision id (RID) is used to specify the specific SKU within a family. GFXOFF is supposed to be working on all raven variants. It was tested and functional on all reference platforms and any OEM platforms that launched with Linux support. There are a lot of dependencies on sbios in the early raven variants (0x15dd), so it's likely more of a specific platform issue, but there is not a good way to detect this so we use the DID/SSID/RID as a proxy. The newer raven variants (0x15d8) have much better GFXOFF support since they all shipped with newer firmware and sbios. Alex > > Logs: > [ 27.708348] [drm] initializing kernel modesetting (RAVEN > 0x1002:0x15DD 0x1002:0x15DD 0x83). > [ 27.789156] amdgpu: ATOM BIOS: 113-RAVEN-115 > > Thanks in advance, > Daniel > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 65db88bb6cbc..319d4b99aec8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1243,6 +1243,8 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { > { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, > /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ > { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, > + /* GFXOFF provokes a hw lockup on 83 parts with a VBIOS 113-RAVEN-115 */ > + { 0x1002, 0x15dd, 0x1002, 0x15dd, 0x83 }, > { 0, 0, 0, 0, 0 }, > }; > > -- > 2.30.1 > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

3 years, 10 months

Re: [Linaro-mm-sig] [PATCH] drm/amdgpu: Remove unnecessary conversion to bool

by Alex Deucher

On Sun, Mar 7, 2021 at 10:14 PM Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> wrote: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1600:40-45: WARNING: conversion > to bool not needed here. > > ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1598:40-45: WARNING: conversion > to bool not needed here. > > Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> > Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> This patch was already applied. Alex > --- > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > index 690a509..b39e7db 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > @@ -1595,9 +1595,9 @@ static int sdma_v5_2_set_clockgating_state(void *handle, > case CHIP_VANGOGH: > case CHIP_DIMGREY_CAVEFISH: > sdma_v5_2_update_medium_grain_clock_gating(adev, > - state == AMD_CG_STATE_GATE ? true : false); > + state == AMD_CG_STATE_GATE); > sdma_v5_2_update_medium_grain_light_sleep(adev, > - state == AMD_CG_STATE_GATE ? true : false); > + state == AMD_CG_STATE_GATE); > break; > default: > break; > -- > 1.8.3.1 > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

3 years, 10 months

Re: [Linaro-mm-sig] [PATCH] drm/amdgpu: Remove unnecessary conversion to bool

by Alex Deucher

On Wed, Mar 3, 2021 at 4:18 AM Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> wrote: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2252:40-45: WARNING: conversion > to bool not needed here. > > Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> > Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > index c8c22c1..00d3773 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > @@ -2249,7 +2249,7 @@ static int sdma_v4_0_set_powergating_state(void *handle, > case CHIP_RAVEN: > case CHIP_RENOIR: > sdma_v4_1_update_power_gating(adev, > - state == AMD_PG_STATE_GATE ? true : false); > + state == AMD_PG_STATE_GATE); > break; > default: > break; > -- > 1.8.3.1 > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

3 years, 10 months

Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Christian König

Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): > > On 3/1/21 10:05 AM, Daniel Vetter wrote: >> On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) >> wrote: >>> Hi, >>> >>> On 3/1/21 9:28 AM, Daniel Vetter wrote: >>>> On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) >>>> <thomas_os(a)shipmail.org> wrote: >>>>> On 2/26/21 2:28 PM, Daniel Vetter wrote: >>>>>> So I think it stops gup. But I haven't verified at all. Would be >>>>>> good >>>>>> if Christian can check this with some direct io to a buffer in >>>>>> system >>>>>> memory. >>>>> Hmm, >>>>> >>>>> Docs (again vm_normal_page() say) >>>>> >>>>> * VM_MIXEDMAP mappings can likewise contain memory with or >>>>> without "struct >>>>> * page" backing, however the difference is that _all_ pages >>>>> with a struct >>>>> * page (that is, those where pfn_valid is true) are refcounted >>>>> and >>>>> considered >>>>> * normal pages by the VM. The disadvantage is that pages are >>>>> refcounted >>>>> * (which can be slower and simply not an option for some PFNMAP >>>>> users). The >>>>> * advantage is that we don't have to follow the strict >>>>> linearity rule of >>>>> * PFNMAP mappings in order to support COWable mappings. >>>>> >>>>> but it's true __vm_insert_mixed() ends up in the insert_pfn() >>>>> path, so >>>>> the above isn't really true, which makes me wonder if and in that >>>>> case >>>>> why there could any longer ever be a significant performance >>>>> difference >>>>> between MIXEDMAP and PFNMAP. >>>> Yeah it's definitely confusing. I guess I'll hack up a patch and see >>>> what sticks. >>>> >>>>> BTW regarding the TTM hugeptes, I don't think we ever landed that >>>>> devmap >>>>> hack, so they are (for the non-gup case) relying on >>>>> vma_is_special_huge(). For the gup case, I think the bug is still >>>>> there. >>>> Maybe there's another devmap hack, but the ttm_vm_insert functions do >>>> use PFN_DEV and all that. And I think that stops gup_fast from trying >>>> to find the underlying page. >>>> -Daniel >>> Hmm perhaps it might, but I don't think so. The fix I tried out was >>> to set >>> >>> PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be >>> true, and >>> then >>> >>> follow_devmap_pmd()->get_dev_pagemap() which returns NULL and >>> gup_fast() >>> backs off, >>> >>> in the end that would mean setting in stone that "if there is a huge >>> devmap >>> page table entry for which we haven't registered any devmap struct >>> pages >>> (get_dev_pagemap returns NULL), we should treat that as a "special" >>> huge >>> page table entry". >>> >>> From what I can tell, all code calling get_dev_pagemap() already >>> does that, >>> it's just a question of getting it accepted and formalizing it. >> Oh I thought that's already how it works, since I didn't spot anything >> else that would block gup_fast from falling over. I guess really would >> need some testcases to make sure direct i/o (that's the easiest to test) >> fails like we expect. > > Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. > Otherwise pmd_devmap() will not return true and since there is no > pmd_special() things break. Is that maybe the issue we have seen with amdgpu and huge pages? Apart from that I'm lost guys, that devmap and gup stuff is not something I have a good knowledge of apart from a one mile high view. Christian. > > /Thomas > > > >> -Daniel

3 years, 10 months

Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) wrote: > Hi, > > On 3/1/21 9:28 AM, Daniel Vetter wrote: > > On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > > <thomas_os(a)shipmail.org> wrote: > > > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > > > So I think it stops gup. But I haven't verified at all. Would be good > > > > if Christian can check this with some direct io to a buffer in system > > > > memory. > > > Hmm, > > > > > > Docs (again vm_normal_page() say) > > > > > > * VM_MIXEDMAP mappings can likewise contain memory with or without "struct > > > * page" backing, however the difference is that _all_ pages with a struct > > > * page (that is, those where pfn_valid is true) are refcounted and > > > considered > > > * normal pages by the VM. The disadvantage is that pages are refcounted > > > * (which can be slower and simply not an option for some PFNMAP > > > users). The > > > * advantage is that we don't have to follow the strict linearity rule of > > > * PFNMAP mappings in order to support COWable mappings. > > > > > > but it's true __vm_insert_mixed() ends up in the insert_pfn() path, so > > > the above isn't really true, which makes me wonder if and in that case > > > why there could any longer ever be a significant performance difference > > > between MIXEDMAP and PFNMAP. > > Yeah it's definitely confusing. I guess I'll hack up a patch and see > > what sticks. > > > > > BTW regarding the TTM hugeptes, I don't think we ever landed that devmap > > > hack, so they are (for the non-gup case) relying on > > > vma_is_special_huge(). For the gup case, I think the bug is still there. > > Maybe there's another devmap hack, but the ttm_vm_insert functions do > > use PFN_DEV and all that. And I think that stops gup_fast from trying > > to find the underlying page. > > -Daniel > > Hmm perhaps it might, but I don't think so. The fix I tried out was to set > > PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be true, and > then > > follow_devmap_pmd()->get_dev_pagemap() which returns NULL and gup_fast() > backs off, > > in the end that would mean setting in stone that "if there is a huge devmap > page table entry for which we haven't registered any devmap struct pages > (get_dev_pagemap returns NULL), we should treat that as a "special" huge > page table entry". > > From what I can tell, all code calling get_dev_pagemap() already does that, > it's just a question of getting it accepted and formalizing it. Oh I thought that's already how it works, since I didn't spot anything else that would block gup_fast from falling over. I guess really would need some testcases to make sure direct i/o (that's the easiest to test) fails like we expect. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

3 years, 10 months

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