- Linaro-mm-sig - lists.linaro.org

Re: [Linaro-mm-sig] [PATCH] dma-buf: use wake_up_process() instead of wake_up_state()

by Christian König

Am 19.03.21 um 03:58 schrieb Wang Qing: > Using wake_up_process() is more simpler and friendly, > and it is more convenient for analysis and statistics > > Signed-off-by: Wang Qing <wangqing(a)vivo.com> Reviewed-by: Christian König <christian.koenig(a)amd.com> Should I pick it up or do you want to push it through some other tree than DRM? Thanks, Christian. > --- > drivers/dma-buf/dma-fence.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c > index 7475e09..de51326 > --- a/drivers/dma-buf/dma-fence.c > +++ b/drivers/dma-buf/dma-fence.c > @@ -655,7 +655,7 @@ dma_fence_default_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb) > struct default_wait_cb *wait = > container_of(cb, struct default_wait_cb, base); > > - wake_up_state(wait->task, TASK_NORMAL); > + wake_up_process(wait->task); > } > > /**

4 years, 2 months

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Re: [Linaro-mm-sig] [PATCH] drm/i915/gt: A typo fix

by Randy Dunlap

On 3/18/21 3:19 AM, Bhaskar Chowdhury wrote: > > s/bariers/barriers/ > > Signed-off-by: Bhaskar Chowdhury <unixbhaskar(a)gmail.com> Acked-by: Randy Dunlap <rdunlap(a)infradead.org> > --- > drivers/gpu/drm/i915/gt/intel_timeline.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c > index 037b0e3ccbed..25fc7f44fee0 100644 > --- a/drivers/gpu/drm/i915/gt/intel_timeline.c > +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c > @@ -435,7 +435,7 @@ void intel_timeline_exit(struct intel_timeline *tl) > spin_unlock(&timelines->lock); > > /* > - * Since this timeline is idle, all bariers upon which we were waiting > + * Since this timeline is idle, all barriers upon which we were waiting > * must also be complete and so we can discard the last used barriers > * without loss of information. > */ > -- > 2.26.2 > -- ~Randy

4 years, 2 months

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Re: [Linaro-mm-sig] [PATCH 3/3] RFC: dma-buf: Add an API for importing and exporting sync files (v5)

by Daniel Vetter

On Wed, Sep 30, 2020 at 11:39:06AM +0200, Michel Dänzer wrote: > On 2020-03-17 10:21 p.m., Jason Ekstrand wrote: > > Explicit synchronization is the future. At least, that seems to be what > > most userspace APIs are agreeing on at this point. However, most of our > > Linux APIs (both userspace and kernel UAPI) are currently built around > > implicit synchronization with dma-buf. While work is ongoing to change > > many of the userspace APIs and protocols to an explicit synchronization > > model, switching over piecemeal is difficult due to the number of > > potential components involved. On the kernel side, many drivers use > > dma-buf including GPU (3D/compute), display, v4l, and others. In > > userspace, we have X11, several Wayland compositors, 3D drivers, compute > > drivers (OpenCL etc.), media encode/decode, and the list goes on. > > > > This patch provides a path forward by allowing userspace to manually > > manage the fences attached to a dma-buf. Alternatively, one can think > > of this as making dma-buf's implicit synchronization simply a carrier > > for an explicit fence. This is accomplished by adding two IOCTLs to > > dma-buf for importing and exporting a sync file to/from the dma-buf. > > This way a userspace component which is uses explicit synchronization, > > such as a Vulkan driver, can manually set the write fence on a buffer > > before handing it off to an implicitly synchronized component such as a > > Wayland compositor or video encoder. In this way, each of the different > > components can be upgraded to an explicit synchronization model one at a > > time as long as the userspace pieces connecting them are aware of it and > > import/export fences at the right times. > > > > There is a potential race condition with this API if userspace is not > > careful. A typical use case for implicit synchronization is to wait for > > the dma-buf to be ready, use it, and then signal it for some other > > component. Because a sync_file cannot be created until it is guaranteed > > to complete in finite time, userspace can only signal the dma-buf after > > it has already submitted the work which uses it to the kernel and has > > received a sync_file back. There is no way to atomically submit a > > wait-use-signal operation. This is not, however, really a problem with > > this API so much as it is a problem with explicit synchronization > > itself. The way this is typically handled is to have very explicit > > ownership transfer points in the API or protocol which ensure that only > > one component is using it at any given time. Both X11 (via the PRESENT > > extension) and Wayland provide such ownership transfer points via > > explicit present and idle messages. > > > > The decision was intentionally made in this patch to make the import and > > export operations IOCTLs on the dma-buf itself rather than as a DRM > > IOCTL. This makes it the import/export operation universal across all > > components which use dma-buf including GPU, display, v4l, and others. > > It also means that a userspace component can do the import/export > > without access to the DRM fd which may be tricky to get in cases where > > the client communicates with DRM via a userspace API such as OpenGL or > > Vulkan. At a future date we may choose to add direct import/export APIs > > to components such as drm_syncobj to avoid allocating a file descriptor > > and going through two ioctls. However, that seems to be something of a > > micro-optimization as import/export operations are likely to happen at a > > rate of a few per frame of rendered or decoded video. > > > > v2 (Jason Ekstrand): > > - Use a wrapper dma_fence_array of all fences including the new one > > when importing an exclusive fence. > > > > v3 (Jason Ekstrand): > > - Lock around setting shared fences as well as exclusive > > - Mark SIGNAL_SYNC_FILE as a read-write ioctl. > > - Initialize ret to 0 in dma_buf_wait_sync_file > > > > v4 (Jason Ekstrand): > > - Use the new dma_resv_get_singleton helper > > > > v5 (Jason Ekstrand): > > - Rename the IOCTLs to import/export rather than wait/signal > > - Drop the WRITE flag and always get/set the exclusive fence > > > > Signed-off-by: Jason Ekstrand <jason(a)jlekstrand.net> > > What's the status of this? DMA_BUF_IOCTL_EXPORT_SYNC_FILE would be useful > for Wayland compositors to wait for client buffers to become ready without > being prone to getting delayed by later HW access to them, so it would be > nice to merge that at least (if DMA_BUF_IOCTL_IMPORT_SYNC_FILE is still > controversial). I think the missing bits are just the usual stuff - igt testcases - userspace using the new ioctls - review of the entire pile I don't think there's any fundamental objections aside from "no one ever pushed this over the finish line". Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 2 months

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[PATCH] dma-fence: Document recoverable page fault implications

by Daniel Vetter

Recently there was a fairly long thread about recoreable hardware page faults, how they can deadlock, and what to do about that. While the discussion is still fresh I figured good time to try and document the conclusions a bit. This documentation section explains what's the potential problem, and the remedies we've discussed, roughly ordered from best to worst. v2: Linus -> Linux typoe (Dave) v3: - Make it clear drivers only need to implement one option (Christian) - Make it clearer that implicit sync is out the window with exclusive fences (Christian) - Add the fairly theoretical option of segementing the memory (either statically or through dynamic checks at runtime for which piece of memory is managed how) and explain why it's not a great idea (Felix) References: https://lore.kernel.org/dri-devel/20210107030127.20393-1-Felix.Kuehling@amd… Cc: Dave Airlie <airlied(a)gmail.com> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Thomas Hellström <thomas.hellstrom(a)intel.com> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: Jerome Glisse <jglisse(a)redhat.com> Cc: Felix Kuehling <felix.kuehling(a)amd.com> Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org --- Documentation/driver-api/dma-buf.rst | 76 ++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst index a2133d69872c..7f37ec30d9fd 100644 --- a/Documentation/driver-api/dma-buf.rst +++ b/Documentation/driver-api/dma-buf.rst @@ -257,3 +257,79 @@ fences in the kernel. This means: userspace is allowed to use userspace fencing or long running compute workloads. This also means no implicit fencing for shared buffers in these cases. + +Recoverable Hardware Page Faults Implications +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Modern hardware supports recoverable page faults, which has a lot of +implications for DMA fences. + +First, a pending page fault obviously holds up the work that's running on the +accelerator and a memory allocation is usually required to resolve the fault. +But memory allocations are not allowed to gate completion of DMA fences, which +means any workload using recoverable page faults cannot use DMA fences for +synchronization. Synchronization fences controlled by userspace must be used +instead. + +On GPUs this poses a problem, because current desktop compositor protocols on +Linux rely on DMA fences, which means without an entirely new userspace stack +built on top of userspace fences, they cannot benefit from recoverable page +faults. Specifically this means implicit synchronization will not be possible. +The exception is when page faults are only used as migration hints and never to +on-demand fill a memory request. For now this means recoverable page +faults on GPUs are limited to pure compute workloads. + +Furthermore GPUs usually have shared resources between the 3D rendering and +compute side, like compute units or command submission engines. If both a 3D +job with a DMA fence and a compute workload using recoverable page faults are +pending they could deadlock: + +- The 3D workload might need to wait for the compute job to finish and release + hardware resources first. + +- The compute workload might be stuck in a page fault, because the memory + allocation is waiting for the DMA fence of the 3D workload to complete. + +There are a few options to prevent this problem, one of which drivers need to +ensure: + +- Compute workloads can always be preempted, even when a page fault is pending + and not yet repaired. Not all hardware supports this. + +- DMA fence workloads and workloads which need page fault handling have + independent hardware resources to guarantee forward progress. This could be + achieved through e.g. through dedicated engines and minimal compute unit + reservations for DMA fence workloads. + +- The reservation approach could be further refined by only reserving the + hardware resources for DMA fence workloads when they are in-flight. This must + cover the time from when the DMA fence is visible to other threads up to + moment when fence is completed through dma_fence_signal(). + +- As a last resort, if the hardware provides no useful reservation mechanics, + all workloads must be flushed from the GPU when switching between jobs + requiring DMA fences or jobs requiring page fault handling: This means all DMA + fences must complete before a compute job with page fault handling can be + inserted into the scheduler queue. And vice versa, before a DMA fence can be + made visible anywhere in the system, all compute workloads must be preempted + to guarantee all pending GPU page faults are flushed. + +- Only a fairly theoretical option would be to untangle these dependencies when + allocating memory to repair hardware page faults, either through separate + memory blocks or runtime tracking of the full dependency graph of all DMA + fences. This results very wide impact on the kernel, since resolving the page + on the CPU side can itself involve a page fault. It is much more feasible and + robust to limit the impact of handling hardware page faults to the specific + driver. + +Note that workloads that run on independent hardware like copy engines or other +GPUs do not have any impact. This allows us to keep using DMA fences internally +in the kernel even for resolving hardware page faults, e.g. by using copy +engines to clear or copy memory needed to resolve the page fault. + +In some ways this page fault problem is a special case of the `Infinite DMA +Fences` discussions: Infinite fences from compute workloads are allowed to +depend on DMA fences, but not the other way around. And not even the page fault +problem is new, because some other CPU thread in userspace might +hit a page fault which holds up a userspace fence - supporting page faults on +GPUs doesn't anything fundamentally new. -- 2.30.0

4 years, 2 months

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Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Thu, Mar 11, 2021 at 2:12 PM Thomas Hellström (Intel) <thomas_os(a)shipmail.org> wrote: > > Hi! > > On 3/11/21 2:00 PM, Daniel Vetter wrote: > > On Thu, Mar 11, 2021 at 11:22:06AM +0100, Thomas Hellström (Intel) wrote: > >> On 3/1/21 3:09 PM, Daniel Vetter wrote: > >>> On Mon, Mar 1, 2021 at 11:17 AM Christian König > >>> <christian.koenig(a)amd.com> wrote: > >>>> > >>>> Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): > >>>>> On 3/1/21 10:05 AM, Daniel Vetter wrote: > >>>>>> On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) > >>>>>> wrote: > >>>>>>> Hi, > >>>>>>> > >>>>>>> On 3/1/21 9:28 AM, Daniel Vetter wrote: > >>>>>>>> On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > >>>>>>>> <thomas_os(a)shipmail.org> wrote: > >>>>>>>>> On 2/26/21 2:28 PM, Daniel Vetter wrote: > >>>>>>>>>> So I think it stops gup. But I haven't verified at all. Would be > >>>>>>>>>> good > >>>>>>>>>> if Christian can check this with some direct io to a buffer in > >>>>>>>>>> system > >>>>>>>>>> memory. > >>>>>>>>> Hmm, > >>>>>>>>> > >>>>>>>>> Docs (again vm_normal_page() say) > >>>>>>>>> > >>>>>>>>> * VM_MIXEDMAP mappings can likewise contain memory with or > >>>>>>>>> without "struct > >>>>>>>>> * page" backing, however the difference is that _all_ pages > >>>>>>>>> with a struct > >>>>>>>>> * page (that is, those where pfn_valid is true) are refcounted > >>>>>>>>> and > >>>>>>>>> considered > >>>>>>>>> * normal pages by the VM. The disadvantage is that pages are > >>>>>>>>> refcounted > >>>>>>>>> * (which can be slower and simply not an option for some PFNMAP > >>>>>>>>> users). The > >>>>>>>>> * advantage is that we don't have to follow the strict > >>>>>>>>> linearity rule of > >>>>>>>>> * PFNMAP mappings in order to support COWable mappings. > >>>>>>>>> > >>>>>>>>> but it's true __vm_insert_mixed() ends up in the insert_pfn() > >>>>>>>>> path, so > >>>>>>>>> the above isn't really true, which makes me wonder if and in that > >>>>>>>>> case > >>>>>>>>> why there could any longer ever be a significant performance > >>>>>>>>> difference > >>>>>>>>> between MIXEDMAP and PFNMAP. > >>>>>>>> Yeah it's definitely confusing. I guess I'll hack up a patch and see > >>>>>>>> what sticks. > >>>>>>>> > >>>>>>>>> BTW regarding the TTM hugeptes, I don't think we ever landed that > >>>>>>>>> devmap > >>>>>>>>> hack, so they are (for the non-gup case) relying on > >>>>>>>>> vma_is_special_huge(). For the gup case, I think the bug is still > >>>>>>>>> there. > >>>>>>>> Maybe there's another devmap hack, but the ttm_vm_insert functions do > >>>>>>>> use PFN_DEV and all that. And I think that stops gup_fast from trying > >>>>>>>> to find the underlying page. > >>>>>>>> -Daniel > >>>>>>> Hmm perhaps it might, but I don't think so. The fix I tried out was > >>>>>>> to set > >>>>>>> > >>>>>>> PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be > >>>>>>> true, and > >>>>>>> then > >>>>>>> > >>>>>>> follow_devmap_pmd()->get_dev_pagemap() which returns NULL and > >>>>>>> gup_fast() > >>>>>>> backs off, > >>>>>>> > >>>>>>> in the end that would mean setting in stone that "if there is a huge > >>>>>>> devmap > >>>>>>> page table entry for which we haven't registered any devmap struct > >>>>>>> pages > >>>>>>> (get_dev_pagemap returns NULL), we should treat that as a "special" > >>>>>>> huge > >>>>>>> page table entry". > >>>>>>> > >>>>>>> From what I can tell, all code calling get_dev_pagemap() already > >>>>>>> does that, > >>>>>>> it's just a question of getting it accepted and formalizing it. > >>>>>> Oh I thought that's already how it works, since I didn't spot anything > >>>>>> else that would block gup_fast from falling over. I guess really would > >>>>>> need some testcases to make sure direct i/o (that's the easiest to test) > >>>>>> fails like we expect. > >>>>> Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. > >>>>> Otherwise pmd_devmap() will not return true and since there is no > >>>>> pmd_special() things break. > >>>> Is that maybe the issue we have seen with amdgpu and huge pages? > >>> Yeah, essentially when you have a hugepte inserted by ttm, and it > >>> happens to point at system memory, then gup will work on that. And > >>> create all kinds of havoc. > >>> > >>>> Apart from that I'm lost guys, that devmap and gup stuff is not > >>>> something I have a good knowledge of apart from a one mile high view. > >>> I'm not really better, hence would be good to do a testcase and see. > >>> This should provoke it: > >>> - allocate nicely aligned bo in system memory > >>> - mmap, again nicely aligned to 2M > >>> - do some direct io from a filesystem into that mmap, that should trigger gup > >>> - before the gup completes free the mmap and bo so that ttm recycles > >>> the pages, which should trip up on the elevated refcount. If you wait > >>> until the direct io is completely, then I think nothing bad can be > >>> observed. > >>> > >>> Ofc if your amdgpu+hugepte issue is something else, then maybe we have > >>> another issue. > >>> > >>> Also usual caveat: I'm not an mm hacker either, so might be completely wrong. > >>> -Daniel > >> So I did the following quick experiment on vmwgfx, and it turns out that > >> with it, > >> fast gup never succeeds. Without the "| PFN_MAP", it typically succeeds > >> > >> I should probably craft an RFC formalizing this. > > Yeah I think that would be good. Maybe even more formalized if we also > > switch over to VM_PFNMAP, since afaiui these pte flags here only stop the > > fast gup path. And slow gup can still peak through VM_MIXEDMAP. Or > > something like that. > > > > Otoh your description of when it only sometimes succeeds would indicate my > > understanding of VM_PFNMAP vs VM_MIXEDMAP is wrong here. > > My understanding from reading the vmf_insert_mixed() code is that iff > the arch has pte_special(), VM_MIXEDMAP should be harmless. But that's > not consistent with the vm_normal_page() doc. For architectures without > pte_special, VM_PFNMAP must be used, and then we must also block COW > mappings. > > If we can get someone can commit to verify that the potential PAT WC > performance issue is gone with PFNMAP, I can put together a series with > that included. Iirc when I checked there's not much archs without pte_special, so I guess that's why we luck out. Hopefully. > As for existing userspace using COW TTM mappings, I once had a couple of > test cases to verify that it actually worked, in particular together > with huge PMDs and PUDs where breaking COW would imply splitting those, > but I can't think of anything else actually wanting to do that other > than by mistake. Yeah disallowing MAP_PRIVATE mappings would be another good thing to lock down. Really doesn't make much sense. -Daniel > /Thomas > > > > > > Christian, what's your take? > > -Daniel > > > >> /Thomas > >> > >> diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c > >> b/drivers/gpu/drm/ttm/ttm_bo_vm.c > >> index 6dc96cf66744..72b6fb17c984 100644 > >> --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c > >> +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c > >> @@ -195,6 +195,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > >> *vmf, > >> pfn_t pfnt; > >> struct ttm_tt *ttm = bo->ttm; > >> bool write = vmf->flags & FAULT_FLAG_WRITE; > >> + struct dev_pagemap *pagemap; > >> > >> /* Fault should not cross bo boundary. */ > >> page_offset &= ~(fault_page_size - 1); > >> @@ -210,6 +211,17 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > >> *vmf, > >> if ((pfn & (fault_page_size - 1)) != 0) > >> goto out_fallback; > >> > >> + /* > >> + * Huge entries must be special, that is marking them as devmap > >> + * with no backing device map range. If there is a backing > >> + * range, Don't insert a huge entry. > >> + */ > >> + pagemap = get_dev_pagemap(pfn, NULL); > >> + if (pagemap) { > >> + put_dev_pagemap(pagemap); > >> + goto out_fallback; > >> + } > >> + > >> /* Check that memory is contiguous. */ > >> if (!bo->mem.bus.is_iomem) { > >> for (i = 1; i < fault_page_size; ++i) { > >> @@ -223,7 +235,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > >> *vmf, > >> } > >> } > >> > >> - pfnt = __pfn_to_pfn_t(pfn, PFN_DEV); > >> + pfnt = __pfn_to_pfn_t(pfn, PFN_DEV | PFN_MAP); > >> if (fault_page_size == (HPAGE_PMD_SIZE >> PAGE_SHIFT)) > >> ret = vmf_insert_pfn_pmd_prot(vmf, pfnt, pgprot, write); > >> #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD > >> @@ -236,6 +248,21 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > >> *vmf, > >> if (ret != VM_FAULT_NOPAGE) > >> goto out_fallback; > >> > >> +#if 1 > >> + { > >> + int npages; > >> + struct page *page; > >> + > >> + npages = get_user_pages_fast_only(vmf->address, 1, 0, > >> &page); > >> + if (npages == 1) { > >> + DRM_WARN("Fast gup succeeded. Bad.\n"); > >> + put_page(page); > >> + } else { > >> + DRM_INFO("Fast gup failed. Good.\n"); > >> + } > >> + } > >> +#endif > >> + > >> return VM_FAULT_NOPAGE; > >> out_fallback: > >> count_vm_event(THP_FAULT_FALLBACK); > >> > >> > >> > >> > >> -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 2 months

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Re: [Linaro-mm-sig] [PATCH]] drm/amdgpu/gfx9: add gfxoff quirk

by Alex Deucher

On Thu, Mar 11, 2021 at 10:02 AM Alexandre Desnoyers <alex(a)qtec.com> wrote: > > On Thu, Mar 11, 2021 at 2:49 PM Daniel Gomez <daniel(a)qtec.com> wrote: > > > > On Thu, 11 Mar 2021 at 10:09, Daniel Gomez <daniel(a)qtec.com> wrote: > > > > > > On Wed, 10 Mar 2021 at 18:06, Alex Deucher <alexdeucher(a)gmail.com> wrote: > > > > > > > > On Wed, Mar 10, 2021 at 11:37 AM Daniel Gomez <daniel(a)qtec.com> wrote: > > > > > > > > > > Disabling GFXOFF via the quirk list fixes a hardware lockup in > > > > > Ryzen V1605B, RAVEN 0x1002:0x15DD rev 0x83. > > > > > > > > > > Signed-off-by: Daniel Gomez <daniel(a)qtec.com> > > > > > --- > > > > > > > > > > This patch is a continuation of the work here: > > > > > https://lkml.org/lkml/2021/2/3/122 where a hardware lockup was discussed and > > > > > a dma_fence deadlock was provoke as a side effect. To reproduce the issue > > > > > please refer to the above link. > > > > > > > > > > The hardware lockup was introduced in 5.6-rc1 for our particular revision as it > > > > > wasn't part of the new blacklist. Before that, in kernel v5.5, this hardware was > > > > > working fine without any hardware lock because the GFXOFF was actually disabled > > > > > by the if condition for the CHIP_RAVEN case. So this patch, adds the 'Radeon > > > > > Vega Mobile Series [1002:15dd] (rev 83)' to the blacklist to disable the GFXOFF. > > > > > > > > > > But besides the fix, I'd like to ask from where this revision comes from. Is it > > > > > an ASIC revision or is it hardcoded in the VBIOS from our vendor? From what I > > > > > can see, it comes from the ASIC and I wonder if somehow we can get an APU in the > > > > > future, 'not blacklisted', with the same problem. Then, should this table only > > > > > filter for the vendor and device and not the revision? Do you know if there are > > > > > any revisions for the 1002:15dd validated, tested and functional? > > > > > > > > The pci revision id (RID) is used to specify the specific SKU within a > > > > family. GFXOFF is supposed to be working on all raven variants. It > > > > was tested and functional on all reference platforms and any OEM > > > > platforms that launched with Linux support. There are a lot of > > > > dependencies on sbios in the early raven variants (0x15dd), so it's > > > > likely more of a specific platform issue, but there is not a good way > > > > to detect this so we use the DID/SSID/RID as a proxy. The newer raven > > > > variants (0x15d8) have much better GFXOFF support since they all > > > > shipped with newer firmware and sbios. > > > > > > We took one of the first reference platform boards to design our > > > custom board based on the V1605B and I assume it has one of the early 'unstable' > > > raven variants with RID 0x83. Also, as OEM we are in control of the bios > > > (provided by insyde) but I wasn't sure about the RID so, thanks for the > > > clarification. Is there anything we can do with the bios to have the GFXOFF > > > enabled and 'stable' for this particular revision? Otherwise we'd need to add > > > the 0x83 RID to the table. Also, there is an extra ']' in the patch > > > subject. Sorry > > > for that. Would you need a new patch in case you accept it with the ']' removed? > > > > > > Good to hear that the newer raven versions have better GFXOFF support. > > > > Adding Alex Desnoyer to the loop as he is the electronic/hardware and > > bios responsible so, he can > > provide more information about this. > > Hello everyone, > > We, Qtechnology, are the OEM of the hardware platform where we > originally discovered the bug. Our platform is based on the AMD > Dibbler V-1000 reference design, with the latest Insyde BIOS release > available for the (now unsupported) Dibbler platform. We have the > Insyde BIOS source code internally, so we can make some modifications > as needed. > > The last test that Daniel and myself performed was on a standard > Dibbler PCB rev.B1 motherboard (NOT our platform), and using the > corresponding latest AMD released BIOS "RDB1109GA". As Daniel wrote, > the hardware lockup can be reproduced on the Dibbler, even if it has a > different RID that our V1605B APU. > > We also have a Neousys Technology POC-515 embedded computer (V-1000, > V1605B) in our office. The Neousys PC also uses Insyde BIOS. This > computer is also locking-up in the test. > https://www.neousys-tech.com/en/product/application/rugged-embedded/poc-500… > > > Digging into the BIOS source code, the only reference to GFXOFF is in > the SMU and PSP firmware release notes, where some bug fixes have been > mentioned for previous SMU/PSP releases. After a quick "git grep -i > gfx | grep -i off", there seems to be no mention of GFXOFF in the > Insyde UEFI (inluding AMD PI) code base. I would appreciate any > information regarding BIOS modification needed to make the GFXOFF > feature stable. As you (Alex Deucher) mentionned, it should be > functional on all AMD Raven reference platforms. > It's handled by the firmwares carried by the sbios. I'm not sure what versions off hand. Probably want to make sure you have the latest ones. Do you have an AMD partner contact? It might be best to bring this up with them. Regarding the issues you are seeing is this a general issue with all workloads that use the GFX shader cores? Or just specific workloads? If it's just compute workloads, you might try this patch. It may fix the issue for you. Alex > > Regards, > > Alexandre Desnoyers > > > > > > I've now done a test on the reference platform (dibbler) with the > > latest bios available > > and the hw lockup can be also reproduced with the same steps. > > > > For reference, I'm using mainline kernel 5.12-rc2. > > > > [ 5.938544] [drm] initializing kernel modesetting (RAVEN > > 0x1002:0x15DD 0x1002:0x15DD 0xC1). > > [ 5.939942] amdgpu: ATOM BIOS: 113-RAVEN-11 > > > > As in the previous cases, the clocks go to 100% of usage when the hang occurs. > > > > However, when the gpu hangs, dmesg output displays the following: > > > > [ 1568.279847] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx > > timeout, signaled seq=188, emitted seq=191 > > [ 1568.434084] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process > > information: process Xorg pid 311 thread Xorg:cs0 pid 312 > > [ 1568.279847] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring gfx > > timeout, signaled seq=188, emitted seq=191 > > [ 1568.434084] [drm:amdgpu_job_timedout [amdgpu]] *ERROR* Process > > information: process Xorg pid 311 thread Xorg:cs0 pid 312 > > [ 1568.507000] amdgpu 0000:01:00.0: amdgpu: GPU reset begin! > > [ 1628.491882] rcu: INFO: rcu_sched self-detected stall on CPU > > [ 1628.491882] rcu: 3-...!: (665 ticks this GP) > > idle=f9a/1/0x4000000000000000 softirq=188533/188533 fqs=15 > > [ 1628.491882] rcu: rcu_sched kthread timer wakeup didn't happen for > > 58497 jiffies! g726761 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 > > [ 1628.491882] rcu: Possible timer handling issue on cpu=2 > > timer-softirq=55225 > > [ 1628.491882] rcu: rcu_sched kthread starved for 58500 jiffies! > > g726761 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x402 ->cpu=2 > > [ 1628.491882] rcu: Unless rcu_sched kthread gets sufficient CPU > > time, OOM is now expected behavior. > > [ 1628.491882] rcu: RCU grace-period kthread stack dump: > > [ 1628.491882] rcu: Stack dump where RCU GP kthread last ran: > > [ 1808.518445] rcu: INFO: rcu_sched self-detected stall on CPU > > [ 1808.518445] rcu: 3-...!: (2643 ticks this GP) > > idle=f9a/1/0x4000000000000000 softirq=188533/188533 fqs=15 > > [ 1808.518445] rcu: rcu_sched kthread starved for 238526 jiffies! > > g726761 f0x0 RCU_GP_WAIT_FQS(5) ->state=0x0 ->cpu=2 > > [ 1808.518445] rcu: Unless rcu_sched kthread gets sufficient CPU > > time, OOM is now expected behavior. > > [ 1808.518445] rcu: RCU grace-period kthread stack dump: > > [ 1808.518445] rcu: Stack dump where RCU GP kthread last ran: > > > > > > > > Daniel > > > > > > > > > > > Alex > > > > > > > > > > > > > > > > > > Logs: > > > > > [ 27.708348] [drm] initializing kernel modesetting (RAVEN > > > > > 0x1002:0x15DD 0x1002:0x15DD 0x83). > > > > > [ 27.789156] amdgpu: ATOM BIOS: 113-RAVEN-115 > > > > > > > > > > Thanks in advance, > > > > > Daniel > > > > > > > > > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ > > > > > 1 file changed, 2 insertions(+) > > > > > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > > > index 65db88bb6cbc..319d4b99aec8 100644 > > > > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > > > @@ -1243,6 +1243,8 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { > > > > > { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, > > > > > /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ > > > > > { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, > > > > > + /* GFXOFF provokes a hw lockup on 83 parts with a VBIOS 113-RAVEN-115 */ > > > > > + { 0x1002, 0x15dd, 0x1002, 0x15dd, 0x83 }, > > > > > { 0, 0, 0, 0, 0 }, > > > > > }; > > > > > > > > > > -- > > > > > 2.30.1 > > > > > > > > > > _______________________________________________ > > > > > dri-devel mailing list > > > > > dri-devel(a)lists.freedesktop.org > > > > > https://lists.freedesktop.org/mailman/listinfo/dri-devel

4 years, 2 months

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Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Thu, Mar 11, 2021 at 11:22:06AM +0100, Thomas Hellström (Intel) wrote: > > On 3/1/21 3:09 PM, Daniel Vetter wrote: > > On Mon, Mar 1, 2021 at 11:17 AM Christian König > > <christian.koenig(a)amd.com> wrote: > > > > > > > > > Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): > > > > On 3/1/21 10:05 AM, Daniel Vetter wrote: > > > > > On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) > > > > > wrote: > > > > > > Hi, > > > > > > > > > > > > On 3/1/21 9:28 AM, Daniel Vetter wrote: > > > > > > > On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > > > > > > > <thomas_os(a)shipmail.org> wrote: > > > > > > > > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > > > > > > > > So I think it stops gup. But I haven't verified at all. Would be > > > > > > > > > good > > > > > > > > > if Christian can check this with some direct io to a buffer in > > > > > > > > > system > > > > > > > > > memory. > > > > > > > > Hmm, > > > > > > > > > > > > > > > > Docs (again vm_normal_page() say) > > > > > > > > > > > > > > > > * VM_MIXEDMAP mappings can likewise contain memory with or > > > > > > > > without "struct > > > > > > > > * page" backing, however the difference is that _all_ pages > > > > > > > > with a struct > > > > > > > > * page (that is, those where pfn_valid is true) are refcounted > > > > > > > > and > > > > > > > > considered > > > > > > > > * normal pages by the VM. The disadvantage is that pages are > > > > > > > > refcounted > > > > > > > > * (which can be slower and simply not an option for some PFNMAP > > > > > > > > users). The > > > > > > > > * advantage is that we don't have to follow the strict > > > > > > > > linearity rule of > > > > > > > > * PFNMAP mappings in order to support COWable mappings. > > > > > > > > > > > > > > > > but it's true __vm_insert_mixed() ends up in the insert_pfn() > > > > > > > > path, so > > > > > > > > the above isn't really true, which makes me wonder if and in that > > > > > > > > case > > > > > > > > why there could any longer ever be a significant performance > > > > > > > > difference > > > > > > > > between MIXEDMAP and PFNMAP. > > > > > > > Yeah it's definitely confusing. I guess I'll hack up a patch and see > > > > > > > what sticks. > > > > > > > > > > > > > > > BTW regarding the TTM hugeptes, I don't think we ever landed that > > > > > > > > devmap > > > > > > > > hack, so they are (for the non-gup case) relying on > > > > > > > > vma_is_special_huge(). For the gup case, I think the bug is still > > > > > > > > there. > > > > > > > Maybe there's another devmap hack, but the ttm_vm_insert functions do > > > > > > > use PFN_DEV and all that. And I think that stops gup_fast from trying > > > > > > > to find the underlying page. > > > > > > > -Daniel > > > > > > Hmm perhaps it might, but I don't think so. The fix I tried out was > > > > > > to set > > > > > > > > > > > > PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be > > > > > > true, and > > > > > > then > > > > > > > > > > > > follow_devmap_pmd()->get_dev_pagemap() which returns NULL and > > > > > > gup_fast() > > > > > > backs off, > > > > > > > > > > > > in the end that would mean setting in stone that "if there is a huge > > > > > > devmap > > > > > > page table entry for which we haven't registered any devmap struct > > > > > > pages > > > > > > (get_dev_pagemap returns NULL), we should treat that as a "special" > > > > > > huge > > > > > > page table entry". > > > > > > > > > > > > From what I can tell, all code calling get_dev_pagemap() already > > > > > > does that, > > > > > > it's just a question of getting it accepted and formalizing it. > > > > > Oh I thought that's already how it works, since I didn't spot anything > > > > > else that would block gup_fast from falling over. I guess really would > > > > > need some testcases to make sure direct i/o (that's the easiest to test) > > > > > fails like we expect. > > > > Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. > > > > Otherwise pmd_devmap() will not return true and since there is no > > > > pmd_special() things break. > > > Is that maybe the issue we have seen with amdgpu and huge pages? > > Yeah, essentially when you have a hugepte inserted by ttm, and it > > happens to point at system memory, then gup will work on that. And > > create all kinds of havoc. > > > > > Apart from that I'm lost guys, that devmap and gup stuff is not > > > something I have a good knowledge of apart from a one mile high view. > > I'm not really better, hence would be good to do a testcase and see. > > This should provoke it: > > - allocate nicely aligned bo in system memory > > - mmap, again nicely aligned to 2M > > - do some direct io from a filesystem into that mmap, that should trigger gup > > - before the gup completes free the mmap and bo so that ttm recycles > > the pages, which should trip up on the elevated refcount. If you wait > > until the direct io is completely, then I think nothing bad can be > > observed. > > > > Ofc if your amdgpu+hugepte issue is something else, then maybe we have > > another issue. > > > > Also usual caveat: I'm not an mm hacker either, so might be completely wrong. > > -Daniel > > So I did the following quick experiment on vmwgfx, and it turns out that > with it, > fast gup never succeeds. Without the "| PFN_MAP", it typically succeeds > > I should probably craft an RFC formalizing this. Yeah I think that would be good. Maybe even more formalized if we also switch over to VM_PFNMAP, since afaiui these pte flags here only stop the fast gup path. And slow gup can still peak through VM_MIXEDMAP. Or something like that. Otoh your description of when it only sometimes succeeds would indicate my understanding of VM_PFNMAP vs VM_MIXEDMAP is wrong here. Christian, what's your take? -Daniel > > /Thomas > > diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c > b/drivers/gpu/drm/ttm/ttm_bo_vm.c > index 6dc96cf66744..72b6fb17c984 100644 > --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c > +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c > @@ -195,6 +195,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > *vmf, > pfn_t pfnt; > struct ttm_tt *ttm = bo->ttm; > bool write = vmf->flags & FAULT_FLAG_WRITE; > + struct dev_pagemap *pagemap; > > /* Fault should not cross bo boundary. */ > page_offset &= ~(fault_page_size - 1); > @@ -210,6 +211,17 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > *vmf, > if ((pfn & (fault_page_size - 1)) != 0) > goto out_fallback; > > + /* > + * Huge entries must be special, that is marking them as devmap > + * with no backing device map range. If there is a backing > + * range, Don't insert a huge entry. > + */ > + pagemap = get_dev_pagemap(pfn, NULL); > + if (pagemap) { > + put_dev_pagemap(pagemap); > + goto out_fallback; > + } > + > /* Check that memory is contiguous. */ > if (!bo->mem.bus.is_iomem) { > for (i = 1; i < fault_page_size; ++i) { > @@ -223,7 +235,7 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > *vmf, > } > } > > - pfnt = __pfn_to_pfn_t(pfn, PFN_DEV); > + pfnt = __pfn_to_pfn_t(pfn, PFN_DEV | PFN_MAP); > if (fault_page_size == (HPAGE_PMD_SIZE >> PAGE_SHIFT)) > ret = vmf_insert_pfn_pmd_prot(vmf, pfnt, pgprot, write); > #ifdef CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD > @@ -236,6 +248,21 @@ static vm_fault_t ttm_bo_vm_insert_huge(struct vm_fault > *vmf, > if (ret != VM_FAULT_NOPAGE) > goto out_fallback; > > +#if 1 > + { > + int npages; > + struct page *page; > + > + npages = get_user_pages_fast_only(vmf->address, 1, 0, > &page); > + if (npages == 1) { > + DRM_WARN("Fast gup succeeded. Bad.\n"); > + put_page(page); > + } else { > + DRM_INFO("Fast gup failed. Good.\n"); > + } > + } > +#endif > + > return VM_FAULT_NOPAGE; > out_fallback: > count_vm_event(THP_FAULT_FALLBACK); > > > > > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 2 months

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Re: [Linaro-mm-sig] [PATCH]] drm/amdgpu/gfx9: add gfxoff quirk

by Alex Deucher

On Wed, Mar 10, 2021 at 11:37 AM Daniel Gomez <daniel(a)qtec.com> wrote: > > Disabling GFXOFF via the quirk list fixes a hardware lockup in > Ryzen V1605B, RAVEN 0x1002:0x15DD rev 0x83. > > Signed-off-by: Daniel Gomez <daniel(a)qtec.com> > --- > > This patch is a continuation of the work here: > https://lkml.org/lkml/2021/2/3/122 where a hardware lockup was discussed and > a dma_fence deadlock was provoke as a side effect. To reproduce the issue > please refer to the above link. > > The hardware lockup was introduced in 5.6-rc1 for our particular revision as it > wasn't part of the new blacklist. Before that, in kernel v5.5, this hardware was > working fine without any hardware lock because the GFXOFF was actually disabled > by the if condition for the CHIP_RAVEN case. So this patch, adds the 'Radeon > Vega Mobile Series [1002:15dd] (rev 83)' to the blacklist to disable the GFXOFF. > > But besides the fix, I'd like to ask from where this revision comes from. Is it > an ASIC revision or is it hardcoded in the VBIOS from our vendor? From what I > can see, it comes from the ASIC and I wonder if somehow we can get an APU in the > future, 'not blacklisted', with the same problem. Then, should this table only > filter for the vendor and device and not the revision? Do you know if there are > any revisions for the 1002:15dd validated, tested and functional? The pci revision id (RID) is used to specify the specific SKU within a family. GFXOFF is supposed to be working on all raven variants. It was tested and functional on all reference platforms and any OEM platforms that launched with Linux support. There are a lot of dependencies on sbios in the early raven variants (0x15dd), so it's likely more of a specific platform issue, but there is not a good way to detect this so we use the DID/SSID/RID as a proxy. The newer raven variants (0x15d8) have much better GFXOFF support since they all shipped with newer firmware and sbios. Alex > > Logs: > [ 27.708348] [drm] initializing kernel modesetting (RAVEN > 0x1002:0x15DD 0x1002:0x15DD 0x83). > [ 27.789156] amdgpu: ATOM BIOS: 113-RAVEN-115 > > Thanks in advance, > Daniel > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 65db88bb6cbc..319d4b99aec8 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -1243,6 +1243,8 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { > { 0x1002, 0x15dd, 0x103c, 0x83e7, 0xd3 }, > /* GFXOFF is unstable on C6 parts with a VBIOS 113-RAVEN-114 */ > { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, > + /* GFXOFF provokes a hw lockup on 83 parts with a VBIOS 113-RAVEN-115 */ > + { 0x1002, 0x15dd, 0x1002, 0x15dd, 0x83 }, > { 0, 0, 0, 0, 0 }, > }; > > -- > 2.30.1 > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

4 years, 2 months

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Re: [Linaro-mm-sig] [PATCH] drm/amdgpu: Remove unnecessary conversion to bool

by Alex Deucher

On Sun, Mar 7, 2021 at 10:14 PM Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> wrote: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1600:40-45: WARNING: conversion > to bool not needed here. > > ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1598:40-45: WARNING: conversion > to bool not needed here. > > Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> > Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> This patch was already applied. Alex > --- > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > index 690a509..b39e7db 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > @@ -1595,9 +1595,9 @@ static int sdma_v5_2_set_clockgating_state(void *handle, > case CHIP_VANGOGH: > case CHIP_DIMGREY_CAVEFISH: > sdma_v5_2_update_medium_grain_clock_gating(adev, > - state == AMD_CG_STATE_GATE ? true : false); > + state == AMD_CG_STATE_GATE); > sdma_v5_2_update_medium_grain_light_sleep(adev, > - state == AMD_CG_STATE_GATE ? true : false); > + state == AMD_CG_STATE_GATE); > break; > default: > break; > -- > 1.8.3.1 > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH] drm/amdgpu: Remove unnecessary conversion to bool

by Alex Deucher

On Wed, Mar 3, 2021 at 4:18 AM Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> wrote: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c:2252:40-45: WARNING: conversion > to bool not needed here. > > Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> > Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > index c8c22c1..00d3773 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c > @@ -2249,7 +2249,7 @@ static int sdma_v4_0_set_powergating_state(void *handle, > case CHIP_RAVEN: > case CHIP_RENOIR: > sdma_v4_1_update_power_gating(adev, > - state == AMD_PG_STATE_GATE ? true : false); > + state == AMD_PG_STATE_GATE); > break; > default: > break; > -- > 1.8.3.1 > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Christian König

Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): > > On 3/1/21 10:05 AM, Daniel Vetter wrote: >> On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) >> wrote: >>> Hi, >>> >>> On 3/1/21 9:28 AM, Daniel Vetter wrote: >>>> On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) >>>> <thomas_os(a)shipmail.org> wrote: >>>>> On 2/26/21 2:28 PM, Daniel Vetter wrote: >>>>>> So I think it stops gup. But I haven't verified at all. Would be >>>>>> good >>>>>> if Christian can check this with some direct io to a buffer in >>>>>> system >>>>>> memory. >>>>> Hmm, >>>>> >>>>> Docs (again vm_normal_page() say) >>>>> >>>>> * VM_MIXEDMAP mappings can likewise contain memory with or >>>>> without "struct >>>>> * page" backing, however the difference is that _all_ pages >>>>> with a struct >>>>> * page (that is, those where pfn_valid is true) are refcounted >>>>> and >>>>> considered >>>>> * normal pages by the VM. The disadvantage is that pages are >>>>> refcounted >>>>> * (which can be slower and simply not an option for some PFNMAP >>>>> users). The >>>>> * advantage is that we don't have to follow the strict >>>>> linearity rule of >>>>> * PFNMAP mappings in order to support COWable mappings. >>>>> >>>>> but it's true __vm_insert_mixed() ends up in the insert_pfn() >>>>> path, so >>>>> the above isn't really true, which makes me wonder if and in that >>>>> case >>>>> why there could any longer ever be a significant performance >>>>> difference >>>>> between MIXEDMAP and PFNMAP. >>>> Yeah it's definitely confusing. I guess I'll hack up a patch and see >>>> what sticks. >>>> >>>>> BTW regarding the TTM hugeptes, I don't think we ever landed that >>>>> devmap >>>>> hack, so they are (for the non-gup case) relying on >>>>> vma_is_special_huge(). For the gup case, I think the bug is still >>>>> there. >>>> Maybe there's another devmap hack, but the ttm_vm_insert functions do >>>> use PFN_DEV and all that. And I think that stops gup_fast from trying >>>> to find the underlying page. >>>> -Daniel >>> Hmm perhaps it might, but I don't think so. The fix I tried out was >>> to set >>> >>> PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be >>> true, and >>> then >>> >>> follow_devmap_pmd()->get_dev_pagemap() which returns NULL and >>> gup_fast() >>> backs off, >>> >>> in the end that would mean setting in stone that "if there is a huge >>> devmap >>> page table entry for which we haven't registered any devmap struct >>> pages >>> (get_dev_pagemap returns NULL), we should treat that as a "special" >>> huge >>> page table entry". >>> >>> From what I can tell, all code calling get_dev_pagemap() already >>> does that, >>> it's just a question of getting it accepted and formalizing it. >> Oh I thought that's already how it works, since I didn't spot anything >> else that would block gup_fast from falling over. I guess really would >> need some testcases to make sure direct i/o (that's the easiest to test) >> fails like we expect. > > Yeah, IIRC the "| PFN_MAP" is the missing piece for TTM huge ptes. > Otherwise pmd_devmap() will not return true and since there is no > pmd_special() things break. Is that maybe the issue we have seen with amdgpu and huge pages? Apart from that I'm lost guys, that devmap and gup stuff is not something I have a good knowledge of apart from a one mile high view. Christian. > > /Thomas > > > >> -Daniel

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) wrote: > Hi, > > On 3/1/21 9:28 AM, Daniel Vetter wrote: > > On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > > <thomas_os(a)shipmail.org> wrote: > > > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > > > So I think it stops gup. But I haven't verified at all. Would be good > > > > if Christian can check this with some direct io to a buffer in system > > > > memory. > > > Hmm, > > > > > > Docs (again vm_normal_page() say) > > > > > > * VM_MIXEDMAP mappings can likewise contain memory with or without "struct > > > * page" backing, however the difference is that _all_ pages with a struct > > > * page (that is, those where pfn_valid is true) are refcounted and > > > considered > > > * normal pages by the VM. The disadvantage is that pages are refcounted > > > * (which can be slower and simply not an option for some PFNMAP > > > users). The > > > * advantage is that we don't have to follow the strict linearity rule of > > > * PFNMAP mappings in order to support COWable mappings. > > > > > > but it's true __vm_insert_mixed() ends up in the insert_pfn() path, so > > > the above isn't really true, which makes me wonder if and in that case > > > why there could any longer ever be a significant performance difference > > > between MIXEDMAP and PFNMAP. > > Yeah it's definitely confusing. I guess I'll hack up a patch and see > > what sticks. > > > > > BTW regarding the TTM hugeptes, I don't think we ever landed that devmap > > > hack, so they are (for the non-gup case) relying on > > > vma_is_special_huge(). For the gup case, I think the bug is still there. > > Maybe there's another devmap hack, but the ttm_vm_insert functions do > > use PFN_DEV and all that. And I think that stops gup_fast from trying > > to find the underlying page. > > -Daniel > > Hmm perhaps it might, but I don't think so. The fix I tried out was to set > > PFN_DEV | PFN_MAP for huge PTEs which causes pfn_devmap() to be true, and > then > > follow_devmap_pmd()->get_dev_pagemap() which returns NULL and gup_fast() > backs off, > > in the end that would mean setting in stone that "if there is a huge devmap > page table entry for which we haven't registered any devmap struct pages > (get_dev_pagemap returns NULL), we should treat that as a "special" huge > page table entry". > > From what I can tell, all code calling get_dev_pagemap() already does that, > it's just a question of getting it accepted and formalizing it. Oh I thought that's already how it works, since I didn't spot anything else that would block gup_fast from falling over. I guess really would need some testcases to make sure direct i/o (that's the easiest to test) fails like we expect. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) <thomas_os(a)shipmail.org> wrote: > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > So I think it stops gup. But I haven't verified at all. Would be good > > if Christian can check this with some direct io to a buffer in system > > memory. > > Hmm, > > Docs (again vm_normal_page() say) > > * VM_MIXEDMAP mappings can likewise contain memory with or without "struct > * page" backing, however the difference is that _all_ pages with a struct > * page (that is, those where pfn_valid is true) are refcounted and > considered > * normal pages by the VM. The disadvantage is that pages are refcounted > * (which can be slower and simply not an option for some PFNMAP > users). The > * advantage is that we don't have to follow the strict linearity rule of > * PFNMAP mappings in order to support COWable mappings. > > but it's true __vm_insert_mixed() ends up in the insert_pfn() path, so > the above isn't really true, which makes me wonder if and in that case > why there could any longer ever be a significant performance difference > between MIXEDMAP and PFNMAP. Yeah it's definitely confusing. I guess I'll hack up a patch and see what sticks. > BTW regarding the TTM hugeptes, I don't think we ever landed that devmap > hack, so they are (for the non-gup case) relying on > vma_is_special_huge(). For the gup case, I think the bug is still there. Maybe there's another devmap hack, but the ttm_vm_insert functions do use PFN_DEV and all that. And I think that stops gup_fast from trying to find the underlying page. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Fri, Feb 26, 2021 at 10:41 AM Thomas Hellström (Intel) <thomas_os(a)shipmail.org> wrote: > > > On 2/25/21 4:49 PM, Daniel Vetter wrote: > > On Thu, Feb 25, 2021 at 11:44 AM Daniel Vetter <daniel(a)ffwll.ch> wrote: > >> On Thu, Feb 25, 2021 at 11:28:31AM +0100, Christian König wrote: > >>> Am 24.02.21 um 10:31 schrieb Daniel Vetter: > >>>> On Wed, Feb 24, 2021 at 10:16 AM Thomas Hellström (Intel) > >>>> <thomas_os(a)shipmail.org> wrote: > >>>>> On 2/24/21 9:45 AM, Daniel Vetter wrote: > >>>>>> On Wed, Feb 24, 2021 at 8:46 AM Thomas Hellström (Intel) > >>>>>> <thomas_os(a)shipmail.org> wrote: > >>>>>>> On 2/23/21 11:59 AM, Daniel Vetter wrote: > >>>>>>>> tldr; DMA buffers aren't normal memory, expecting that you can use > >>>>>>>> them like that (like calling get_user_pages works, or that they're > >>>>>>>> accounting like any other normal memory) cannot be guaranteed. > >>>>>>>> > >>>>>>>> Since some userspace only runs on integrated devices, where all > >>>>>>>> buffers are actually all resident system memory, there's a huge > >>>>>>>> temptation to assume that a struct page is always present and useable > >>>>>>>> like for any more pagecache backed mmap. This has the potential to > >>>>>>>> result in a uapi nightmare. > >>>>>>>> > >>>>>>>> To stop this gap require that DMA buffer mmaps are VM_PFNMAP, which > >>>>>>>> blocks get_user_pages and all the other struct page based > >>>>>>>> infrastructure for everyone. In spirit this is the uapi counterpart to > >>>>>>>> the kernel-internal CONFIG_DMABUF_DEBUG. > >>>>>>>> > >>>>>>>> Motivated by a recent patch which wanted to swich the system dma-buf > >>>>>>>> heap to vm_insert_page instead of vm_insert_pfn. > >>>>>>>> > >>>>>>>> v2: > >>>>>>>> > >>>>>>>> Jason brought up that we also want to guarantee that all ptes have the > >>>>>>>> pte_special flag set, to catch fast get_user_pages (on architectures > >>>>>>>> that support this). Allowing VM_MIXEDMAP (like VM_SPECIAL does) would > >>>>>>>> still allow vm_insert_page, but limiting to VM_PFNMAP will catch that. > >>>>>>>> > >>>>>>>> From auditing the various functions to insert pfn pte entires > >>>>>>>> (vm_insert_pfn_prot, remap_pfn_range and all it's callers like > >>>>>>>> dma_mmap_wc) it looks like VM_PFNMAP is already required anyway, so > >>>>>>>> this should be the correct flag to check for. > >>>>>>>> > >>>>>>> If we require VM_PFNMAP, for ordinary page mappings, we also need to > >>>>>>> disallow COW mappings, since it will not work on architectures that > >>>>>>> don't have CONFIG_ARCH_HAS_PTE_SPECIAL, (see the docs for vm_normal_page()). > >>>>>> Hm I figured everyone just uses MAP_SHARED for buffer objects since > >>>>>> COW really makes absolutely no sense. How would we enforce this? > >>>>> Perhaps returning -EINVAL on is_cow_mapping() at mmap time. Either that > >>>>> or allowing MIXEDMAP. > >>>>> > >>>>>>> Also worth noting is the comment in ttm_bo_mmap_vma_setup() with > >>>>>>> possible performance implications with x86 + PAT + VM_PFNMAP + normal > >>>>>>> pages. That's a very old comment, though, and might not be valid anymore. > >>>>>> I think that's why ttm has a page cache for these, because it indeed > >>>>>> sucks. The PAT changes on pages are rather expensive. > >>>>> IIRC the page cache was implemented because of the slowness of the > >>>>> caching mode transition itself, more specifically the wbinvd() call + > >>>>> global TLB flush. > >>> Yes, exactly that. The global TLB flush is what really breaks our neck here > >>> from a performance perspective. > >>> > >>>>>> There is still an issue for iomem mappings, because the PAT validation > >>>>>> does a linear walk of the resource tree (lol) for every vm_insert_pfn. > >>>>>> But for i915 at least this is fixed by using the io_mapping > >>>>>> infrastructure, which does the PAT reservation only once when you set > >>>>>> up the mapping area at driver load. > >>>>> Yes, I guess that was the issue that the comment describes, but the > >>>>> issue wasn't there with vm_insert_mixed() + VM_MIXEDMAP. > >>>>> > >>>>>> Also TTM uses VM_PFNMAP right now for everything, so it can't be a > >>>>>> problem that hurts much :-) > >>>>> Hmm, both 5.11 and drm-tip appears to still use MIXEDMAP? > >>>>> > >>>>> https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/ttm/ttm_bo_v… > >>>> Uh that's bad, because mixed maps pointing at struct page wont stop > >>>> gup. At least afaik. > >>> Hui? I'm pretty sure MIXEDMAP stops gup as well. Otherwise we would have > >>> already seen tons of problems with the page cache. > >> On any architecture which has CONFIG_ARCH_HAS_PTE_SPECIAL vm_insert_mixed > >> boils down to vm_insert_pfn wrt gup. And special pte stops gup fast path. > >> > >> But if you don't have VM_IO or VM_PFNMAP set, then I'm not seeing how > >> you're stopping gup slow path. See check_vma_flags() in mm/gup.c. > >> > >> Also if you don't have CONFIG_ARCH_HAS_PTE_SPECIAL then I don't think > >> vm_insert_mixed even works on iomem pfns. There's the devmap exception, > >> but we're not devmap. Worse ttm abuses some accidental codepath to smuggle > >> in hugepte support by intentionally not being devmap. > >> > >> So I'm really not sure this works as we think it should. Maybe good to do > >> a quick test program on amdgpu with a buffer in system memory only and try > >> to do direct io into it. If it works, you have a problem, and a bad one. > > That's probably impossible, since a quick git grep shows that pretty > > much anything reasonable has special ptes: arc, arm, arm64, powerpc, > > riscv, s390, sh, sparc, x86. I don't think you'll have a platform > > where you can plug an amdgpu in and actually exercise the bug :-) > > Hm. AFAIK _insert_mixed() doesn't set PTE_SPECIAL on system pages, so I > don't see what should be stopping gup to those? If you have an arch with pte special we use insert_pfn(), which afaict will use pte_mkspecial for the !devmap case. And ttm isn't devmap (otherwise our hugepte abuse of devmap hugeptes would go rather wrong). So I think it stops gup. But I haven't verified at all. Would be good if Christian can check this with some direct io to a buffer in system memory. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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[PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

tldr; DMA buffers aren't normal memory, expecting that you can use them like that (like calling get_user_pages works, or that they're accounting like any other normal memory) cannot be guaranteed. Since some userspace only runs on integrated devices, where all buffers are actually all resident system memory, there's a huge temptation to assume that a struct page is always present and useable like for any more pagecache backed mmap. This has the potential to result in a uapi nightmare. To stop this gap require that DMA buffer mmaps are VM_PFNMAP, which blocks get_user_pages and all the other struct page based infrastructure for everyone. In spirit this is the uapi counterpart to the kernel-internal CONFIG_DMABUF_DEBUG. Motivated by a recent patch which wanted to swich the system dma-buf heap to vm_insert_page instead of vm_insert_pfn. v2: Jason brought up that we also want to guarantee that all ptes have the pte_special flag set, to catch fast get_user_pages (on architectures that support this). Allowing VM_MIXEDMAP (like VM_SPECIAL does) would still allow vm_insert_page, but limiting to VM_PFNMAP will catch that. >From auditing the various functions to insert pfn pte entires (vm_insert_pfn_prot, remap_pfn_range and all it's callers like dma_mmap_wc) it looks like VM_PFNMAP is already required anyway, so this should be the correct flag to check for. References: https://lore.kernel.org/lkml/CAKMK7uHi+mG0z0HUmNt13QCCvutuRVjpcR0NjRL12k-Wb… Acked-by: Christian König <christian.koenig(a)amd.com> Cc: Jason Gunthorpe <jgg(a)ziepe.ca> Cc: Suren Baghdasaryan <surenb(a)google.com> Cc: Matthew Wilcox <willy(a)infradead.org> Cc: John Stultz <john.stultz(a)linaro.org> Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org --- drivers/dma-buf/dma-buf.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index f264b70c383e..06cb1d2e9fdc 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -127,6 +127,7 @@ static struct file_system_type dma_buf_fs_type = { static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma) { struct dma_buf *dmabuf; + int ret; if (!is_dma_buf_file(file)) return -EINVAL; @@ -142,7 +143,11 @@ static int dma_buf_mmap_internal(struct file *file, struct vm_area_struct *vma) dmabuf->size >> PAGE_SHIFT) return -EINVAL; - return dmabuf->ops->mmap(dmabuf, vma); + ret = dmabuf->ops->mmap(dmabuf, vma); + + WARN_ON(!(vma->vm_flags & VM_PFNMAP)); + + return ret; } static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence) @@ -1244,6 +1249,8 @@ EXPORT_SYMBOL_GPL(dma_buf_end_cpu_access); int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma, unsigned long pgoff) { + int ret; + if (WARN_ON(!dmabuf || !vma)) return -EINVAL; @@ -1264,7 +1271,11 @@ int dma_buf_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma, vma_set_file(vma, dmabuf->file); vma->vm_pgoff = pgoff; - return dmabuf->ops->mmap(dmabuf, vma); + ret = dmabuf->ops->mmap(dmabuf, vma); + + WARN_ON(!(vma->vm_flags & VM_PFNMAP)); + + return ret; } EXPORT_SYMBOL_GPL(dma_buf_mmap); -- 2.30.0

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH] drm/amdgpu: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE

by Alex Deucher

On Thu, Feb 25, 2021 at 4:02 AM Yang Li <yang.lee(a)linux.alibaba.com> wrote: > > Fix the following coccicheck warning: > ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1589:0-23: WARNING: > fops_ib_preempt should be defined with DEFINE_DEBUGFS_ATTRIBUTE > ./drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1592:0-23: WARNING: > fops_sclk_set should be defined with DEFINE_DEBUGFS_ATTRIBUTE > > Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> > Signed-off-by: Yang Li <yang.lee(a)linux.alibaba.com> Applied. Thanks! Alex > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > index 0a25fec..52ef488 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c > @@ -1586,10 +1586,10 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) > return 0; > } > > -DEFINE_SIMPLE_ATTRIBUTE(fops_ib_preempt, NULL, > +DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL, > amdgpu_debugfs_ib_preempt, "%llu\n"); > > -DEFINE_SIMPLE_ATTRIBUTE(fops_sclk_set, NULL, > +DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL, > amdgpu_debugfs_sclk_set, "%llu\n"); > > int amdgpu_debugfs_init(struct amdgpu_device *adev) > -- > 1.8.3.1 > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Wed, Feb 24, 2021 at 10:16 AM Thomas Hellström (Intel) <thomas_os(a)shipmail.org> wrote: > > > On 2/24/21 9:45 AM, Daniel Vetter wrote: > > On Wed, Feb 24, 2021 at 8:46 AM Thomas Hellström (Intel) > > <thomas_os(a)shipmail.org> wrote: > >> > >> On 2/23/21 11:59 AM, Daniel Vetter wrote: > >>> tldr; DMA buffers aren't normal memory, expecting that you can use > >>> them like that (like calling get_user_pages works, or that they're > >>> accounting like any other normal memory) cannot be guaranteed. > >>> > >>> Since some userspace only runs on integrated devices, where all > >>> buffers are actually all resident system memory, there's a huge > >>> temptation to assume that a struct page is always present and useable > >>> like for any more pagecache backed mmap. This has the potential to > >>> result in a uapi nightmare. > >>> > >>> To stop this gap require that DMA buffer mmaps are VM_PFNMAP, which > >>> blocks get_user_pages and all the other struct page based > >>> infrastructure for everyone. In spirit this is the uapi counterpart to > >>> the kernel-internal CONFIG_DMABUF_DEBUG. > >>> > >>> Motivated by a recent patch which wanted to swich the system dma-buf > >>> heap to vm_insert_page instead of vm_insert_pfn. > >>> > >>> v2: > >>> > >>> Jason brought up that we also want to guarantee that all ptes have the > >>> pte_special flag set, to catch fast get_user_pages (on architectures > >>> that support this). Allowing VM_MIXEDMAP (like VM_SPECIAL does) would > >>> still allow vm_insert_page, but limiting to VM_PFNMAP will catch that. > >>> > >>> From auditing the various functions to insert pfn pte entires > >>> (vm_insert_pfn_prot, remap_pfn_range and all it's callers like > >>> dma_mmap_wc) it looks like VM_PFNMAP is already required anyway, so > >>> this should be the correct flag to check for. > >>> > >> If we require VM_PFNMAP, for ordinary page mappings, we also need to > >> disallow COW mappings, since it will not work on architectures that > >> don't have CONFIG_ARCH_HAS_PTE_SPECIAL, (see the docs for vm_normal_page()). > > Hm I figured everyone just uses MAP_SHARED for buffer objects since > > COW really makes absolutely no sense. How would we enforce this? > > Perhaps returning -EINVAL on is_cow_mapping() at mmap time. Either that > or allowing MIXEDMAP. > > >> Also worth noting is the comment in ttm_bo_mmap_vma_setup() with > >> possible performance implications with x86 + PAT + VM_PFNMAP + normal > >> pages. That's a very old comment, though, and might not be valid anymore. > > I think that's why ttm has a page cache for these, because it indeed > > sucks. The PAT changes on pages are rather expensive. > > IIRC the page cache was implemented because of the slowness of the > caching mode transition itself, more specifically the wbinvd() call + > global TLB flush. > > > > > There is still an issue for iomem mappings, because the PAT validation > > does a linear walk of the resource tree (lol) for every vm_insert_pfn. > > But for i915 at least this is fixed by using the io_mapping > > infrastructure, which does the PAT reservation only once when you set > > up the mapping area at driver load. > > Yes, I guess that was the issue that the comment describes, but the > issue wasn't there with vm_insert_mixed() + VM_MIXEDMAP. > > > > > Also TTM uses VM_PFNMAP right now for everything, so it can't be a > > problem that hurts much :-) > > Hmm, both 5.11 and drm-tip appears to still use MIXEDMAP? > > https://elixir.bootlin.com/linux/latest/source/drivers/gpu/drm/ttm/ttm_bo_v… Uh that's bad, because mixed maps pointing at struct page wont stop gup. At least afaik. Christian, do we need to patch this up, and maybe fix up ttm fault handler to use io_mapping so the vm_insert_pfn stuff is fast? -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

by Daniel Vetter

On Wed, Feb 24, 2021 at 8:46 AM Thomas Hellström (Intel) <thomas_os(a)shipmail.org> wrote: > > > On 2/23/21 11:59 AM, Daniel Vetter wrote: > > tldr; DMA buffers aren't normal memory, expecting that you can use > > them like that (like calling get_user_pages works, or that they're > > accounting like any other normal memory) cannot be guaranteed. > > > > Since some userspace only runs on integrated devices, where all > > buffers are actually all resident system memory, there's a huge > > temptation to assume that a struct page is always present and useable > > like for any more pagecache backed mmap. This has the potential to > > result in a uapi nightmare. > > > > To stop this gap require that DMA buffer mmaps are VM_PFNMAP, which > > blocks get_user_pages and all the other struct page based > > infrastructure for everyone. In spirit this is the uapi counterpart to > > the kernel-internal CONFIG_DMABUF_DEBUG. > > > > Motivated by a recent patch which wanted to swich the system dma-buf > > heap to vm_insert_page instead of vm_insert_pfn. > > > > v2: > > > > Jason brought up that we also want to guarantee that all ptes have the > > pte_special flag set, to catch fast get_user_pages (on architectures > > that support this). Allowing VM_MIXEDMAP (like VM_SPECIAL does) would > > still allow vm_insert_page, but limiting to VM_PFNMAP will catch that. > > > > From auditing the various functions to insert pfn pte entires > > (vm_insert_pfn_prot, remap_pfn_range and all it's callers like > > dma_mmap_wc) it looks like VM_PFNMAP is already required anyway, so > > this should be the correct flag to check for. > > > If we require VM_PFNMAP, for ordinary page mappings, we also need to > disallow COW mappings, since it will not work on architectures that > don't have CONFIG_ARCH_HAS_PTE_SPECIAL, (see the docs for vm_normal_page()). Hm I figured everyone just uses MAP_SHARED for buffer objects since COW really makes absolutely no sense. How would we enforce this? > Also worth noting is the comment in ttm_bo_mmap_vma_setup() with > possible performance implications with x86 + PAT + VM_PFNMAP + normal > pages. That's a very old comment, though, and might not be valid anymore. I think that's why ttm has a page cache for these, because it indeed sucks. The PAT changes on pages are rather expensive. There is still an issue for iomem mappings, because the PAT validation does a linear walk of the resource tree (lol) for every vm_insert_pfn. But for i915 at least this is fixed by using the io_mapping infrastructure, which does the PAT reservation only once when you set up the mapping area at driver load. Also TTM uses VM_PFNMAP right now for everything, so it can't be a problem that hurts much :-) -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH] dma-fence: Document recoverable page fault implications

by Daniel Vetter

On Wed, Feb 24, 2021 at 12:22 PM Thomas Hellström (Intel) <thomas_os(a)shipmail.org> wrote: > > > On 2/24/21 10:26 AM, Daniel Vetter wrote: > > On Wed, Feb 24, 2021 at 9:47 AM Thomas Hellström (Intel) > > <thomas_os(a)shipmail.org> wrote: > >> > >> On 2/3/21 4:29 PM, Daniel Vetter wrote: > >>> Recently there was a fairly long thread about recoreable hardware page > >>> faults, how they can deadlock, and what to do about that. > >>> > >>> While the discussion is still fresh I figured good time to try and > >>> document the conclusions a bit. This documentation section explains > >>> what's the potential problem, and the remedies we've discussed, > >>> roughly ordered from best to worst. > >>> > >>> v2: Linus -> Linux typoe (Dave) > >>> > >>> v3: > >>> - Make it clear drivers only need to implement one option (Christian) > >>> - Make it clearer that implicit sync is out the window with exclusive > >>> fences (Christian) > >>> - Add the fairly theoretical option of segementing the memory (either > >>> statically or through dynamic checks at runtime for which piece of > >>> memory is managed how) and explain why it's not a great idea (Felix) > >>> > >>> References: https://lore.kernel.org/dri-devel/20210107030127.20393-1-Felix.Kuehling@amd… > >>> Cc: Dave Airlie <airlied(a)gmail.com> > >>> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> > >>> Cc: Thomas Hellström <thomas.hellstrom(a)intel.com> > >>> Cc: "Christian König" <christian.koenig(a)amd.com> > >>> Cc: Jerome Glisse <jglisse(a)redhat.com> > >>> Cc: Felix Kuehling <felix.kuehling(a)amd.com> > >>> Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> > >>> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> > >>> Cc: linux-media(a)vger.kernel.org > >>> Cc: linaro-mm-sig(a)lists.linaro.org > >>> --- > >>> Documentation/driver-api/dma-buf.rst | 76 ++++++++++++++++++++++++++++ > >>> 1 file changed, 76 insertions(+) > >>> > >>> diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > >>> index a2133d69872c..7f37ec30d9fd 100644 > >>> --- a/Documentation/driver-api/dma-buf.rst > >>> +++ b/Documentation/driver-api/dma-buf.rst > >>> @@ -257,3 +257,79 @@ fences in the kernel. This means: > >>> userspace is allowed to use userspace fencing or long running compute > >>> workloads. This also means no implicit fencing for shared buffers in these > >>> cases. > >>> + > >>> +Recoverable Hardware Page Faults Implications > >>> +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > >>> + > >>> +Modern hardware supports recoverable page faults, which has a lot of > >>> +implications for DMA fences. > >>> + > >>> +First, a pending page fault obviously holds up the work that's running on the > >>> +accelerator and a memory allocation is usually required to resolve the fault. > >>> +But memory allocations are not allowed to gate completion of DMA fences, which > >>> +means any workload using recoverable page faults cannot use DMA fences for > >>> +synchronization. Synchronization fences controlled by userspace must be used > >>> +instead. > >>> + > >>> +On GPUs this poses a problem, because current desktop compositor protocols on > >>> +Linux rely on DMA fences, which means without an entirely new userspace stack > >>> +built on top of userspace fences, they cannot benefit from recoverable page > >>> +faults. Specifically this means implicit synchronization will not be possible. > >>> +The exception is when page faults are only used as migration hints and never to > >>> +on-demand fill a memory request. For now this means recoverable page > >>> +faults on GPUs are limited to pure compute workloads. > >>> + > >>> +Furthermore GPUs usually have shared resources between the 3D rendering and > >>> +compute side, like compute units or command submission engines. If both a 3D > >>> +job with a DMA fence and a compute workload using recoverable page faults are > >>> +pending they could deadlock: > >>> + > >>> +- The 3D workload might need to wait for the compute job to finish and release > >>> + hardware resources first. > >>> + > >>> +- The compute workload might be stuck in a page fault, because the memory > >>> + allocation is waiting for the DMA fence of the 3D workload to complete. > >>> + > >>> +There are a few options to prevent this problem, one of which drivers need to > >>> +ensure: > >>> + > >>> +- Compute workloads can always be preempted, even when a page fault is pending > >>> + and not yet repaired. Not all hardware supports this. > >>> + > >>> +- DMA fence workloads and workloads which need page fault handling have > >>> + independent hardware resources to guarantee forward progress. This could be > >>> + achieved through e.g. through dedicated engines and minimal compute unit > >>> + reservations for DMA fence workloads. > >>> + > >>> +- The reservation approach could be further refined by only reserving the > >>> + hardware resources for DMA fence workloads when they are in-flight. This must > >>> + cover the time from when the DMA fence is visible to other threads up to > >>> + moment when fence is completed through dma_fence_signal(). > >>> + > >>> +- As a last resort, if the hardware provides no useful reservation mechanics, > >>> + all workloads must be flushed from the GPU when switching between jobs > >>> + requiring DMA fences or jobs requiring page fault handling: This means all DMA > >>> + fences must complete before a compute job with page fault handling can be > >>> + inserted into the scheduler queue. And vice versa, before a DMA fence can be > >>> + made visible anywhere in the system, all compute workloads must be preempted > >>> + to guarantee all pending GPU page faults are flushed. > >>> + > >>> +- Only a fairly theoretical option would be to untangle these dependencies when > >>> + allocating memory to repair hardware page faults, either through separate > >>> + memory blocks or runtime tracking of the full dependency graph of all DMA > >>> + fences. This results very wide impact on the kernel, since resolving the page > >>> + on the CPU side can itself involve a page fault. It is much more feasible and > >>> + robust to limit the impact of handling hardware page faults to the specific > >>> + driver. > >>> + > >>> +Note that workloads that run on independent hardware like copy engines or other > >>> +GPUs do not have any impact. This allows us to keep using DMA fences internally > >>> +in the kernel even for resolving hardware page faults, e.g. by using copy > >>> +engines to clear or copy memory needed to resolve the page fault. > >>> + > >>> +In some ways this page fault problem is a special case of the `Infinite DMA > >>> +Fences` discussions: Infinite fences from compute workloads are allowed to > >>> +depend on DMA fences, but not the other way around. And not even the page fault > >>> +problem is new, because some other CPU thread in userspace might > >>> +hit a page fault which holds up a userspace fence - supporting page faults on > >>> +GPUs doesn't anything fundamentally new. > >> To me, in general this looks good. One thing, though is that for a first > >> time reader it might not be totally clear what's special with a compute > >> workload. Perhaps some clarification? > > In the docs this new section is right after the infinite fence > > section, which goes through this kind of stuff. So it's not so much > > "compute workloads" but "infinite fences", which I think is explained > > plenty enough. > > > OK, > >> Also since the current cross-driver dma_fence locking order is > >> > >> 1) dma_resv -> > >> 2) memory_allocation / reclaim -> > >> 3) dma_fence_wait/critical > >> > >> And the locking order required for recoverable pagefault is > >> > >> a) dma_resv -> > >> b) fence_wait/critical -> > >> c) memory_allocation / reclaim > >> > >> (Possibly with a) and b) interchanged above, Is it possible to service a > >> recoverable pagefault without taking the dma_resv lock?) > > It's worse, since the lock order we care about is: > > 1) mmap_sem > > 2) dma_resv > > 3) reclaim > > 4) dma_fence_wait > > > > And for this nice brave new world of unified shared memory/hmm, we > > really need to be able to resolve arbitrary cpu side page faults (with > > fixup_user_fault() like the iommu driver does too for PASID mode) to > > be able to serve gpu page faults. So even if we take dma_resv > > completely out of the system we still have: > > > > 1) mmap_sem > > 2) reclaim > > 3) dma_fence_wait > > > > So we'd also need to throw out dma_fence_wait, and at that point we're > > looking at a new gpu driver stack. > > > Meaning that the locking order for workloads with recoverable page > faults becomes: > > a) dma_fence_wait/critical > b) mmap_sem > c) dma_resv > d) reclaim > > which I agree we can't really use with the current stack whatever we do > with dma_fence_wait vs reclaim. > > > >> It's clear that the fence critical section in b) is not compatible with > >> the dma_fence wait in 3) and thus the memory restrictions are needed. > >> But I think given the memory allocation restrictions for recoverable > >> pagefaults I guess at some point we must ask ourselves why are they > >> necessary and what's the price to be paid for getting rid of them, and > >> document also that. *If* it's the case that it all boils down to the 2) > >> -> 3) locking order above, and that's mandated *only* by the dma_fence > >> wait in the userptr mmu notifiers, I think these restrictions are a > >> pretty high price to pay. Wouldn't it be possible now to replace that > >> fence wait with either page pinning (which now is coherent since 5.9) or > >> preempt-ctx fences + unpinned pages if available and thus invert the 2) > >> -> 3) locking order? > > It's not just userptr, it's also shrinkers. mmap_sem requires > > GFP_KERNEL allocations, so that already excludes our shrinkers if we > > want this. That means gpu memory becomes pinned when it's managed with > > dma_fence. Christian König just reworked ttm to stop doing that, to > > remove the hard and fairly arbitrary "max 50% of system memory" limit. > > Even with shrinkers, and assuming there is no guarantee we can preempt, > one could tag memory / bos for release on next reservation / dma_fence > signal whatever happens first, which would not give memory back on > direct reclaim, but will eventually release it. Will not help with the > mmap_sem issue, though. > > > > > > > > Note that just preempt-ctx fences alone isn't enough, since you could > > end up with something like this: > > - compute workload using gpu page faults hangs a all of the > > compute/shadercores on page faults, we can't preempt > > - concurrently there's a 3d workload running, which because fixed > > function, and only preempt between draw calls. it is stuck waiting for > > some shader cores to become avaiable. this is possible because most > > gpus nowadays have separate command queues for compute/3d workloads > > - our kernel page fault handler for the compute job wants to preempt > > the 3d workload, which wont happen > > - everyone is firmly stuck and the user gets angry > Yes, preempt-ctx fences would indeed have to be guaranteed to be able to > preempt to work, using one of the options described above, But in > general, inverting reclaim and dma_fence_wait would actually resolve > this particular situation, even if it doesn't help with recoverable > pagefaults due to mmap_sem: > > - kernel page fault handler ends up in shrinker tagging 3D workload > resources for release > - Moves on to another shrinker that succeeds to release enough memory > - Compute workload proceeds > - 3D workload proceeds. > > ..But just wanting to get the full picture of what the tradeoffs of this > really are. The trouble with this is that we still need to guarantee forward progress. That means we must have enough memory available in other shrinkers/page-cache which is not hogged by the gpu in any way. E.g. just removing the dma_fence_wait from the mmu notifier wont help if we still hold the page refcounts at large. There's roughly two options: - Lots of local caches for memory allocations which are sized to contain the max in-flight working set. This is essentially what the block layer uses for GFP_NOIO inversions. Problem is you must guarantee that everyone goes through these mempools, and that they're actually sized for the worst case. Since we're talking about fixing up userspace page faults that's pretty much the entire kernel which needs to be switched over to accurate memory reservation and accounting. - Other option is what essentially shrinkers/filesystems do with GFP_NOFS: You hard-limit them to something that's small enough overall and make sure you still have enough other memory (like normal page cache, which can be evicted with GFP_NOFS generally) to guarantee forward progress. Since shrinkers keep looping even when there's fairly minimal forward progress you should be able to get out of things again. Problem for us is that we don't just have shrinkers, but also love to consume arbitrary pagecache with get_user_pages/userptr, so this is tricky to guarantee. The big hammer approach here what ttm has done thus far with a hard limit to 50% and a best-effort kthread that tries to balance things in the background, outside of reclaim. The other problem I'm seeing is that core kernel is building ever more features on top of page migration, and there's a fairly constant flow of work to get to a point where page migration can be guaranteed. Stuff like get_user_pages vs. pin_user_pages, recent work (I think not yet merged) to move pages out of ZONE_MOVEABLE if their pinned. This is because hugepages have become rather critical for performance, and contiguous memory allocator really has to guarantee it can find its large blocks (I think there's people looking into using CMA for giant pages, since you're not going to ever get 1gb pages out of the buddy allocator). GPUs hogging arbitrary amounts of these pages through userptr, without being able to release them in a timely manner, does not look like a design with a bright future. But yeah if we could just wish away the dma_fence_wait from reclaim context, all these problems would go away. -Daniel > /Thomas > > > > So just requiring that everything uses preempt-ctx fences isn't enough > > due to shared resources possible blocking preemption even across > > engines. Plus we'd still have the problem that dma_fence_wait from > > reclaim isn't allowed, pinning all the 3d workload memory for good. > > > > Aside: This means that for compute workloads using page faults we > > cannot use preempt-ctx fences either, but instead memory reclaim has > > to exclusively use pte zapping (both shrinker and mmu notifier). > > > > Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH] dma-fence: Document recoverable page fault implications

by Daniel Vetter

On Wed, Feb 24, 2021 at 9:47 AM Thomas Hellström (Intel) <thomas_os(a)shipmail.org> wrote: > > > On 2/3/21 4:29 PM, Daniel Vetter wrote: > > Recently there was a fairly long thread about recoreable hardware page > > faults, how they can deadlock, and what to do about that. > > > > While the discussion is still fresh I figured good time to try and > > document the conclusions a bit. This documentation section explains > > what's the potential problem, and the remedies we've discussed, > > roughly ordered from best to worst. > > > > v2: Linus -> Linux typoe (Dave) > > > > v3: > > - Make it clear drivers only need to implement one option (Christian) > > - Make it clearer that implicit sync is out the window with exclusive > > fences (Christian) > > - Add the fairly theoretical option of segementing the memory (either > > statically or through dynamic checks at runtime for which piece of > > memory is managed how) and explain why it's not a great idea (Felix) > > > > References: https://lore.kernel.org/dri-devel/20210107030127.20393-1-Felix.Kuehling@amd… > > Cc: Dave Airlie <airlied(a)gmail.com> > > Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> > > Cc: Thomas Hellström <thomas.hellstrom(a)intel.com> > > Cc: "Christian König" <christian.koenig(a)amd.com> > > Cc: Jerome Glisse <jglisse(a)redhat.com> > > Cc: Felix Kuehling <felix.kuehling(a)amd.com> > > Signed-off-by: Daniel Vetter <daniel.vetter(a)intel.com> > > Cc: Sumit Semwal <sumit.semwal(a)linaro.org> > > Cc: linux-media(a)vger.kernel.org > > Cc: linaro-mm-sig(a)lists.linaro.org > > --- > > Documentation/driver-api/dma-buf.rst | 76 ++++++++++++++++++++++++++++ > > 1 file changed, 76 insertions(+) > > > > diff --git a/Documentation/driver-api/dma-buf.rst b/Documentation/driver-api/dma-buf.rst > > index a2133d69872c..7f37ec30d9fd 100644 > > --- a/Documentation/driver-api/dma-buf.rst > > +++ b/Documentation/driver-api/dma-buf.rst > > @@ -257,3 +257,79 @@ fences in the kernel. This means: > > userspace is allowed to use userspace fencing or long running compute > > workloads. This also means no implicit fencing for shared buffers in these > > cases. > > + > > +Recoverable Hardware Page Faults Implications > > +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > > + > > +Modern hardware supports recoverable page faults, which has a lot of > > +implications for DMA fences. > > + > > +First, a pending page fault obviously holds up the work that's running on the > > +accelerator and a memory allocation is usually required to resolve the fault. > > +But memory allocations are not allowed to gate completion of DMA fences, which > > +means any workload using recoverable page faults cannot use DMA fences for > > +synchronization. Synchronization fences controlled by userspace must be used > > +instead. > > + > > +On GPUs this poses a problem, because current desktop compositor protocols on > > +Linux rely on DMA fences, which means without an entirely new userspace stack > > +built on top of userspace fences, they cannot benefit from recoverable page > > +faults. Specifically this means implicit synchronization will not be possible. > > +The exception is when page faults are only used as migration hints and never to > > +on-demand fill a memory request. For now this means recoverable page > > +faults on GPUs are limited to pure compute workloads. > > + > > +Furthermore GPUs usually have shared resources between the 3D rendering and > > +compute side, like compute units or command submission engines. If both a 3D > > +job with a DMA fence and a compute workload using recoverable page faults are > > +pending they could deadlock: > > + > > +- The 3D workload might need to wait for the compute job to finish and release > > + hardware resources first. > > + > > +- The compute workload might be stuck in a page fault, because the memory > > + allocation is waiting for the DMA fence of the 3D workload to complete. > > + > > +There are a few options to prevent this problem, one of which drivers need to > > +ensure: > > + > > +- Compute workloads can always be preempted, even when a page fault is pending > > + and not yet repaired. Not all hardware supports this. > > + > > +- DMA fence workloads and workloads which need page fault handling have > > + independent hardware resources to guarantee forward progress. This could be > > + achieved through e.g. through dedicated engines and minimal compute unit > > + reservations for DMA fence workloads. > > + > > +- The reservation approach could be further refined by only reserving the > > + hardware resources for DMA fence workloads when they are in-flight. This must > > + cover the time from when the DMA fence is visible to other threads up to > > + moment when fence is completed through dma_fence_signal(). > > + > > +- As a last resort, if the hardware provides no useful reservation mechanics, > > + all workloads must be flushed from the GPU when switching between jobs > > + requiring DMA fences or jobs requiring page fault handling: This means all DMA > > + fences must complete before a compute job with page fault handling can be > > + inserted into the scheduler queue. And vice versa, before a DMA fence can be > > + made visible anywhere in the system, all compute workloads must be preempted > > + to guarantee all pending GPU page faults are flushed. > > + > > +- Only a fairly theoretical option would be to untangle these dependencies when > > + allocating memory to repair hardware page faults, either through separate > > + memory blocks or runtime tracking of the full dependency graph of all DMA > > + fences. This results very wide impact on the kernel, since resolving the page > > + on the CPU side can itself involve a page fault. It is much more feasible and > > + robust to limit the impact of handling hardware page faults to the specific > > + driver. > > + > > +Note that workloads that run on independent hardware like copy engines or other > > +GPUs do not have any impact. This allows us to keep using DMA fences internally > > +in the kernel even for resolving hardware page faults, e.g. by using copy > > +engines to clear or copy memory needed to resolve the page fault. > > + > > +In some ways this page fault problem is a special case of the `Infinite DMA > > +Fences` discussions: Infinite fences from compute workloads are allowed to > > +depend on DMA fences, but not the other way around. And not even the page fault > > +problem is new, because some other CPU thread in userspace might > > +hit a page fault which holds up a userspace fence - supporting page faults on > > +GPUs doesn't anything fundamentally new. > > To me, in general this looks good. One thing, though is that for a first > time reader it might not be totally clear what's special with a compute > workload. Perhaps some clarification? In the docs this new section is right after the infinite fence section, which goes through this kind of stuff. So it's not so much "compute workloads" but "infinite fences", which I think is explained plenty enough. > Also since the current cross-driver dma_fence locking order is > > 1) dma_resv -> > 2) memory_allocation / reclaim -> > 3) dma_fence_wait/critical > > And the locking order required for recoverable pagefault is > > a) dma_resv -> > b) fence_wait/critical -> > c) memory_allocation / reclaim > > (Possibly with a) and b) interchanged above, Is it possible to service a > recoverable pagefault without taking the dma_resv lock?) It's worse, since the lock order we care about is: 1) mmap_sem 2) dma_resv 3) reclaim 4) dma_fence_wait And for this nice brave new world of unified shared memory/hmm, we really need to be able to resolve arbitrary cpu side page faults (with fixup_user_fault() like the iommu driver does too for PASID mode) to be able to serve gpu page faults. So even if we take dma_resv completely out of the system we still have: 1) mmap_sem 2) reclaim 3) dma_fence_wait So we'd also need to throw out dma_fence_wait, and at that point we're looking at a new gpu driver stack. > It's clear that the fence critical section in b) is not compatible with > the dma_fence wait in 3) and thus the memory restrictions are needed. > But I think given the memory allocation restrictions for recoverable > pagefaults I guess at some point we must ask ourselves why are they > necessary and what's the price to be paid for getting rid of them, and > document also that. *If* it's the case that it all boils down to the 2) > -> 3) locking order above, and that's mandated *only* by the dma_fence > wait in the userptr mmu notifiers, I think these restrictions are a > pretty high price to pay. Wouldn't it be possible now to replace that > fence wait with either page pinning (which now is coherent since 5.9) or > preempt-ctx fences + unpinned pages if available and thus invert the 2) > -> 3) locking order? It's not just userptr, it's also shrinkers. mmap_sem requires GFP_KERNEL allocations, so that already excludes our shrinkers if we want this. That means gpu memory becomes pinned when it's managed with dma_fence. Christian König just reworked ttm to stop doing that, to remove the hard and fairly arbitrary "max 50% of system memory" limit. The only option that would work is if we throw out dma_fence out and exclusively manage memory with gpu page faults only. Even across the gpus that do support page faults that's not true for all workloads, e.g. nvidia only supports page faults on compute engines, not on any of the 3d fixed function stuff or media codecs (to my knowledge). So not going to happen. In addition, this plan requires that we stop using dma_fence for sync (otherwise you can't use preempt-ctx fences). That's the "10 year plan to rev the ecosystem" problem, although with lots of discussions with Christian and Jason from mesa I think we've boiled this down to a more minimal task list by now: - vk driver mode that users userspace fences. There's a somewhat nasty problem here because you can only decide which mode to use when you know which winsys to use. And with vk that's created after the render pipeline (unlike gl). Plus it's dynamic, e.g. if you run on X or wayland without the below stuff support, but then use direct display and the kernel already has timeline syncobj support, you should probably use userspace fencing. - new wayland/x protocol to pass timeline drm_syncob around as syncobj - drm_syncobj support in atomic ioctl - compositors switching over to vk + using timeline syncobj for fencing - new drm_syncobj mode where we wrap a userspace fence: new userspace would pull the userspace fence out, any legacy drivers would have to block until the fence has signalled. This sucks compared to current timeline syncobj, where we just wait for the dma_fence to materialize, but since it can use the same paths/ioctls it would at least give us a smooth upgrade path. Inclusive allowing both old and new userspace to co-exist on the same compositor session. Note that just preempt-ctx fences alone isn't enough, since you could end up with something like this: - compute workload using gpu page faults hangs a all of the compute/shadercores on page faults, we can't preempt - concurrently there's a 3d workload running, which because fixed function, and only preempt between draw calls. it is stuck waiting for some shader cores to become avaiable. this is possible because most gpus nowadays have separate command queues for compute/3d workloads - our kernel page fault handler for the compute job wants to preempt the 3d workload, which wont happen - everyone is firmly stuck and the user gets angry So just requiring that everything uses preempt-ctx fences isn't enough due to shared resources possible blocking preemption even across engines. Plus we'd still have the problem that dma_fence_wait from reclaim isn't allowed, pinning all the 3d workload memory for good. Aside: This means that for compute workloads using page faults we cannot use preempt-ctx fences either, but instead memory reclaim has to exclusively use pte zapping (both shrinker and mmu notifier). Cheers, Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH] drm/ttm/ttm_bo: make ttm_bo_glob_use_count static

by Christian König

Am 23.02.21 um 09:54 schrieb Jiapeng Chong: > Fix the following sparse warning: > > drivers/gpu/drm/ttm/ttm_bo.c:53:10: warning: symbol > 'ttm_bo_glob_use_count' was not declared. Should it be static? IIRC we already have a patch for this on the mailing list and the mutex can be static as well. Christian. > > Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> > Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> > --- > drivers/gpu/drm/ttm/ttm_bo.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c > index b65f4b1..107dd13 100644 > --- a/drivers/gpu/drm/ttm/ttm_bo.c > +++ b/drivers/gpu/drm/ttm/ttm_bo.c > @@ -50,7 +50,7 @@ > * ttm_global_mutex - protecting the global BO state > */ > DEFINE_MUTEX(ttm_global_mutex); > -unsigned ttm_bo_glob_use_count; > +static unsigned ttm_bo_glob_use_count; > struct ttm_bo_global ttm_bo_glob; > EXPORT_SYMBOL(ttm_bo_glob); >

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH] drm/amdgpu/sdma5.2: Remove unnecessary conversion to bool

by Alex Deucher

Applied. Thanks! Alex On Sat, Feb 20, 2021 at 3:35 AM Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> wrote: > > Fix the following coccicheck warnings: > > ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1621:40-45: WARNING: conversion > to bool not needed here. > > ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1619:40-45: WARNING: conversion > to bool not needed here. > > Reported-by: Abaci Robot <abaci(a)linux.alibaba.com> > Signed-off-by: Jiapeng Chong <jiapeng.chong(a)linux.alibaba.com> > --- > drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > index f1ba36a..9ed79a9 100644 > --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c > @@ -1616,9 +1616,9 @@ static int sdma_v5_2_set_clockgating_state(void *handle, > case CHIP_VANGOGH: > case CHIP_DIMGREY_CAVEFISH: > sdma_v5_2_update_medium_grain_clock_gating(adev, > - state == AMD_CG_STATE_GATE ? true : false); > + state == AMD_CG_STATE_GATE); > sdma_v5_2_update_medium_grain_light_sleep(adev, > - state == AMD_CG_STATE_GATE ? true : false); > + state == AMD_CG_STATE_GATE); > break; > default: > break; > -- > 1.8.3.1 > > _______________________________________________ > dri-devel mailing list > dri-devel(a)lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/dri-devel

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH v2 0/3] drm/prime: Only call dma_map_sgtable() for devices with DMA support

by Daniel Vetter

On Mon, Feb 22, 2021 at 05:25:46PM +0100, Thomas Zimmermann wrote: > Hi > > Am 22.02.21 um 17:10 schrieb Daniel Vetter: > > On Mon, Feb 22, 2021 at 2:24 PM Thomas Zimmermann <tzimmermann(a)suse.de> wrote: > > > > > > Hi > > > > > > Am 22.02.21 um 14:09 schrieb Christian König: > > > > > > > > > > > > Am 22.02.21 um 13:43 schrieb Thomas Zimmermann: > > > > > USB-based drivers cannot use DMA, so the importing of dma-buf attachments > > > > > currently fails for udl and gm12u320. This breaks joining/mirroring of > > > > > displays. > > > > > > > > > > The fix is now a little series. To solve the issue on the importer > > > > > side (i.e., the affected USB-based driver), patch 1 introduces a new > > > > > PRIME callback, struct drm_driver.gem_prime_create_object, which creates > > > > > an object and gives more control to the importing driver. Specifically, > > > > > udl and gm12u320 can now avoid the creation of a scatter/gather table > > > > > for the imported pages. Patch 1 is self-contained in the sense that it > > > > > can be backported into older kernels. > > > > > > > > Mhm, that sounds like a little overkill to me. > > > > > > > > Drivers can already import the DMA-bufs all by them selves without the > > > > help of the DRM functions. See amdgpu for an example. > > > > > > > > Daniel also already noted to me that he sees the DRM helper as a bit > > > > questionable middle layer. > > > > > > And this bug proves that it is. :) > > > > The trouble here is actually gem_bo->import_attach, which isn't really > > part of the questionable midlayer, but fairly mandatory (only > > exception is vmwgfx because not using gem) caching to make sure we > > don't end up with duped imports and fun stuff like that. > > > > And dma_buf_attach now implicitly creates the sg table already, so > > we're already in game over land. I think we'd need to make > > import_attach a union with import_buf or something like that, so that > > you can do attachment-less importing. > > Creating the sg table is not the problem; mapping it is. So dma_buf_attach > shouldn't be a problem. dma_buf_attach will create a cached sg-mapping for you if the exporter is dynamic. Currently that's only the case for amdgpu, I guess you didn't test with that. So yeah dma_buf_attach is a problem already. And if we can't attach, the entire obj->import_attach logic in drm_prime.c falls over, and we get all kinds of fun with double import and re-export. > > > > Have you thought about doing that instead? > > > > > > There appears to be some useful code in drm_gem_prime_import_dev(). But > > > if the general sentiment goes towards removing > > > gem_prime_import_sg_table, we can work towards that as well. > > > > I still think this part is a bit a silly midlayer for no good reason, > > but I think that's orthogonal to the issue at hand here. > > > > I'd suggest we first try to paper over the issue by using > > prime_import_dev with the host controller (which hopefully is > > dma-capable for most systems). And then, at leisure, try to untangle > > the obj->import_attach issue. > > I really don't want to do this. My time is also limited, and I''ll spend > time papering over the thing. And then more time for the real fix. I'd > rather pull drm_gem_prime_import_dev() in to USB drivers and avoid the > dma_buf_map(). Yeah I understand, it's just (as usual :-/) more complex than it seems ... -Daniel > > Best regard > Thomas > > > -Daniel > > > > > > > > Best regards > > > Thomas > > > > > > > > > > > Christian. > > > > > > > > > > > > > > Patches 2 and 3 update SHMEM and CMA helpers to use the new callback. > > > > > Effectively this moves the sg table setup from the PRIME helpers into > > > > > the memory managers. SHMEM now supports devices without DMA support, > > > > > so custom code can be removed from udl and g12u320. > > > > > > > > > > Tested by joining/mirroring displays of udl and radeon under Gnome/X11. > > > > > > > > > > v2: > > > > > * move fix to importer side (Christian, Daniel) > > > > > * update SHMEM and CMA helpers for new PRIME callbacks > > > > > > > > > > Thomas Zimmermann (3): > > > > > drm: Support importing dmabufs into drivers without DMA > > > > > drm/shmem-helper: Implement struct drm_driver.gem_prime_create_object > > > > > drm/cma-helper: Implement struct drm_driver.gem_prime_create_object > > > > > > > > > > drivers/gpu/drm/drm_gem_cma_helper.c | 62 ++++++++++++++----------- > > > > > drivers/gpu/drm/drm_gem_shmem_helper.c | 38 ++++++++++----- > > > > > drivers/gpu/drm/drm_prime.c | 43 +++++++++++------ > > > > > drivers/gpu/drm/lima/lima_drv.c | 2 +- > > > > > drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +- > > > > > drivers/gpu/drm/panfrost/panfrost_gem.c | 6 +-- > > > > > drivers/gpu/drm/panfrost/panfrost_gem.h | 4 +- > > > > > drivers/gpu/drm/pl111/pl111_drv.c | 8 ++-- > > > > > drivers/gpu/drm/v3d/v3d_bo.c | 6 +-- > > > > > drivers/gpu/drm/v3d/v3d_drv.c | 2 +- > > > > > drivers/gpu/drm/v3d/v3d_drv.h | 5 +- > > > > > include/drm/drm_drv.h | 12 +++++ > > > > > include/drm/drm_gem_cma_helper.h | 12 ++--- > > > > > include/drm/drm_gem_shmem_helper.h | 6 +-- > > > > > 14 files changed, 120 insertions(+), 88 deletions(-) > > > > > > > > > > -- > > > > > 2.30.1 > > > > > > > > > > > > > > > -- > > > Thomas Zimmermann > > > Graphics Driver Developer > > > SUSE Software Solutions Germany GmbH > > > Maxfeldstr. 5, 90409 Nürnberg, Germany > > > (HRB 36809, AG Nürnberg) > > > Geschäftsführer: Felix Imendörffer > > > > > > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 Nürnberg, Germany > (HRB 36809, AG Nürnberg) > Geschäftsführer: Felix Imendörffer > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH v2 1/3] drm: Support importing dmabufs into drivers without DMA

by Daniel Vetter

On Mon, Feb 22, 2021 at 01:43:26PM +0100, Thomas Zimmermann wrote: > USB devices cannot perform DMA and hence have no dma_mask set in their > device structure. Importing dmabuf into a USB-based driver fails, which > break joining and mirroring of display in X11. A corresponding error > message is shown below. > > [ 60.050199] ------------[ cut here ]------------ > [ 60.055092] WARNING: CPU: 0 PID: 1403 at kernel/dma/mapping.c:190 dma_map_sg_attrs+0x8f/0xc0 > [ 60.064331] Modules linked in: af_packet(E) rfkill(E) dmi_sysfs(E) intel_rapl_msr(E) intel_rapl_common(E) snd_hda_codec_realtek(E) snd_hda_codec_generic(E) ledtrig_audio(E) snd_hda_codec_hdmi(E) x86_pkg_temp_thermal(E) intel_powerclam) > [ 60.064801] wmi(E) video(E) btrfs(E) blake2b_generic(E) libcrc32c(E) crc32c_intel(E) xor(E) raid6_pq(E) sg(E) dm_multipath(E) dm_mod(E) scsi_dh_rdac(E) scsi_dh_emc(E) scsi_dh_alua(E) msr(E) efivarfs(E) > [ 60.170778] CPU: 0 PID: 1403 Comm: Xorg.bin Tainted: G E 5.11.0-rc5-1-default+ #747 > [ 60.179841] Hardware name: Dell Inc. OptiPlex 9020/0N4YC8, BIOS A24 10/24/2018 > [ 60.187145] RIP: 0010:dma_map_sg_attrs+0x8f/0xc0 > [ 60.191822] Code: 4d 85 ff 75 2b 49 89 d8 44 89 e1 44 89 f2 4c 89 ee 48 89 ef e8 62 30 00 00 85 c0 78 36 5b 5d 41 5c 41 5d 41 5e 41 5f c3 0f 0b <0f> 0b 31 c0 eb ed 49 8d 7f 50 e8 72 f5 2a 00 49 8b 47 50 49 89 d8 > [ 60.210770] RSP: 0018:ffffc90001d6fc18 EFLAGS: 00010246 > [ 60.216062] RAX: 0000000000000000 RBX: 0000000000000020 RCX: ffffffffb31e677b > [ 60.223274] RDX: dffffc0000000000 RSI: ffff888212c10600 RDI: ffff8881b08a9488 > [ 60.230501] RBP: ffff8881b08a9030 R08: 0000000000000020 R09: ffff888212c10600 > [ 60.237710] R10: ffffed10425820df R11: 0000000000000001 R12: 0000000000000000 > [ 60.244939] R13: ffff888212c10600 R14: 0000000000000008 R15: 0000000000000000 > [ 60.252155] FS: 00007f08ac2b2f00(0000) GS:ffff8887cbe00000(0000) knlGS:0000000000000000 > [ 60.260333] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 > [ 60.266150] CR2: 000055831c899be8 CR3: 000000015372e006 CR4: 00000000001706f0 > [ 60.273369] Call Trace: > [ 60.275845] drm_gem_map_dma_buf+0xb4/0x120 > [ 60.280089] dma_buf_map_attachment+0x15d/0x1e0 > [ 60.284688] drm_gem_prime_import_dev.part.0+0x5d/0x140 > [ 60.289984] drm_gem_prime_fd_to_handle+0x213/0x280 > [ 60.294931] ? drm_prime_destroy_file_private+0x30/0x30 > [ 60.300224] drm_ioctl_kernel+0x131/0x180 > [ 60.304291] ? drm_setversion+0x230/0x230 > [ 60.308366] ? drm_prime_destroy_file_private+0x30/0x30 > [ 60.313659] drm_ioctl+0x2f1/0x500 > [ 60.317118] ? drm_version+0x150/0x150 > [ 60.320903] ? lock_downgrade+0xa0/0xa0 > [ 60.324806] ? do_vfs_ioctl+0x5f4/0x680 > [ 60.328694] ? __fget_files+0x13e/0x210 > [ 60.332591] ? ioctl_fiemap.isra.0+0x1a0/0x1a0 > [ 60.337102] ? __fget_files+0x15d/0x210 > [ 60.340990] __x64_sys_ioctl+0xb9/0xf0 > [ 60.344795] do_syscall_64+0x33/0x80 > [ 60.348427] entry_SYSCALL_64_after_hwframe+0x44/0xa9 > [ 60.353542] RIP: 0033:0x7f08ac7b53cb > [ 60.357168] Code: 89 d8 49 8d 3c 1c 48 f7 d8 49 39 c4 72 b5 e8 1c ff ff ff 85 c0 78 ba 4c 89 e0 5b 5d 41 5c c3 f3 0f 1e fa b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 75 ba 0c 00 f7 d8 64 89 01 48 > [ 60.376108] RSP: 002b:00007ffeabc89fc8 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 > [ 60.383758] RAX: ffffffffffffffda RBX: 00007ffeabc8a00c RCX: 00007f08ac7b53cb > [ 60.390970] RDX: 00007ffeabc8a00c RSI: 00000000c00c642e RDI: 000000000000000d > [ 60.398221] RBP: 00000000c00c642e R08: 000055831c691d00 R09: 000055831b2ec010 > [ 60.405446] R10: 00007f08acf6ada0 R11: 0000000000000246 R12: 000055831c691d00 > [ 60.412667] R13: 000000000000000d R14: 00000000007e9000 R15: 0000000000000000 > [ 60.419903] irq event stamp: 672893 > [ 60.423441] hardirqs last enabled at (672913): [<ffffffffb31b796d>] console_unlock+0x44d/0x500 > [ 60.432230] hardirqs last disabled at (672922): [<ffffffffb31b7963>] console_unlock+0x443/0x500 > [ 60.441021] softirqs last enabled at (672940): [<ffffffffb46003dd>] __do_softirq+0x3dd/0x554 > [ 60.449634] softirqs last disabled at (672931): [<ffffffffb44010f2>] asm_call_irq_on_stack+0x12/0x20 > [ 60.458871] ---[ end trace f2f88696eb17806c ]--- > > This patch introduces struct drm_driver.gem_prime_create_object, which > creates a GEM object during the import. Drivers should implement this > callback and handle DMA S/G table support by themselves. For USB-based > drivers, the patch adds an implementation without DMA-related code. > > The original interface struct drm_driver.gem_prime_import_sg_table > is deprecated. All drivers should switch over. > > Tested by joining/mirroring displays of udl and radeon un der Gnome/X11. > > Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> > Fixes: 6eb0233ec2d0 ("usb: don't inherity DMA properties for USB devices") > Cc: Christoph Hellwig <hch(a)lst.de> > Cc: Greg Kroah-Hartman <gregkh(a)linuxfoundation.org> > Cc: Alan Stern <stern(a)rowland.harvard.edu> > Cc: Johan Hovold <johan(a)kernel.org> > Cc: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> > Cc: Sebastian Andrzej Siewior <bigeasy(a)linutronix.de> > Cc: Mathias Nyman <mathias.nyman(a)linux.intel.com> > Cc: "Ahmed S. Darwish" <a.darwish(a)linutronix.de> > Cc: Oliver Neukum <oneukum(a)suse.com> > Cc: Thomas Gleixner <tglx(a)linutronix.de> > Cc: Felipe Balbi <balbi(a)kernel.org> > Cc: <stable(a)vger.kernel.org> # v5.10+ > --- > drivers/gpu/drm/drm_prime.c | 43 +++++++++++++++++++++------------ > drivers/gpu/drm/tiny/gm12u320.c | 7 ++++++ > drivers/gpu/drm/udl/udl_drv.c | 7 ++++++ > include/drm/drm_drv.h | 12 +++++++++ > 4 files changed, 54 insertions(+), 15 deletions(-) > > diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c > index 2a54f86856af..9bb30e843a44 100644 > --- a/drivers/gpu/drm/drm_prime.c > +++ b/drivers/gpu/drm/drm_prime.c > @@ -923,7 +923,8 @@ struct drm_gem_object *drm_gem_prime_import_dev(struct drm_device *dev, > } > } > > - if (!dev->driver->gem_prime_import_sg_table) > + if (!dev->driver->gem_prime_import_sg_table && > + !dev->driver->gem_prime_create_object) > return ERR_PTR(-EINVAL); > > attach = dma_buf_attach(dma_buf, attach_dev); > @@ -932,25 +933,37 @@ struct drm_gem_object *drm_gem_prime_import_dev(struct drm_device *dev, > > get_dma_buf(dma_buf); > > - sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); > - if (IS_ERR(sgt)) { > - ret = PTR_ERR(sgt); > - goto fail_detach; > - } > + if (dev->driver->gem_prime_create_object) { > + obj = dev->driver->gem_prime_create_object(dev, attach); > + if (IS_ERR(obj)) { > + ret = PTR_ERR(obj); > + goto fail_detach; > + } > > - obj = dev->driver->gem_prime_import_sg_table(dev, attach, sgt); > - if (IS_ERR(obj)) { > - ret = PTR_ERR(obj); > - goto fail_unmap; > - } > + if (!obj->import_attach) > + obj->import_attach = attach; If you don't set import_attach then the refcounting and double-import prevention goes all kinds of wrong. So unfortunately it's not that easy. -Daniel > + if (!obj->resv) > + obj->resv = dma_buf->resv; > + } else { > + sgt = dma_buf_map_attachment(attach, DMA_BIDIRECTIONAL); > + if (IS_ERR(sgt)) { > + ret = PTR_ERR(sgt); > + goto fail_detach; > + } > > - obj->import_attach = attach; > - obj->resv = dma_buf->resv; > + obj = dev->driver->gem_prime_import_sg_table(dev, attach, sgt); > + if (IS_ERR(obj)) { > + ret = PTR_ERR(obj); > + dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL); > + goto fail_detach; > + } > + > + obj->import_attach = attach; > + obj->resv = dma_buf->resv; > + } > > return obj; > > -fail_unmap: > - dma_buf_unmap_attachment(attach, sgt, DMA_BIDIRECTIONAL); > fail_detach: > dma_buf_detach(dma_buf, attach); > dma_buf_put(dma_buf); > diff --git a/drivers/gpu/drm/tiny/gm12u320.c b/drivers/gpu/drm/tiny/gm12u320.c > index 0b4f4f2af1ef..9f13a7c7c2da 100644 > --- a/drivers/gpu/drm/tiny/gm12u320.c > +++ b/drivers/gpu/drm/tiny/gm12u320.c > @@ -601,6 +601,12 @@ static const uint64_t gm12u320_pipe_modifiers[] = { > > DEFINE_DRM_GEM_FOPS(gm12u320_fops); > > +static struct drm_gem_object *gm12u320_gem_prime_create_object(struct drm_device *dev, > + struct dma_buf_attachment *attach) > +{ > + return drm_gem_shmem_prime_import_sg_table(dev, attach, NULL); > +} > + > static const struct drm_driver gm12u320_drm_driver = { > .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, > > @@ -612,6 +618,7 @@ static const struct drm_driver gm12u320_drm_driver = { > > .fops = &gm12u320_fops, > DRM_GEM_SHMEM_DRIVER_OPS, > + .gem_prime_create_object = gm12u320_gem_prime_create_object, > }; > > static const struct drm_mode_config_funcs gm12u320_mode_config_funcs = { > diff --git a/drivers/gpu/drm/udl/udl_drv.c b/drivers/gpu/drm/udl/udl_drv.c > index 9269092697d8..fdf37b44a956 100644 > --- a/drivers/gpu/drm/udl/udl_drv.c > +++ b/drivers/gpu/drm/udl/udl_drv.c > @@ -34,12 +34,19 @@ static int udl_usb_resume(struct usb_interface *interface) > > DEFINE_DRM_GEM_FOPS(udl_driver_fops); > > +static struct drm_gem_object *udl_gem_prime_create_object(struct drm_device *dev, > + struct dma_buf_attachment *attach) > +{ > + return drm_gem_shmem_prime_import_sg_table(dev, attach, NULL); > +} > + > static const struct drm_driver driver = { > .driver_features = DRIVER_ATOMIC | DRIVER_GEM | DRIVER_MODESET, > > /* GEM hooks */ > .fops = &udl_driver_fops, > DRM_GEM_SHMEM_DRIVER_OPS, > + .gem_prime_create_object = udl_gem_prime_create_object, > > .name = DRIVER_NAME, > .desc = DRIVER_DESC, > diff --git a/include/drm/drm_drv.h b/include/drm/drm_drv.h > index 827838e0a97e..77657d649ca6 100644 > --- a/include/drm/drm_drv.h > +++ b/include/drm/drm_drv.h > @@ -369,11 +369,23 @@ struct drm_driver { > */ > struct drm_gem_object * (*gem_prime_import)(struct drm_device *dev, > struct dma_buf *dma_buf); > + /** > + * @gem_prime_create_object: > + * > + * Optional hook used by the PRIME helper functions > + * drm_gem_prime_import() respectively drm_gem_prime_import_dev(). > + */ > + struct drm_gem_object *(*gem_prime_create_object)( > + struct drm_device *dev, > + struct dma_buf_attachment *attach); > /** > * @gem_prime_import_sg_table: > * > * Optional hook used by the PRIME helper functions > * drm_gem_prime_import() respectively drm_gem_prime_import_dev(). > + * > + * TODO: This function is deprecated in favor of @drm_driver.gem_prime_create_object. > + * Drivers should switch over and implement SG-table support by themselves. > */ > struct drm_gem_object *(*gem_prime_import_sg_table)( > struct drm_device *dev, > -- > 2.30.1 > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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Re: [Linaro-mm-sig] [PATCH v2 0/3] drm/prime: Only call dma_map_sgtable() for devices with DMA support

by Daniel Vetter

On Mon, Feb 22, 2021 at 2:24 PM Thomas Zimmermann <tzimmermann(a)suse.de> wrote: > > Hi > > Am 22.02.21 um 14:09 schrieb Christian König: > > > > > > Am 22.02.21 um 13:43 schrieb Thomas Zimmermann: > >> USB-based drivers cannot use DMA, so the importing of dma-buf attachments > >> currently fails for udl and gm12u320. This breaks joining/mirroring of > >> displays. > >> > >> The fix is now a little series. To solve the issue on the importer > >> side (i.e., the affected USB-based driver), patch 1 introduces a new > >> PRIME callback, struct drm_driver.gem_prime_create_object, which creates > >> an object and gives more control to the importing driver. Specifically, > >> udl and gm12u320 can now avoid the creation of a scatter/gather table > >> for the imported pages. Patch 1 is self-contained in the sense that it > >> can be backported into older kernels. > > > > Mhm, that sounds like a little overkill to me. > > > > Drivers can already import the DMA-bufs all by them selves without the > > help of the DRM functions. See amdgpu for an example. > > > > Daniel also already noted to me that he sees the DRM helper as a bit > > questionable middle layer. > > And this bug proves that it is. :) The trouble here is actually gem_bo->import_attach, which isn't really part of the questionable midlayer, but fairly mandatory (only exception is vmwgfx because not using gem) caching to make sure we don't end up with duped imports and fun stuff like that. And dma_buf_attach now implicitly creates the sg table already, so we're already in game over land. I think we'd need to make import_attach a union with import_buf or something like that, so that you can do attachment-less importing. > > Have you thought about doing that instead? > > There appears to be some useful code in drm_gem_prime_import_dev(). But > if the general sentiment goes towards removing > gem_prime_import_sg_table, we can work towards that as well. I still think this part is a bit a silly midlayer for no good reason, but I think that's orthogonal to the issue at hand here. I'd suggest we first try to paper over the issue by using prime_import_dev with the host controller (which hopefully is dma-capable for most systems). And then, at leisure, try to untangle the obj->import_attach issue. -Daniel > > Best regards > Thomas > > > > > Christian. > > > >> > >> Patches 2 and 3 update SHMEM and CMA helpers to use the new callback. > >> Effectively this moves the sg table setup from the PRIME helpers into > >> the memory managers. SHMEM now supports devices without DMA support, > >> so custom code can be removed from udl and g12u320. > >> > >> Tested by joining/mirroring displays of udl and radeon under Gnome/X11. > >> > >> v2: > >> * move fix to importer side (Christian, Daniel) > >> * update SHMEM and CMA helpers for new PRIME callbacks > >> > >> Thomas Zimmermann (3): > >> drm: Support importing dmabufs into drivers without DMA > >> drm/shmem-helper: Implement struct drm_driver.gem_prime_create_object > >> drm/cma-helper: Implement struct drm_driver.gem_prime_create_object > >> > >> drivers/gpu/drm/drm_gem_cma_helper.c | 62 ++++++++++++++----------- > >> drivers/gpu/drm/drm_gem_shmem_helper.c | 38 ++++++++++----- > >> drivers/gpu/drm/drm_prime.c | 43 +++++++++++------ > >> drivers/gpu/drm/lima/lima_drv.c | 2 +- > >> drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +- > >> drivers/gpu/drm/panfrost/panfrost_gem.c | 6 +-- > >> drivers/gpu/drm/panfrost/panfrost_gem.h | 4 +- > >> drivers/gpu/drm/pl111/pl111_drv.c | 8 ++-- > >> drivers/gpu/drm/v3d/v3d_bo.c | 6 +-- > >> drivers/gpu/drm/v3d/v3d_drv.c | 2 +- > >> drivers/gpu/drm/v3d/v3d_drv.h | 5 +- > >> include/drm/drm_drv.h | 12 +++++ > >> include/drm/drm_gem_cma_helper.h | 12 ++--- > >> include/drm/drm_gem_shmem_helper.h | 6 +-- > >> 14 files changed, 120 insertions(+), 88 deletions(-) > >> > >> -- > >> 2.30.1 > >> > > > > -- > Thomas Zimmermann > Graphics Driver Developer > SUSE Software Solutions Germany GmbH > Maxfeldstr. 5, 90409 Nürnberg, Germany > (HRB 36809, AG Nürnberg) > Geschäftsführer: Felix Imendörffer > -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch

4 years, 3 months

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