Re: [PATCH v4 0/6] TEE subsystem for restricted dma-buf allocations
by Sumit Garg
On Fri, 14 Feb 2025 at 21:19, Boris Brezillon
<boris.brezillon(a)collabora.com> wrote:
>
> On Fri, 14 Feb 2025 18:37:14 +0530
> Sumit Garg <sumit.garg(a)linaro.org> wrote:
>
> > On Fri, 14 Feb 2025 at 15:37, Jens Wiklander <jens.wiklander(a)linaro.org> wrote:
> > >
> > > Hi,
> > >
> > > On Thu, Feb 13, 2025 at 6:39 PM Daniel Stone <daniel(a)fooishbar.org> wrote:
> > > >
> > > > Hi,
> > > >
> > > > On Thu, 13 Feb 2025 at 15:57, Jens Wiklander <jens.wiklander(a)linaro.org> wrote:
> > > > > On Thu, Feb 13, 2025 at 3:05 PM Daniel Stone <daniel(a)fooishbar.org> wrote:
> > > > > > But just because TEE is one good backend implementation, doesn't mean
> > > > > > it should be the userspace ABI. Why should userspace care that TEE has
> > > > > > mediated the allocation instead of it being a predefined range within
> > > > > > DT?
> > > > >
> > > > > The TEE may very well use a predefined range that part is abstracted
> > > > > with the interface.
> > > >
> > > > Of course. But you can also (and this has been shipped on real
> > > > devices) handle this without any per-allocation TEE needs by simply
> > > > allocating from a memory range which is predefined within DT.
> > > >
> > > > From the userspace point of view, why should there be one ABI to
> > > > allocate memory from a predefined range which is delivered by DT to
> > > > the kernel, and one ABI to allocate memory from a predefined range
> > > > which is mediated by TEE?
> > >
> > > We need some way to specify the protection profile (or use case as
> > > I've called it in the ABI) required for the buffer. Whether it's
> > > defined in DT seems irrelevant.
> > >
> > > >
> > > > > > What advantage
> > > > > > does userspace get from having to have a different codepath to get a
> > > > > > different handle to memory? What about x86?
> > > > > >
> > > > > > I think this proposal is looking at it from the wrong direction.
> > > > > > Instead of working upwards from the implementation to userspace, start
> > > > > > with userspace and work downwards. The interesting property to focus
> > > > > > on is allocating memory, not that EL1 is involved behind the scenes.
> > > > >
> > > > > From what I've gathered from earlier discussions, it wasn't much of a
> > > > > problem for userspace to handle this. If the kernel were to provide it
> > > > > via a different ABI, how would it be easier to implement in the
> > > > > kernel? I think we need an example to understand your suggestion.
> > > >
> > > > It is a problem for userspace, because we need to expose acceptable
> > > > parameters for allocation through the entire stack. If you look at the
> > > > dmabuf documentation in the kernel for how buffers should be allocated
> > > > and exchanged, you can see the negotiation flow for modifiers. This
> > > > permeates through KMS, EGL, Vulkan, Wayland, GStreamer, and more.
> > >
> > > What dma-buf properties are you referring to?
> > > dma_heap_ioctl_allocate() accepts a few flags for the resulting file
> > > descriptor and no flags for the heap itself.
> > >
> > > >
> > > > Standardising on heaps allows us to add those in a similar way.
> > >
> > > How would you solve this with heaps? Would you use one heap for each
> > > protection profile (use case), add heap_flags, or do a bit of both?
>
> I would say one heap per-profile.
>
And then it would have a per vendor multiplication factor as each
vendor enforces memory restriction in a platform specific manner which
won't scale.
> >
> > Christian gave an historical background here [1] as to why that hasn't
> > worked in the past with DMA heaps given the scalability issues.
> >
> > [1] https://lore.kernel.org/dri-devel/e967e382-6cca-4dee-8333-39892d532f71@gmai…
>
> Hm, I fail to see where Christian dismiss the dma-heaps solution in
> this email. He even says:
>
> > If the memory is not physically attached to any device, but rather just
> memory attached to the CPU or a system wide memory controller then
> expose the memory as DMA-heap with specific requirements (e.g. certain
> sized pages, contiguous, restricted, encrypted, ...).
I am not saying Christian dismissed DMA heaps but rather how
scalability is an issue. What we are proposing here is a generic
interface via TEE to the firmware/Trusted OS which can perform all the
platform specific memory restrictions. This solution will scale across
vendors.
>
> >
> > >
> > > > If we
> > > > have to add different allocation mechanisms, then the complexity
> > > > increases, permeating not only into all the different userspace APIs,
> > > > but also into the drivers which need to support every different
> > > > allocation mechanism even if they have no opinion on it - e.g. Mali
> > > > doesn't care in any way whether the allocation comes from a heap or
> > > > TEE or ACPI or whatever, it cares only that the memory is protected.
> > > >
> > > > Does that help?
> > >
> > > I think you're missing the stage where an unprotected buffer is
> > > received and decrypted into a protected buffer. If you use the TEE for
> > > decryption or to configure the involved devices for the use case, it
> > > makes sense to let the TEE allocate the buffers, too. A TEE doesn't
> > > have to be an OS in the secure world, it can be an abstraction to
> > > support the use case depending on the design. So the restricted buffer
> > > is already allocated before we reach Mali in your example.
> > >
> > > Allocating restricted buffers from the TEE subsystem saves us from
> > > maintaining proxy dma-buf heaps.
>
> Honestly, when I look at dma-heap implementations, they seem
> to be trivial shells around existing (more complex) allocators, and the
> boiler plate [1] to expose a dma-heap is relatively small. The dma-buf
> implementation, you already have, so we're talking about a hundred
> lines of code to maintain, which shouldn't be significantly more than
> what you have for the new ioctl() to be honest.
It will rather be redundant vendor specific code under DMA heaps
calling into firmware/Trusted OS to enforce memory restrictions as you
can look into Mediatek example [1]. With TEE subsystem managing that
it won't be the case as we will provide a common abstraction for the
communication with underlying firmware/Trusted OS.
[1] https://lore.kernel.org/linux-arm-kernel/20240515112308.10171-1-yong.wu@med…
> And I'll insist on what
> Daniel said, it's a small price to pay to have a standard interface to
> expose to userspace. If dma-heaps are not used for this kind things, I
> honestly wonder what they will be used for...
Let's try not to forcefully find a use-case for DMA heaps when there
is a better alternative available. I am still failing to see why you
don't consider following as a standardised user-space interface:
"When user-space has to work with restricted memory, ask TEE device to
allocate it"
-Sumit
11 months, 2 weeks
- 3
- 4
Re: [PATCH v2 1/7] dt-bindings: npu: rockchip,rknn: Add bindings
by Rob Herring
On Tue, Feb 25, 2025 at 08:55:47AM +0100, Tomeu Vizoso wrote:
> Add the bindings for the Neural Processing Unit IP from Rockchip.
>
> v2:
> - Adapt to new node structure (one node per core, each with its own
> IOMMU)
> - Several misc. fixes from Sebastian Reichel
>
> Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net>
> Signed-off-by: Sebastian Reichel <sebastian.reichel(a)collabora.com>
> ---
> .../bindings/npu/rockchip,rknn-core.yaml | 152 +++++++++++++++++++++
> 1 file changed, 152 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..e8d0afe4a7d1c4f166cf13a9f4aa7c1901362a3f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/npu/rockchip,rknn-core.yaml
> @@ -0,0 +1,152 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/npu/rockchip,rknn-core.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Neural Processing Unit IP from Rockchip
> +
> +maintainers:
> + - Tomeu Vizoso <tomeu(a)tomeuvizoso.net>
> +
> +description:
> + Rockchip IP for accelerating inference of neural networks, based on NVIDIA's
> + open source NVDLA IP.
> +
> +properties:
> + $nodename:
> + pattern: '^npu-core@[a-f0-9]+$'
> +
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - rockchip,rk3588-rknn-core-top
> + - const: rockchip,rknn-core-top
Drop the fallbacks unless you have some evidence that the IP is the
same across a lot of SoCs. If you don't, then
rockchip,rk3588-rknn-core-top can be the fallback whenever there are
more compatible SoCs.
Or if there's version/feature registers that otherwise make it
discoverable, then a common compatible is fine.
> + - items:
> + - enum:
> + - rockchip,rk3588-rknn-core
> + - const: rockchip,rknn-core
I don't understand the difference between core and core-top. That needs
to be explained in the top-level description.
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> + maxItems: 4
> +
> + clock-names:
> + items:
> + - const: aclk
> + - const: hclk
> + - const: npu
> + - const: pclk
> + minItems: 2
> +
> + interrupts:
> + maxItems: 1
> +
> + iommus:
> + maxItems: 1
> +
> + npu-supply: true
> +
> + power-domains:
> + maxItems: 1
> +
> + resets:
> + maxItems: 2
> +
> + reset-names:
> + items:
> + - const: srst_a
> + - const: srst_h
> +
> + sram-supply: true
Group supply properties together
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - iommus
> + - npu-supply
> + - power-domains
> + - resets
> + - reset-names
> + - sram-supply
> +
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - rockchip,rknn-core-top
> + then:
> + properties:
> + clocks:
> + minItems: 4
> +
> + clock-names:
> + minItems: 4
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - rockchip,rknn-core
> + then:
> + properties:
> + clocks:
> + maxItems: 2
> + clock-names:
> + maxItems: 2
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/rockchip,rk3588-cru.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/power/rk3588-power.h>
> + #include <dt-bindings/reset/rockchip,rk3588-cru.h>
> +
> + bus {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + rknn_core_top: npu-core@fdab0000 {
npu@...
> + compatible = "rockchip,rk3588-rknn-core-top", "rockchip,rknn-core-top";
> + reg = <0x0 0xfdab0000 0x0 0x9000>;
> + assigned-clocks = <&scmi_clk SCMI_CLK_NPU>;
> + assigned-clock-rates = <200000000>;
> + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>,
> + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>;
> + clock-names = "aclk", "hclk", "npu", "pclk";
> + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&rknn_mmu_top>;
> + npu-supply = <&vdd_npu_s0>;
> + power-domains = <&power RK3588_PD_NPUTOP>;
> + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>;
> + reset-names = "srst_a", "srst_h";
> + sram-supply = <&vdd_npu_mem_s0>;
> + };
> +
> + rknn_core_1: npu-core@fdac0000 {
> + compatible = "rockchip,rk3588-rknn-core", "rockchip,rknn-core";
> + reg = <0x0 0xfdac0000 0x0 0x9000>;
> + clocks = <&cru ACLK_NPU1>, <&cru HCLK_NPU1>;
> + clock-names = "aclk", "hclk";
> + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&rknn_mmu_1>;
> + npu-supply = <&vdd_npu_s0>;
> + power-domains = <&power RK3588_PD_NPU1>;
> + resets = <&cru SRST_A_RKNN1>, <&cru SRST_H_RKNN1>;
> + reset-names = "srst_a", "srst_h";
> + sram-supply = <&vdd_npu_mem_s0>;
> + };
> + };
> +...
>
> --
> 2.48.1
>
11 months, 3 weeks
- 1
- 0
Re: [PATCH v2 6/7] accel/rocket: Add job submission IOCTL
by Thomas Zimmermann
Hi
Am 25.02.25 um 08:55 schrieb Tomeu Vizoso:
> Using the DRM GPU scheduler infrastructure, with a scheduler for each
> core.
>
> Userspace can decide for a series of tasks to be executed sequentially
> in the same core, so SRAM locality can be taken advantage of.
>
> The job submission code was initially based on Panfrost.
>
> v2:
> - Remove hardcoded number of cores
> - Misc. style fixes (Jeffrey Hugo)
> - Repack IOCTL struct (Jeffrey Hugo)
>
> Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net>
> ---
> drivers/accel/rocket/Makefile | 3 +-
> drivers/accel/rocket/rocket_core.c | 6 +
> drivers/accel/rocket/rocket_core.h | 14 +
> drivers/accel/rocket/rocket_device.c | 2 +
> drivers/accel/rocket/rocket_device.h | 2 +
> drivers/accel/rocket/rocket_drv.c | 15 +
> drivers/accel/rocket/rocket_drv.h | 4 +
> drivers/accel/rocket/rocket_job.c | 710 +++++++++++++++++++++++++++++++++++
> drivers/accel/rocket/rocket_job.h | 50 +++
> include/uapi/drm/rocket_accel.h | 55 +++
> 10 files changed, 860 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/accel/rocket/Makefile b/drivers/accel/rocket/Makefile
> index 875cac2243d902694e0d5d05e60b4ae551a633c4..4d59036af8d9c213d3cac0559eb66e3ebb0320e7 100644
> --- a/drivers/accel/rocket/Makefile
> +++ b/drivers/accel/rocket/Makefile
> @@ -6,4 +6,5 @@ rocket-y := \
> rocket_core.o \
> rocket_device.o \
> rocket_drv.o \
> - rocket_gem.o
> + rocket_gem.o \
> + rocket_job.o
> diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rocket_core.c
> index 09d966c826b5b1090a18cb24b3aa4aba286a12d4..2b522592693874eed90463e8f85653d5282ae5b8 100644
> --- a/drivers/accel/rocket/rocket_core.c
> +++ b/drivers/accel/rocket/rocket_core.c
> @@ -6,6 +6,7 @@
> #include <linux/pm_runtime.h>
>
> #include "rocket_core.h"
> +#include "rocket_job.h"
> #include "rocket_registers.h"
>
> static int rocket_clk_init(struct rocket_core *core)
> @@ -48,6 +49,10 @@ int rocket_core_init(struct rocket_core *core)
> if (IS_ERR(core->iomem))
> return PTR_ERR(core->iomem);
>
> + err = rocket_job_init(core);
> + if (err)
> + return err;
> +
> pm_runtime_use_autosuspend(dev);
> pm_runtime_set_autosuspend_delay(dev, 50); /* ~3 frames */
> pm_runtime_enable(dev);
> @@ -68,4 +73,5 @@ int rocket_core_init(struct rocket_core *core)
> void rocket_core_fini(struct rocket_core *core)
> {
> pm_runtime_disable(core->dev);
> + rocket_job_fini(core);
> }
> diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rocket_core.h
> index 2171eba7139ccc63fe24802dc81b4adb7f3abf31..045a46a2010a2ffd6122ed86c379e5fabc70365a 100644
> --- a/drivers/accel/rocket/rocket_core.h
> +++ b/drivers/accel/rocket/rocket_core.h
> @@ -21,6 +21,20 @@ struct rocket_core {
> void __iomem *iomem;
> struct clk *a_clk;
> struct clk *h_clk;
> +
> + struct rocket_job *in_flight_job;
> +
> + spinlock_t job_lock;
> +
> + struct {
> + struct workqueue_struct *wq;
> + struct work_struct work;
> + atomic_t pending;
> + } reset;
> +
> + struct drm_gpu_scheduler sched;
> + u64 fence_context;
> + u64 emit_seqno;
> };
>
> int rocket_core_init(struct rocket_core *core);
> diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/rocket_device.c
> index 9af36357caba7148dcac764c8222699f3b572d60..62c640e1e0200fe25b6834e45d71f6de139ff3ab 100644
> --- a/drivers/accel/rocket/rocket_device.c
> +++ b/drivers/accel/rocket/rocket_device.c
> @@ -12,6 +12,7 @@ int rocket_device_init(struct rocket_device *rdev)
> int err;
>
> mutex_init(&rdev->iommu_lock);
> + mutex_init(&rdev->sched_lock);
>
> rdev->clk_npu = devm_clk_get(dev, "npu");
> rdev->pclk = devm_clk_get(dev, "pclk");
> @@ -29,5 +30,6 @@ int rocket_device_init(struct rocket_device *rdev)
> void rocket_device_fini(struct rocket_device *rdev)
> {
> rocket_core_fini(&rdev->cores[0]);
> + mutex_destroy(&rdev->sched_lock);
> mutex_destroy(&rdev->iommu_lock);
> }
> diff --git a/drivers/accel/rocket/rocket_device.h b/drivers/accel/rocket/rocket_device.h
> index c6152569fdd9e5587c8e8d7b0d7c2e2a77af6000..4168ae8da2d38c2ea114b37c6e053b02611a0232 100644
> --- a/drivers/accel/rocket/rocket_device.h
> +++ b/drivers/accel/rocket/rocket_device.h
> @@ -11,6 +11,8 @@
> struct rocket_device {
> struct drm_device ddev;
>
> + struct mutex sched_lock;
> +
> struct clk *clk_npu;
> struct clk *pclk;
>
> diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
> index e5612b52952fa7a0cd0af02aef314984bc483b05..a6b486e2d4f648d7b1d8831590b633bf661c7bc4 100644
> --- a/drivers/accel/rocket/rocket_drv.c
> +++ b/drivers/accel/rocket/rocket_drv.c
> @@ -16,12 +16,14 @@
>
> #include "rocket_drv.h"
> #include "rocket_gem.h"
> +#include "rocket_job.h"
>
> static int
> rocket_open(struct drm_device *dev, struct drm_file *file)
> {
> struct rocket_device *rdev = to_rocket_device(dev);
> struct rocket_file_priv *rocket_priv;
> + int ret;
>
> rocket_priv = kzalloc(sizeof(*rocket_priv), GFP_KERNEL);
> if (!rocket_priv)
> @@ -30,7 +32,15 @@ rocket_open(struct drm_device *dev, struct drm_file *file)
> rocket_priv->rdev = rdev;
> file->driver_priv = rocket_priv;
>
> + ret = rocket_job_open(rocket_priv);
> + if (ret)
> + goto err_free;
> +
> return 0;
> +
> +err_free:
> + kfree(rocket_priv);
> + return ret;
> }
>
> static void
> @@ -38,6 +48,7 @@ rocket_postclose(struct drm_device *dev, struct drm_file *file)
> {
> struct rocket_file_priv *rocket_priv = file->driver_priv;
>
> + rocket_job_close(rocket_priv);
> kfree(rocket_priv);
> }
>
> @@ -46,6 +57,7 @@ static const struct drm_ioctl_desc rocket_drm_driver_ioctls[] = {
> DRM_IOCTL_DEF_DRV(ROCKET_##n, rocket_ioctl_##func, 0)
>
> ROCKET_IOCTL(CREATE_BO, create_bo),
> + ROCKET_IOCTL(SUBMIT, submit),
> };
>
> DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
> @@ -245,6 +257,9 @@ static int rocket_device_runtime_suspend(struct device *dev)
> if (dev != rdev->cores[core].dev)
> continue;
>
> + if (!rocket_job_is_idle(&rdev->cores[core]))
> + return -EBUSY;
> +
> clk_disable_unprepare(rdev->cores[core].a_clk);
> clk_disable_unprepare(rdev->cores[core].h_clk);
>
> diff --git a/drivers/accel/rocket/rocket_drv.h b/drivers/accel/rocket/rocket_drv.h
> index ccdd50c69d4c033eea18cb800407fdcfb3bf2e9b..54e21a61006057aee293496016e54b495a2f6d55 100644
> --- a/drivers/accel/rocket/rocket_drv.h
> +++ b/drivers/accel/rocket/rocket_drv.h
> @@ -4,10 +4,14 @@
> #ifndef __ROCKET_DRV_H__
> #define __ROCKET_DRV_H__
>
> +#include <drm/gpu_scheduler.h>
> +
> #include "rocket_device.h"
>
> struct rocket_file_priv {
> struct rocket_device *rdev;
> +
> + struct drm_sched_entity sched_entity;
> };
>
> #endif
> diff --git a/drivers/accel/rocket/rocket_job.c b/drivers/accel/rocket/rocket_job.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..25b31f28e932aaee86173b9a0962932c9c640c03
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_job.c
> @@ -0,0 +1,710 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2019 Linaro, Ltd, Rob Herring <robh(a)kernel.org> */
> +/* Copyright 2019 Collabora ltd. */
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#include <drm/drm_file.h>
> +#include <drm/drm_gem.h>
> +#include <drm/rocket_accel.h>
> +#include <linux/interrupt.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "rocket_core.h"
> +#include "rocket_device.h"
> +#include "rocket_drv.h"
> +#include "rocket_job.h"
> +#include "rocket_registers.h"
> +
> +#define JOB_TIMEOUT_MS 500
> +
> +#define job_write(dev, reg, data) writel(data, dev->iomem + (reg))
> +#define job_read(dev, reg) readl(dev->iomem + (reg))
> +
> +static struct rocket_job *
> +to_rocket_job(struct drm_sched_job *sched_job)
> +{
> + return container_of(sched_job, struct rocket_job, base);
> +}
> +
> +struct rocket_fence {
> + struct dma_fence base;
> + struct drm_device *dev;
> + /* rocket seqno for signaled() test */
> + u64 seqno;
> + int queue;
> +};
> +
> +static inline struct rocket_fence *
> +to_rocket_fence(struct dma_fence *fence)
> +{
> + return (struct rocket_fence *)fence;
Proper upcast with container_of() please.
> +}
> +
> +static const char *rocket_fence_get_driver_name(struct dma_fence *fence)
> +{
> + return "rocket";
> +}
> +
> +static const char *rocket_fence_get_timeline_name(struct dma_fence *fence)
> +{
> + return "rockchip-npu";
> +}
> +
> +static const struct dma_fence_ops rocket_fence_ops = {
> + .get_driver_name = rocket_fence_get_driver_name,
> + .get_timeline_name = rocket_fence_get_timeline_name,
> +};
> +
> +static struct dma_fence *rocket_fence_create(struct rocket_core *core)
> +{
> + struct rocket_device *rdev = core->rdev;
> + struct rocket_fence *fence;
> +
> + fence = kzalloc(sizeof(*fence), GFP_KERNEL);
> + if (!fence)
> + return ERR_PTR(-ENOMEM);
> +
> + fence->dev = &rdev->ddev;
> + fence->seqno = ++core->emit_seqno;
> + dma_fence_init(&fence->base, &rocket_fence_ops, &core->job_lock,
> + core->fence_context, fence->seqno);
> +
> + return &fence->base;
> +}
> +
> +static int
> +rocket_copy_tasks(struct drm_device *dev,
> + struct drm_file *file_priv,
> + struct drm_rocket_job *job,
> + struct rocket_job *rjob)
> +{
> + struct drm_rocket_task *tasks;
> + int ret = 0;
> + int i;
> +
> + rjob->task_count = job->task_count;
> +
> + if (!rjob->task_count)
> + return 0;
> +
> + tasks = kvmalloc_array(rjob->task_count, sizeof(*tasks), GFP_KERNEL);
> + if (!tasks) {
> + ret = -ENOMEM;
> + DRM_DEBUG("Failed to allocate incoming tasks\n");
These logging macros are deprecated. Please use drm_dbg() and similar
functions instead. Here and everywhere else.
> + goto fail;
> + }
> +
> + if (copy_from_user(tasks,
> + (void __user *)(uintptr_t)job->tasks,
> + rjob->task_count * sizeof(*tasks))) {
> + ret = -EFAULT;
> + DRM_DEBUG("Failed to copy incoming tasks\n");
> + goto fail;
> + }
> +
> + rjob->tasks = kvmalloc_array(job->task_count, sizeof(*rjob->tasks), GFP_KERNEL);
> + if (!rjob->tasks) {
> + DRM_DEBUG("Failed to allocate task array\n");
> + ret = -ENOMEM;
> + goto fail;
> + }
> +
> + for (i = 0; i < rjob->task_count; i++) {
> + if (tasks[i].regcmd_count == 0) {
> + ret = -EINVAL;
> + goto fail;
> + }
> + rjob->tasks[i].regcmd = tasks[i].regcmd;
> + rjob->tasks[i].regcmd_count = tasks[i].regcmd_count;
> + }
> +
> +fail:
> + kvfree(tasks);
> + return ret;
> +}
> +
> +static void rocket_job_hw_submit(struct rocket_core *core, struct rocket_job *job)
> +{
> + struct rocket_task *task;
> + bool task_pp_en = 1;
> + bool task_count = 1;
> +
> + /* GO ! */
> +
> + /* Don't queue the job if a reset is in progress */
> + if (!atomic_read(&core->reset.pending)) {
> +
> + task = &job->tasks[job->next_task_idx];
> + job->next_task_idx++; /* TODO: Do this only after a successful run? */
> +
> + rocket_write(core, REG_PC_BASE_ADDRESS, 0x1);
Just 'write' seems a little imprecise. Maybe 'writel' would be better.
Best regards
Thomas
> +
> + rocket_write(core, REG_CNA_S_POINTER, 0xe + 0x10000000 * core->index);
> + rocket_write(core, REG_CORE_S_POINTER, 0xe + 0x10000000 * core->index);
> +
> + rocket_write(core, REG_PC_BASE_ADDRESS, task->regcmd);
> + rocket_write(core, REG_PC_REGISTER_AMOUNTS, (task->regcmd_count + 1) / 2 - 1);
> +
> + rocket_write(core, REG_PC_INTERRUPT_MASK,
> + PC_INTERRUPT_MASK_DPU_0 | PC_INTERRUPT_MASK_DPU_1);
> + rocket_write(core, REG_PC_INTERRUPT_CLEAR,
> + PC_INTERRUPT_CLEAR_DPU_0 | PC_INTERRUPT_CLEAR_DPU_1);
> +
> + rocket_write(core, REG_PC_TASK_CON, ((0x6 | task_pp_en) << 12) | task_count);
> +
> + rocket_write(core, REG_PC_TASK_DMA_BASE_ADDR, 0x0);
> +
> + rocket_write(core, REG_PC_OPERATION_ENABLE, 0x1);
> +
> + dev_dbg(core->dev,
> + "Submitted regcmd at 0x%llx to core %d",
> + task->regcmd, core->index);
> + }
> +}
> +
> +static int rocket_acquire_object_fences(struct drm_gem_object **bos,
> + int bo_count,
> + struct drm_sched_job *job,
> + bool is_write)
> +{
> + int i, ret;
> +
> + for (i = 0; i < bo_count; i++) {
> + ret = dma_resv_reserve_fences(bos[i]->resv, 1);
> + if (ret)
> + return ret;
> +
> + ret = drm_sched_job_add_implicit_dependencies(job, bos[i],
> + is_write);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void rocket_attach_object_fences(struct drm_gem_object **bos,
> + int bo_count,
> + struct dma_fence *fence)
> +{
> + int i;
> +
> + for (i = 0; i < bo_count; i++)
> + dma_resv_add_fence(bos[i]->resv, fence, DMA_RESV_USAGE_WRITE);
> +}
> +
> +static int rocket_job_push(struct rocket_job *job)
> +{
> + struct rocket_device *rdev = job->rdev;
> + struct drm_gem_object **bos;
> + struct ww_acquire_ctx acquire_ctx;
> + int ret = 0;
> +
> + bos = kvmalloc_array(job->in_bo_count + job->out_bo_count, sizeof(void *),
> + GFP_KERNEL);
> + memcpy(bos, job->in_bos, job->in_bo_count * sizeof(void *));
> + memcpy(&bos[job->in_bo_count], job->out_bos, job->out_bo_count * sizeof(void *));
> +
> + ret = drm_gem_lock_reservations(bos, job->in_bo_count + job->out_bo_count, &acquire_ctx);
> + if (ret)
> + goto err;
> +
> + mutex_lock(&rdev->sched_lock);
> + drm_sched_job_arm(&job->base);
> +
> + job->inference_done_fence = dma_fence_get(&job->base.s_fence->finished);
> +
> + ret = rocket_acquire_object_fences(job->in_bos, job->in_bo_count, &job->base, false);
> + if (ret) {
> + mutex_unlock(&rdev->sched_lock);
> + goto err_unlock;
> + }
> +
> + ret = rocket_acquire_object_fences(job->out_bos, job->out_bo_count, &job->base, true);
> + if (ret) {
> + mutex_unlock(&rdev->sched_lock);
> + goto err_unlock;
> + }
> +
> + kref_get(&job->refcount); /* put by scheduler job completion */
> +
> + drm_sched_entity_push_job(&job->base);
> +
> + mutex_unlock(&rdev->sched_lock);
> +
> + rocket_attach_object_fences(job->out_bos, job->out_bo_count, job->inference_done_fence);
> +
> +err_unlock:
> + drm_gem_unlock_reservations(bos, job->in_bo_count + job->out_bo_count, &acquire_ctx);
> +err:
> + kfree(bos);
> +
> + return ret;
> +}
> +
> +static void rocket_job_cleanup(struct kref *ref)
> +{
> + struct rocket_job *job = container_of(ref, struct rocket_job,
> + refcount);
> + unsigned int i;
> +
> + dma_fence_put(job->done_fence);
> + dma_fence_put(job->inference_done_fence);
> +
> + if (job->in_bos) {
> + for (i = 0; i < job->in_bo_count; i++)
> + drm_gem_object_put(job->in_bos[i]);
> +
> + kvfree(job->in_bos);
> + }
> +
> + if (job->out_bos) {
> + for (i = 0; i < job->out_bo_count; i++)
> + drm_gem_object_put(job->out_bos[i]);
> +
> + kvfree(job->out_bos);
> + }
> +
> + kfree(job->tasks);
> +
> + kfree(job);
> +}
> +
> +static void rocket_job_put(struct rocket_job *job)
> +{
> + kref_put(&job->refcount, rocket_job_cleanup);
> +}
> +
> +static void rocket_job_free(struct drm_sched_job *sched_job)
> +{
> + struct rocket_job *job = to_rocket_job(sched_job);
> +
> + drm_sched_job_cleanup(sched_job);
> +
> + rocket_job_put(job);
> +}
> +
> +static struct rocket_core *sched_to_core(struct rocket_device *rdev,
> + struct drm_gpu_scheduler *sched)
> +{
> + unsigned int core;
> +
> + for (core = 0; core < rdev->num_cores; core++) {
> + if (&rdev->cores[core].sched == sched)
> + return &rdev->cores[core];
> + }
> +
> + return NULL;
> +}
> +
> +static struct dma_fence *rocket_job_run(struct drm_sched_job *sched_job)
> +{
> + struct rocket_job *job = to_rocket_job(sched_job);
> + struct rocket_device *rdev = job->rdev;
> + struct rocket_core *core = sched_to_core(rdev, sched_job->sched);
> + struct dma_fence *fence = NULL;
> + int ret;
> +
> + if (unlikely(job->base.s_fence->finished.error))
> + return NULL;
> +
> + /*
> + * Nothing to execute: can happen if the job has finished while
> + * we were resetting the GPU.
> + */
> + if (job->next_task_idx == job->task_count)
> + return NULL;
> +
> + fence = rocket_fence_create(core);
> + if (IS_ERR(fence))
> + return fence;
> +
> + if (job->done_fence)
> + dma_fence_put(job->done_fence);
> + job->done_fence = dma_fence_get(fence);
> +
> + ret = pm_runtime_get_sync(core->dev);
> + if (ret < 0)
> + return fence;
> +
> + spin_lock(&core->job_lock);
> +
> + core->in_flight_job = job;
> + rocket_job_hw_submit(core, job);
> +
> + spin_unlock(&core->job_lock);
> +
> + return fence;
> +}
> +
> +static void rocket_job_handle_done(struct rocket_core *core,
> + struct rocket_job *job)
> +{
> + if (job->next_task_idx < job->task_count) {
> + rocket_job_hw_submit(core, job);
> + return;
> + }
> +
> + core->in_flight_job = NULL;
> + dma_fence_signal_locked(job->done_fence);
> + pm_runtime_put_autosuspend(core->dev);
> +}
> +
> +static void rocket_job_handle_irq(struct rocket_core *core)
> +{
> + uint32_t status, raw_status;
> +
> + pm_runtime_mark_last_busy(core->dev);
> +
> + status = rocket_read(core, REG_PC_INTERRUPT_STATUS);
> + raw_status = rocket_read(core, REG_PC_INTERRUPT_RAW_STATUS);
> +
> + rocket_write(core, REG_PC_OPERATION_ENABLE, 0x0);
> + rocket_write(core, REG_PC_INTERRUPT_CLEAR, 0x1ffff);
> +
> + spin_lock(&core->job_lock);
> +
> + if (core->in_flight_job)
> + rocket_job_handle_done(core, core->in_flight_job);
> +
> + spin_unlock(&core->job_lock);
> +}
> +
> +static void
> +rocket_reset(struct rocket_core *core, struct drm_sched_job *bad)
> +{
> + bool cookie;
> +
> + if (!atomic_read(&core->reset.pending))
> + return;
> +
> + /*
> + * Stop the scheduler.
> + *
> + * FIXME: We temporarily get out of the dma_fence_signalling section
> + * because the cleanup path generate lockdep splats when taking locks
> + * to release job resources. We should rework the code to follow this
> + * pattern:
> + *
> + * try_lock
> + * if (locked)
> + * release
> + * else
> + * schedule_work_to_release_later
> + */
> + drm_sched_stop(&core->sched, bad);
> +
> + cookie = dma_fence_begin_signalling();
> +
> + if (bad)
> + drm_sched_increase_karma(bad);
> +
> + /*
> + * Mask job interrupts and synchronize to make sure we won't be
> + * interrupted during our reset.
> + */
> + rocket_write(core, REG_PC_INTERRUPT_MASK, 0x0);
> + synchronize_irq(core->irq);
> +
> + /* Handle the remaining interrupts before we reset. */
> + rocket_job_handle_irq(core);
> +
> + /*
> + * Remaining interrupts have been handled, but we might still have
> + * stuck jobs. Let's make sure the PM counters stay balanced by
> + * manually calling pm_runtime_put_noidle() and
> + * rocket_devfreq_record_idle() for each stuck job.
> + * Let's also make sure the cycle counting register's refcnt is
> + * kept balanced to prevent it from running forever
> + */
> + spin_lock(&core->job_lock);
> + if (core->in_flight_job)
> + pm_runtime_put_noidle(core->dev);
> +
> + core->in_flight_job = NULL;
> + spin_unlock(&core->job_lock);
> +
> + /* Proceed with reset now. */
> + pm_runtime_force_suspend(core->dev);
> + pm_runtime_force_resume(core->dev);
> +
> + /* GPU has been reset, we can clear the reset pending bit. */
> + atomic_set(&core->reset.pending, 0);
> +
> + /*
> + * Now resubmit jobs that were previously queued but didn't have a
> + * chance to finish.
> + * FIXME: We temporarily get out of the DMA fence signalling section
> + * while resubmitting jobs because the job submission logic will
> + * allocate memory with the GFP_KERNEL flag which can trigger memory
> + * reclaim and exposes a lock ordering issue.
> + */
> + dma_fence_end_signalling(cookie);
> + drm_sched_resubmit_jobs(&core->sched);
> + cookie = dma_fence_begin_signalling();
> +
> + /* Restart the scheduler */
> + drm_sched_start(&core->sched, 0);
> +
> + dma_fence_end_signalling(cookie);
> +}
> +
> +static enum drm_gpu_sched_stat rocket_job_timedout(struct drm_sched_job *sched_job)
> +{
> + struct rocket_job *job = to_rocket_job(sched_job);
> + struct rocket_device *rdev = job->rdev;
> + struct rocket_core *core = sched_to_core(rdev, sched_job->sched);
> +
> + /*
> + * If the GPU managed to complete this jobs fence, the timeout is
> + * spurious. Bail out.
> + */
> + if (dma_fence_is_signaled(job->done_fence))
> + return DRM_GPU_SCHED_STAT_NOMINAL;
> +
> + /*
> + * Rocket IRQ handler may take a long time to process an interrupt
> + * if there is another IRQ handler hogging the processing.
> + * For example, the HDMI encoder driver might be stuck in the IRQ
> + * handler for a significant time in a case of bad cable connection.
> + * In order to catch such cases and not report spurious rocket
> + * job timeouts, synchronize the IRQ handler and re-check the fence
> + * status.
> + */
> + synchronize_irq(core->irq);
> +
> + if (dma_fence_is_signaled(job->done_fence)) {
> + dev_warn(core->dev, "unexpectedly high interrupt latency\n");
> + return DRM_GPU_SCHED_STAT_NOMINAL;
> + }
> +
> + dev_err(core->dev, "gpu sched timeout");
> +
> + atomic_set(&core->reset.pending, 1);
> + rocket_reset(core, sched_job);
> +
> + return DRM_GPU_SCHED_STAT_NOMINAL;
> +}
> +
> +static void rocket_reset_work(struct work_struct *work)
> +{
> + struct rocket_core *core;
> +
> + core = container_of(work, struct rocket_core, reset.work);
> + rocket_reset(core, NULL);
> +}
> +
> +static const struct drm_sched_backend_ops rocket_sched_ops = {
> + .run_job = rocket_job_run,
> + .timedout_job = rocket_job_timedout,
> + .free_job = rocket_job_free
> +};
> +
> +static irqreturn_t rocket_job_irq_handler_thread(int irq, void *data)
> +{
> + struct rocket_core *core = data;
> +
> + rocket_job_handle_irq(core);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static irqreturn_t rocket_job_irq_handler(int irq, void *data)
> +{
> + struct rocket_core *core = data;
> + uint32_t raw_status = rocket_read(core, REG_PC_INTERRUPT_RAW_STATUS);
> +
> + WARN_ON(raw_status & PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR);
> + WARN_ON(raw_status & PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR);
> +
> + if (!(raw_status & PC_INTERRUPT_RAW_STATUS_DPU_0 ||
> + raw_status & PC_INTERRUPT_RAW_STATUS_DPU_1))
> + return IRQ_NONE;
> +
> + rocket_write(core, REG_PC_INTERRUPT_MASK, 0x0);
> +
> + return IRQ_WAKE_THREAD;
> +}
> +
> +int rocket_job_init(struct rocket_core *core)
> +{
> + int ret;
> +
> + INIT_WORK(&core->reset.work, rocket_reset_work);
> + spin_lock_init(&core->job_lock);
> +
> + core->irq = platform_get_irq(to_platform_device(core->dev), 0);
> + if (core->irq < 0)
> + return core->irq;
> +
> + ret = devm_request_threaded_irq(core->dev, core->irq,
> + rocket_job_irq_handler,
> + rocket_job_irq_handler_thread,
> + IRQF_SHARED, KBUILD_MODNAME "-job",
> + core);
> + if (ret) {
> + dev_err(core->dev, "failed to request job irq");
> + return ret;
> + }
> +
> + core->reset.wq = alloc_ordered_workqueue("rocket-reset-%d", 0, core->index);
> + if (!core->reset.wq)
> + return -ENOMEM;
> +
> + core->fence_context = dma_fence_context_alloc(1);
> +
> + ret = drm_sched_init(&core->sched,
> + &rocket_sched_ops, NULL,
> + DRM_SCHED_PRIORITY_COUNT,
> + 1, 0,
> + msecs_to_jiffies(JOB_TIMEOUT_MS),
> + core->reset.wq,
> + NULL, "rocket", core->dev);
> + if (ret) {
> + dev_err(core->dev, "Failed to create scheduler: %d.", ret);
> + goto err_sched;
> + }
> +
> + return 0;
> +
> +err_sched:
> + drm_sched_fini(&core->sched);
> +
> + destroy_workqueue(core->reset.wq);
> + return ret;
> +}
> +
> +void rocket_job_fini(struct rocket_core *core)
> +{
> + drm_sched_fini(&core->sched);
> +
> + cancel_work_sync(&core->reset.work);
> + destroy_workqueue(core->reset.wq);
> +}
> +
> +int rocket_job_open(struct rocket_file_priv *rocket_priv)
> +{
> + struct rocket_device *rdev = rocket_priv->rdev;
> + struct drm_gpu_scheduler **scheds = kmalloc_array(rdev->num_cores, sizeof(scheds),
> + GFP_KERNEL);
> + unsigned int core;
> + int ret;
> +
> + for (core = 0; core < rdev->num_cores; core++)
> + scheds[core] = &rdev->cores[core].sched;
> +
> + ret = drm_sched_entity_init(&rocket_priv->sched_entity,
> + DRM_SCHED_PRIORITY_NORMAL,
> + scheds,
> + rdev->num_cores, NULL);
> + if (WARN_ON(ret))
> + return ret;
> +
> + return 0;
> +}
> +
> +void rocket_job_close(struct rocket_file_priv *rocket_priv)
> +{
> + struct drm_sched_entity *entity = &rocket_priv->sched_entity;
> +
> + kfree(entity->sched_list);
> + drm_sched_entity_destroy(entity);
> +}
> +
> +int rocket_job_is_idle(struct rocket_core *core)
> +{
> + /* If there are any jobs in this HW queue, we're not idle */
> + if (atomic_read(&core->sched.credit_count))
> + return false;
> +
> + return true;
> +}
> +
> +static int rocket_ioctl_submit_job(struct drm_device *dev, struct drm_file *file,
> + struct drm_rocket_job *job)
> +{
> + struct rocket_device *rdev = to_rocket_device(dev);
> + struct rocket_file_priv *file_priv = file->driver_priv;
> + struct rocket_job *rjob = NULL;
> + int ret = 0;
> +
> + if (job->task_count == 0)
> + return -EINVAL;
> +
> + rjob = kzalloc(sizeof(*rjob), GFP_KERNEL);
> + if (!rjob)
> + return -ENOMEM;
> +
> + kref_init(&rjob->refcount);
> +
> + rjob->rdev = rdev;
> +
> + ret = drm_sched_job_init(&rjob->base,
> + &file_priv->sched_entity,
> + 1, NULL);
> + if (ret)
> + goto out_put_job;
> +
> + ret = rocket_copy_tasks(dev, file, job, rjob);
> + if (ret)
> + goto out_cleanup_job;
> +
> + ret = drm_gem_objects_lookup(file,
> + (void __user *)(uintptr_t)job->in_bo_handles,
> + job->in_bo_handle_count, &rjob->in_bos);
> + if (ret)
> + goto out_cleanup_job;
> +
> + rjob->in_bo_count = job->in_bo_handle_count;
> +
> + ret = drm_gem_objects_lookup(file,
> + (void __user *)(uintptr_t)job->out_bo_handles,
> + job->out_bo_handle_count, &rjob->out_bos);
> + if (ret)
> + goto out_cleanup_job;
> +
> + rjob->out_bo_count = job->out_bo_handle_count;
> +
> + ret = rocket_job_push(rjob);
> + if (ret)
> + goto out_cleanup_job;
> +
> +out_cleanup_job:
> + if (ret)
> + drm_sched_job_cleanup(&rjob->base);
> +out_put_job:
> + rocket_job_put(rjob);
> +
> + return ret;
> +}
> +
> +int rocket_ioctl_submit(struct drm_device *dev, void *data, struct drm_file *file)
> +{
> + struct drm_rocket_submit *args = data;
> + struct drm_rocket_job *jobs;
> + int ret = 0;
> + unsigned int i = 0;
> +
> + jobs = kvmalloc_array(args->job_count, sizeof(*jobs), GFP_KERNEL);
> + if (!jobs) {
> + DRM_DEBUG("Failed to allocate incoming job array\n");
> + return -ENOMEM;
> + }
> +
> + if (copy_from_user(jobs,
> + (void __user *)(uintptr_t)args->jobs,
> + args->job_count * sizeof(*jobs))) {
> + ret = -EFAULT;
> + DRM_DEBUG("Failed to copy incoming job array\n");
> + goto exit;
> + }
> +
> + for (i = 0; i < args->job_count; i++)
> + rocket_ioctl_submit_job(dev, file, &jobs[i]);
> +
> +exit:
> + kfree(jobs);
> +
> + return ret;
> +}
> diff --git a/drivers/accel/rocket/rocket_job.h b/drivers/accel/rocket/rocket_job.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..93fa1f988c72adb7a405acbf08c1c9b87d22f9c5
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_job.h
> @@ -0,0 +1,50 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#ifndef __ROCKET_JOB_H__
> +#define __ROCKET_JOB_H__
> +
> +#include <drm/drm_drv.h>
> +#include <drm/gpu_scheduler.h>
> +
> +#include "rocket_core.h"
> +#include "rocket_drv.h"
> +
> +struct rocket_task {
> + u64 regcmd;
> + u32 regcmd_count;
> +};
> +
> +struct rocket_job {
> + struct drm_sched_job base;
> +
> + struct rocket_device *rdev;
> +
> + struct drm_gem_object **in_bos;
> + struct drm_gem_object **out_bos;
> +
> + u32 in_bo_count;
> + u32 out_bo_count;
> +
> + struct rocket_task *tasks;
> + u32 task_count;
> + u32 next_task_idx;
> +
> + /* Fence to be signaled by drm-sched once its done with the job */
> + struct dma_fence *inference_done_fence;
> +
> + /* Fence to be signaled by IRQ handler when the job is complete. */
> + struct dma_fence *done_fence;
> +
> + struct kref refcount;
> +};
> +
> +int rocket_ioctl_submit(struct drm_device *dev, void *data, struct drm_file *file);
> +
> +int rocket_job_init(struct rocket_core *core);
> +void rocket_job_fini(struct rocket_core *core);
> +int rocket_job_open(struct rocket_file_priv *rocket_priv);
> +void rocket_job_close(struct rocket_file_priv *rocket_priv);
> +int rocket_job_is_idle(struct rocket_core *core);
> +
> +#endif
> diff --git a/include/uapi/drm/rocket_accel.h b/include/uapi/drm/rocket_accel.h
> index 8338726a83c31b954608ca505cf78bcd70d3494b..eb886351134ebef62969b1e1182ccc174f88fe9d 100644
> --- a/include/uapi/drm/rocket_accel.h
> +++ b/include/uapi/drm/rocket_accel.h
> @@ -12,8 +12,10 @@ extern "C" {
> #endif
>
> #define DRM_ROCKET_CREATE_BO 0x00
> +#define DRM_ROCKET_SUBMIT 0x01
>
> #define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
> +#define DRM_IOCTL_ROCKET_SUBMIT DRM_IOW(DRM_COMMAND_BASE + DRM_ROCKET_SUBMIT, struct drm_rocket_submit)
>
> /**
> * struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
> @@ -36,6 +38,59 @@ struct drm_rocket_create_bo {
> __u64 offset;
> };
>
> +/**
> + * struct drm_rocket_task - A task to be run on the NPU
> + *
> + * A task is the smallest unit of work that can be run on the NPU.
> + */
> +struct drm_rocket_task {
> + /** DMA address to NPU mapping of register command buffer */
> + __u64 regcmd;
> +
> + /** Number of commands in the register command buffer */
> + __u32 regcmd_count;
> +};
> +
> +/**
> + * struct drm_rocket_job - A job to be run on the NPU
> + *
> + * The kernel will schedule the execution of this job taking into account its
> + * dependencies with other jobs. All tasks in the same job will be executed
> + * sequentially on the same core, to benefit from memory residency in SRAM.
> + */
> +struct drm_rocket_job {
> + /** Pointer to an array of struct drm_rocket_task. */
> + __u64 tasks;
> +
> + /** Pointer to a u32 array of the BOs that are read by the job. */
> + __u64 in_bo_handles;
> +
> + /** Pointer to a u32 array of the BOs that are written to by the job. */
> + __u64 out_bo_handles;
> +
> + /** Number of tasks passed in. */
> + __u32 task_count;
> +
> + /** Number of input BO handles passed in (size is that times 4). */
> + __u32 in_bo_handle_count;
> +
> + /** Number of output BO handles passed in (size is that times 4). */
> + __u32 out_bo_handle_count;
> +};
> +
> +/**
> + * struct drm_rocket_submit - ioctl argument for submitting commands to the NPU.
> + *
> + * The kernel will schedule the execution of these jobs in dependency order.
> + */
> +struct drm_rocket_submit {
> + /** Pointer to an array of struct drm_rocket_job. */
> + __u64 jobs;
> +
> + /** Number of jobs passed in. */
> + __u32 job_count;
> +};
> +
> #if defined(__cplusplus)
> }
> #endif
>
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
11 months, 3 weeks
- 1
- 0
Re: [PATCH v2 5/7] accel/rocket: Add IOCTL for BO creation
by Thomas Zimmermann
Hi
Am 25.02.25 um 08:55 schrieb Tomeu Vizoso:
> This uses the SHMEM DRM helpers and we map right away to the CPU and NPU
> sides, as all buffers are expected to be accessed from both.
>
> v2:
> - Sync the IOMMUs for the other cores when mapping and unmapping.
>
> Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net>
> ---
> drivers/accel/rocket/Makefile | 3 +-
> drivers/accel/rocket/rocket_device.c | 4 +
> drivers/accel/rocket/rocket_device.h | 2 +
> drivers/accel/rocket/rocket_drv.c | 7 +-
> drivers/accel/rocket/rocket_gem.c | 141 +++++++++++++++++++++++++++++++++++
> drivers/accel/rocket/rocket_gem.h | 27 +++++++
> include/uapi/drm/rocket_accel.h | 43 +++++++++++
> 7 files changed, 225 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/accel/rocket/Makefile b/drivers/accel/rocket/Makefile
> index 73a7280d260c068d37ad3048824f710482333540..875cac2243d902694e0d5d05e60b4ae551a633c4 100644
> --- a/drivers/accel/rocket/Makefile
> +++ b/drivers/accel/rocket/Makefile
> @@ -5,4 +5,5 @@ obj-$(CONFIG_DRM_ACCEL_ROCKET) := rocket.o
> rocket-y := \
> rocket_core.o \
> rocket_device.o \
> - rocket_drv.o
> + rocket_drv.o \
> + rocket_gem.o
> diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/rocket_device.c
> index ce3b533f15c1011d8a7a23dd8132e907cc334c58..9af36357caba7148dcac764c8222699f3b572d60 100644
> --- a/drivers/accel/rocket/rocket_device.c
> +++ b/drivers/accel/rocket/rocket_device.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0
> /* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
>
> +#include "linux/mutex.h"
Include with angle brackets please.
> #include <linux/clk.h>
>
> #include "rocket_device.h"
> @@ -10,6 +11,8 @@ int rocket_device_init(struct rocket_device *rdev)
> struct device *dev = rdev->cores[0].dev;
> int err;
>
> + mutex_init(&rdev->iommu_lock);
In DRM, we have drmm_mutex_init() in drm/drm_managed.h. Managed cleanup
is generally preferred.
> +
> rdev->clk_npu = devm_clk_get(dev, "npu");
> rdev->pclk = devm_clk_get(dev, "pclk");
>
> @@ -26,4 +29,5 @@ int rocket_device_init(struct rocket_device *rdev)
> void rocket_device_fini(struct rocket_device *rdev)
> {
> rocket_core_fini(&rdev->cores[0]);
> + mutex_destroy(&rdev->iommu_lock);
> }
> diff --git a/drivers/accel/rocket/rocket_device.h b/drivers/accel/rocket/rocket_device.h
> index 466edba9102c5dc5dfac5d3fcc1c904f206eaebb..c6152569fdd9e5587c8e8d7b0d7c2e2a77af6000 100644
> --- a/drivers/accel/rocket/rocket_device.h
> +++ b/drivers/accel/rocket/rocket_device.h
> @@ -14,6 +14,8 @@ struct rocket_device {
> struct clk *clk_npu;
> struct clk *pclk;
>
> + struct mutex iommu_lock;
> +
> struct rocket_core *cores;
> unsigned int num_cores;
> };
> diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
> index c22d965f20f1239a36b1d823d5fe5f372713555d..e5612b52952fa7a0cd0af02aef314984bc483b05 100644
> --- a/drivers/accel/rocket/rocket_drv.c
> +++ b/drivers/accel/rocket/rocket_drv.c
> @@ -6,6 +6,7 @@
> #include <drm/drm_gem.h>
> #include <drm/drm_ioctl.h>
> #include <drm/drm_of.h>
> +#include <drm/rocket_accel.h>
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/dma-mapping.h>
> @@ -14,6 +15,7 @@
> #include <linux/pm_runtime.h>
>
> #include "rocket_drv.h"
> +#include "rocket_gem.h"
>
> static int
> rocket_open(struct drm_device *dev, struct drm_file *file)
> @@ -42,6 +44,8 @@ rocket_postclose(struct drm_device *dev, struct drm_file *file)
> static const struct drm_ioctl_desc rocket_drm_driver_ioctls[] = {
> #define ROCKET_IOCTL(n, func) \
> DRM_IOCTL_DEF_DRV(ROCKET_##n, rocket_ioctl_##func, 0)
> +
> + ROCKET_IOCTL(CREATE_BO, create_bo),
> };
>
> DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
> @@ -51,9 +55,10 @@ DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
> * - 1.0 - initial interface
> */
> static const struct drm_driver rocket_drm_driver = {
> - .driver_features = DRIVER_COMPUTE_ACCEL,
> + .driver_features = DRIVER_COMPUTE_ACCEL | DRIVER_GEM,
> .open = rocket_open,
> .postclose = rocket_postclose,
> + .gem_create_object = rocket_gem_create_object,
> .ioctls = rocket_drm_driver_ioctls,
> .num_ioctls = ARRAY_SIZE(rocket_drm_driver_ioctls),
> .fops = &rocket_accel_driver_fops,
> diff --git a/drivers/accel/rocket/rocket_gem.c b/drivers/accel/rocket/rocket_gem.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..d5337cf1e275c249a1491d0dd28e6b8ccd2ff2cb
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_gem.c
> @@ -0,0 +1,141 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#include <drm/drm_device.h>
> +#include <drm/drm_utils.h>
> +#include <drm/rocket_accel.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/iommu.h>
> +
> +#include "rocket_device.h"
> +#include "rocket_gem.h"
> +
> +static void rocket_gem_bo_free(struct drm_gem_object *obj)
> +{
> + struct rocket_device *rdev = to_rocket_device(obj->dev);
> + struct rocket_gem_object *bo = to_rocket_bo(obj);
> + struct sg_table *sgt;
> +
> + drm_WARN_ON(obj->dev, bo->base.pages_use_count > 1);
> +
> + mutex_lock(&rdev->iommu_lock);
> +
> + sgt = drm_gem_shmem_get_pages_sgt(&bo->base);
> +
> + /* Unmap this object from the IOMMUs for cores > 0 */
> + for (unsigned int core = 1; core < rdev->num_cores; core++) {
> + struct iommu_domain *domain = iommu_get_domain_for_dev(rdev->cores[core].dev);
> + size_t unmapped = iommu_unmap(domain, sgt->sgl->dma_address, bo->size);
> +
> + drm_WARN_ON(obj->dev, unmapped != bo->size);
> + }
> +
> + /* This will unmap the pages from the IOMMU linked to core 0 */
> + drm_gem_shmem_free(&bo->base);
> +
> + mutex_unlock(&rdev->iommu_lock);
> +}
> +
> +static const struct drm_gem_object_funcs rocket_gem_funcs = {
> + .free = rocket_gem_bo_free,
> + .print_info = drm_gem_shmem_object_print_info,
> + .pin = drm_gem_shmem_object_pin,
> + .unpin = drm_gem_shmem_object_unpin,
> + .get_sg_table = drm_gem_shmem_object_get_sg_table,
> + .vmap = drm_gem_shmem_object_vmap,
> + .vunmap = drm_gem_shmem_object_vunmap,
> + .mmap = drm_gem_shmem_object_mmap,
> + .vm_ops = &drm_gem_shmem_vm_ops,
> +};
> +
> +/**
> + * rocket_gem_create_object - Implementation of driver->gem_create_object.
> + * @dev: DRM device
> + * @size: Size in bytes of the memory the object will reference
> + *
> + * This lets the GEM helpers allocate object structs for us, and keep
> + * our BO stats correct.
> + */
> +struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size)
> +{
> + struct rocket_gem_object *obj;
> +
> + obj = kzalloc(sizeof(*obj), GFP_KERNEL);
> + if (!obj)
> + return ERR_PTR(-ENOMEM);
> +
> + obj->base.base.funcs = &rocket_gem_funcs;
> +
> + return &obj->base.base;
> +}
> +
> +int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file)
> +{
> + struct drm_rocket_create_bo *args = data;
> + struct rocket_device *rdev = to_rocket_device(dev);
> + struct drm_gem_shmem_object *shmem_obj;
> + struct rocket_gem_object *rkt_obj;
> + struct drm_gem_object *gem_obj;
> + struct sg_table *sgt;
> + int ret;
> +
> + shmem_obj = drm_gem_shmem_create(dev, args->size);
> + if (IS_ERR(shmem_obj))
> + return PTR_ERR(shmem_obj);
> +
> + gem_obj = &shmem_obj->base;
> + rkt_obj = to_rocket_bo(gem_obj);
> +
> + rkt_obj->size = args->size;
> + rkt_obj->offset = 0;
> + mutex_init(&rkt_obj->mutex);
> +
> + ret = drm_gem_handle_create(file, gem_obj, &args->handle);
> + drm_gem_object_put(gem_obj);
> + if (ret)
> + goto err;
> +
> + mutex_lock(&rdev->iommu_lock);
> +
> + /* This will map the pages to the IOMMU linked to core 0 */
> + sgt = drm_gem_shmem_get_pages_sgt(shmem_obj);
> + if (IS_ERR(sgt)) {
> + ret = PTR_ERR(sgt);
> + goto err_unlock;
> + }
> +
> + /* Map the pages to the IOMMUs linked to the other cores, so all cores can access this BO */
> + for (unsigned int core = 1; core < rdev->num_cores; core++) {
> +
> + ret = iommu_map_sgtable(iommu_get_domain_for_dev(rdev->cores[core].dev),
> + sgt->sgl->dma_address,
> + sgt,
> + IOMMU_READ | IOMMU_WRITE);
> + if (ret < 0 || ret < args->size) {
> + DRM_ERROR("failed to map buffer: size=%d request_size=%u\n",
> + ret, args->size);
> + ret = -ENOMEM;
> + goto err_unlock;
> + }
> +
> + /* iommu_map_sgtable might have aligned the size */
> + rkt_obj->size = ret;
> +
> + dma_sync_sgtable_for_device(rdev->cores[core].dev, shmem_obj->sgt,
> + DMA_BIDIRECTIONAL);
> + }
> +
> + mutex_unlock(&rdev->iommu_lock);
> +
> + args->offset = drm_vma_node_offset_addr(&gem_obj->vma_node);
> + args->dma_address = sg_dma_address(shmem_obj->sgt->sgl);
> +
> + return 0;
> +
> +err_unlock:
> + mutex_unlock(&rdev->iommu_lock);
> +err:
> + drm_gem_shmem_object_free(gem_obj);
> +
> + return ret;
> +}
> diff --git a/drivers/accel/rocket/rocket_gem.h b/drivers/accel/rocket/rocket_gem.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..19b0cf91ddd99bd126c1af30beb169d6101f6dee
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_gem.h
> @@ -0,0 +1,27 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#ifndef __ROCKET_GEM_H__
> +#define __ROCKET_GEM_H__
> +
> +#include <drm/drm_gem_shmem_helper.h>
> +
> +struct rocket_gem_object {
> + struct drm_gem_shmem_object base;
> +
> + struct mutex mutex;
You init this mutex, but never destroy it.
I strongly recommend to scratch all per-object locks and use the
object's reservation lock instead (found in base.resv), if possible.
With multiple locks and dma-buf buffer sharing, there's otherwise
endless fun from getting the locking order right.
> + size_t size;
> + u32 offset;
> +};
> +
> +struct drm_gem_object *rocket_gem_create_object(struct drm_device *dev, size_t size);
> +
> +int rocket_ioctl_create_bo(struct drm_device *dev, void *data, struct drm_file *file);
> +
> +static inline
> +struct rocket_gem_object *to_rocket_bo(struct drm_gem_object *obj)
> +{
> + return container_of(to_drm_gem_shmem_obj(obj), struct rocket_gem_object, base);
> +}
> +
> +#endif
> diff --git a/include/uapi/drm/rocket_accel.h b/include/uapi/drm/rocket_accel.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..8338726a83c31b954608ca505cf78bcd70d3494b
> --- /dev/null
> +++ b/include/uapi/drm/rocket_accel.h
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Tomeu Vizoso
> + */
> +#ifndef _ROCKET_DRM_H_
> +#define _ROCKET_DRM_H_
For UAPI headers, it makes sense to use a more verbose include guard;
say __DRM_UAPI_ROCKET_ACCEL_H__. Avoids possible conflicts.
Best regards
Thomas
> +
> +#include "drm.h"
> +
> +#if defined(__cplusplus)
> +extern "C" {
> +#endif
> +
> +#define DRM_ROCKET_CREATE_BO 0x00
> +
> +#define DRM_IOCTL_ROCKET_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_ROCKET_CREATE_BO, struct drm_rocket_create_bo)
> +
> +/**
> + * struct drm_rocket_create_bo - ioctl argument for creating Rocket BOs.
> + *
> + */
> +struct drm_rocket_create_bo {
> + __u32 size;
> +
> + /** Returned GEM handle for the BO. */
> + __u32 handle;
> +
> + /**
> + * Returned DMA address for the BO in the NPU address space. This address
> + * is private to the DRM fd and is valid for the lifetime of the GEM
> + * handle.
> + */
> + __u64 dma_address;
> +
> + /** Offset into the drm node to use for subsequent mmap call. */
> + __u64 offset;
> +};
> +
> +#if defined(__cplusplus)
> +}
> +#endif
> +
> +#endif /* _ROCKET_DRM_H_ */
>
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
11 months, 3 weeks
- 1
- 0
Re: [PATCH v2 4/7] accel/rocket: Add a new driver for Rockchip's NPU
by Thomas Zimmermann
Hi
Am 25.02.25 um 08:55 schrieb Tomeu Vizoso:
> This initial version supports the NPU as shipped in the RK3588 SoC and
> described in the first part of its TRM, in Chapter 36.
>
> This NPU contains 3 independent cores that the driver can submit jobs
> to.
>
> This commit adds just hardware initialization and power management.
>
> v2:
> - Split cores and IOMMUs as independent devices (Sebastian Reichel)
> - Add some documentation (Jeffrey Hugo)
> - Be more explicit in the Kconfig documentation (Jeffrey Hugo)
> - Remove resets, as these haven't been found useful so far (Zenghui Yu)
> - Repack structs (Jeffrey Hugo)
> - Use DEFINE_DRM_ACCEL_FOPS (Jeffrey Hugo)
> - Use devm_drm_dev_alloc (Jeffrey Hugo)
> - Use probe log helper (Jeffrey Hugo)
> - Introduce UABI header in a later patch (Jeffrey Hugo)
>
> Signed-off-by: Tomeu Vizoso <tomeu(a)tomeuvizoso.net>
> ---
> Documentation/accel/index.rst | 1 +
> Documentation/accel/rocket/index.rst | 19 +
> MAINTAINERS | 8 +
> drivers/accel/Kconfig | 1 +
> drivers/accel/Makefile | 1 +
> drivers/accel/rocket/Kconfig | 25 +
> drivers/accel/rocket/Makefile | 8 +
> drivers/accel/rocket/rocket_core.c | 71 +
> drivers/accel/rocket/rocket_core.h | 29 +
> drivers/accel/rocket/rocket_device.c | 29 +
> drivers/accel/rocket/rocket_device.h | 29 +
> drivers/accel/rocket/rocket_drv.c | 273 ++
> drivers/accel/rocket/rocket_drv.h | 13 +
> drivers/accel/rocket/rocket_registers.h | 4425 +++++++++++++++++++++++++++++++
> 14 files changed, 4932 insertions(+)
>
> diff --git a/Documentation/accel/index.rst b/Documentation/accel/index.rst
> index bc85f26533d88891dde482f91e26c99991b22869..d8fa332d60a890dbb617454d2a26d9b6f9b196aa 100644
> --- a/Documentation/accel/index.rst
> +++ b/Documentation/accel/index.rst
> @@ -10,6 +10,7 @@ Compute Accelerators
> introduction
> amdxdna/index
> qaic/index
> + rocket/index
>
> .. only:: subproject and html
>
> diff --git a/Documentation/accel/rocket/index.rst b/Documentation/accel/rocket/index.rst
> new file mode 100644
> index 0000000000000000000000000000000000000000..ad33194dec0325d0dab362768fd349e8dc286970
> --- /dev/null
> +++ b/Documentation/accel/rocket/index.rst
> @@ -0,0 +1,19 @@
> +.. SPDX-License-Identifier: GPL-2.0-only
> +
> +=====================================
> + accel/rocket Rockchip NPU driver
> +=====================================
> +
> +The accel/rocket driver supports the Neural Processing Units (NPUs) inside some Rockchip SoCs such as the RK3588. Rockchip calls it RKNN and sometimes RKNPU.
> +
> +This NPU is closely based on the NVDLA IP released by NVIDIA as open hardware in 2018, along with open source kernel and userspace drivers.
> +
> +The frontend unit in Rockchip's NPU though is completely different from that in the open source IP, so this kernel driver is specific to Rockchip's version.
> +
> +The hardware is described in chapter 36 in the RK3588 TRM.
> +
> +This driver just powers the hardware on and off, allocates and maps buffers to the device and submits jobs to the frontend unit. Everything else is done in userspace, as a Gallium driver that is part of the Mesa3D project.
> +
> +Hardware currently supported:
> +
> +* RK3588
> \ No newline at end of file
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 25c86f47353de25c88291cc7fd6c4e9bfb12d5c4..cf89846b8bd2cf7ba742169debfc81838b2db46c 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7135,6 +7135,14 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
> F: drivers/accel/ivpu/
> F: include/uapi/drm/ivpu_accel.h
>
> +DRM ACCEL DRIVER FOR ROCKCHIP NPU
> +M: Tomeu Vizoso <tomeu(a)tomeuvizoso.net>
> +L: dri-devel(a)lists.freedesktop.org
> +S: Supported
> +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
> +F: drivers/accel/rocket/
> +F: include/uapi/drm/rocket_accel.h
> +
> DRM COMPUTE ACCELERATORS DRIVERS AND FRAMEWORK
> M: Oded Gabbay <ogabbay(a)kernel.org>
> L: dri-devel(a)lists.freedesktop.org
> diff --git a/drivers/accel/Kconfig b/drivers/accel/Kconfig
> index 5b9490367a39fd12d35a8d9021768aa186c09308..bb01cebc42bf16ebf02e938040f339ff94869e33 100644
> --- a/drivers/accel/Kconfig
> +++ b/drivers/accel/Kconfig
> @@ -28,5 +28,6 @@ source "drivers/accel/amdxdna/Kconfig"
> source "drivers/accel/habanalabs/Kconfig"
> source "drivers/accel/ivpu/Kconfig"
> source "drivers/accel/qaic/Kconfig"
> +source "drivers/accel/rocket/Kconfig"
>
> endif
> diff --git a/drivers/accel/Makefile b/drivers/accel/Makefile
> index a301fb6089d4c515430175c5e2ba9190f6dc9158..ffc3fa58866616d933184a7659573cd4d4780a8d 100644
> --- a/drivers/accel/Makefile
> +++ b/drivers/accel/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_ACCEL_AMDXDNA) += amdxdna/
> obj-$(CONFIG_DRM_ACCEL_HABANALABS) += habanalabs/
> obj-$(CONFIG_DRM_ACCEL_IVPU) += ivpu/
> obj-$(CONFIG_DRM_ACCEL_QAIC) += qaic/
> +obj-$(CONFIG_DRM_ACCEL_ROCKET) += rocket/
> \ No newline at end of file
> diff --git a/drivers/accel/rocket/Kconfig b/drivers/accel/rocket/Kconfig
> new file mode 100644
> index 0000000000000000000000000000000000000000..83a401129ab2dc2847ccc30c6364e8802f43648d
> --- /dev/null
> +++ b/drivers/accel/rocket/Kconfig
> @@ -0,0 +1,25 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +config DRM_ACCEL_ROCKET
> + tristate "Rocket (support for Rockchip NPUs)"
> + depends on DRM
> + depends on ARM64 || COMPILE_TEST
> + depends on MMU
> + select DRM_SCHED
> + select IOMMU_SUPPORT
> + select IOMMU_IO_PGTABLE_LPAE
> + select DRM_GEM_SHMEM_HELPER
> + help
> + Choose this option if you have a Rockchip SoC that contains a
> + compatible Neural Processing Unit (NPU), such as the RK3588. Called by
> + Rockchip either RKNN or RKNPU, it accelerates inference of neural
> + networks.
> +
> + The interface exposed to userspace is described in
> + include/uapi/drm/rocket_accel.h and is used by the userspace driver in
> + Mesa3D.
> +
> + If unsure, say N.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called rocket.
> diff --git a/drivers/accel/rocket/Makefile b/drivers/accel/rocket/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..73a7280d260c068d37ad3048824f710482333540
> --- /dev/null
> +++ b/drivers/accel/rocket/Makefile
> @@ -0,0 +1,8 @@
> +# SPDX-License-Identifier: GPL-2.0
> +
> +obj-$(CONFIG_DRM_ACCEL_ROCKET) := rocket.o
> +
> +rocket-y := \
> + rocket_core.o \
> + rocket_device.o \
> + rocket_drv.o
> diff --git a/drivers/accel/rocket/rocket_core.c b/drivers/accel/rocket/rocket_core.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..09d966c826b5b1090a18cb24b3aa4aba286a12d4
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_core.c
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#include <linux/clk.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "rocket_core.h"
> +#include "rocket_registers.h"
> +
> +static int rocket_clk_init(struct rocket_core *core)
> +{
> + struct device *dev = core->dev;
> + int err;
> +
> + core->a_clk = devm_clk_get(dev, "aclk");
> + if (IS_ERR(core->a_clk)) {
> + err = PTR_ERR(core->a_clk);
> + dev_err(dev, "devm_clk_get_enabled failed %d for core %d\n", err, core->index);
> + return err;
> + }
> +
> + core->h_clk = devm_clk_get(dev, "hclk");
> + if (IS_ERR(core->h_clk)) {
> + err = PTR_ERR(core->h_clk);
> + dev_err(dev, "devm_clk_get_enabled failed %d for core %d\n", err, core->index);
> + clk_disable_unprepare(core->a_clk);
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +int rocket_core_init(struct rocket_core *core)
> +{
> + struct device *dev = core->dev;
> + struct platform_device *pdev = to_platform_device(dev);
> + uint32_t version;
> + int err = 0;
> +
> + err = rocket_clk_init(core);
> + if (err) {
> + dev_err(dev, "clk init failed %d\n", err);
> + return err;
> + }
> +
> + core->iomem = devm_platform_ioremap_resource(pdev, 0);
> + if (IS_ERR(core->iomem))
> + return PTR_ERR(core->iomem);
> +
> + pm_runtime_use_autosuspend(dev);
> + pm_runtime_set_autosuspend_delay(dev, 50); /* ~3 frames */
> + pm_runtime_enable(dev);
> +
> + err = pm_runtime_get_sync(dev);
> +
> + version = rocket_read(core, REG_PC_VERSION);
> + version += rocket_read(core, REG_PC_VERSION_NUM) & 0xffff;
> +
> + pm_runtime_mark_last_busy(dev);
> + pm_runtime_put_autosuspend(dev);
> +
> + dev_info(dev, "Rockchip NPU core %d version: %d\n", core->index, version);
> +
> + return 0;
> +}
> +
> +void rocket_core_fini(struct rocket_core *core)
> +{
> + pm_runtime_disable(core->dev);
> +}
> diff --git a/drivers/accel/rocket/rocket_core.h b/drivers/accel/rocket/rocket_core.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..2171eba7139ccc63fe24802dc81b4adb7f3abf31
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_core.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#ifndef __ROCKET_CORE_H__
> +#define __ROCKET_CORE_H__
> +
> +#include <drm/gpu_scheduler.h>
> +#include <linux/mutex_types.h>
> +#include <linux/io.h>
linux/ headers go first.
> +
> +#define rocket_read(core, reg) readl((core)->iomem + (reg))
> +#define rocket_write(core, reg, value) writel(value, (core)->iomem + (reg))
> +
> +struct rocket_core {
> + struct device *dev;
> + struct rocket_device *rdev;
> + struct device_link *link;
> + unsigned int index;
> +
> + int irq;
> + void __iomem *iomem;
> + struct clk *a_clk;
> + struct clk *h_clk;
> +};
> +
> +int rocket_core_init(struct rocket_core *core);
> +void rocket_core_fini(struct rocket_core *core);
> +
> +#endif
> diff --git a/drivers/accel/rocket/rocket_device.c b/drivers/accel/rocket/rocket_device.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..ce3b533f15c1011d8a7a23dd8132e907cc334c58
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_device.c
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#include <linux/clk.h>
> +
> +#include "rocket_device.h"
> +
> +int rocket_device_init(struct rocket_device *rdev)
> +{
> + struct device *dev = rdev->cores[0].dev;
> + int err;
> +
> + rdev->clk_npu = devm_clk_get(dev, "npu");
> + rdev->pclk = devm_clk_get(dev, "pclk");
> +
> + /* Initialize core 0 (top) */
> + err = rocket_core_init(&rdev->cores[0]);
> + if (err) {
> + rocket_device_fini(rdev);
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +void rocket_device_fini(struct rocket_device *rdev)
> +{
> + rocket_core_fini(&rdev->cores[0]);
> +}
> diff --git a/drivers/accel/rocket/rocket_device.h b/drivers/accel/rocket/rocket_device.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..466edba9102c5dc5dfac5d3fcc1c904f206eaebb
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_device.h
> @@ -0,0 +1,29 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#ifndef __ROCKET_DEVICE_H__
> +#define __ROCKET_DEVICE_H__
> +
> +#include <drm/drm_device.h>
> +
> +#include "rocket_core.h"
> +
> +struct rocket_device {
> + struct drm_device ddev;
> +
> + struct clk *clk_npu;
> + struct clk *pclk;
> +
> + struct rocket_core *cores;
> + unsigned int num_cores;
> +};
> +
> +int rocket_device_init(struct rocket_device *rdev);
> +void rocket_device_fini(struct rocket_device *rdev);
> +
> +static inline struct rocket_device *to_rocket_device(struct drm_device *dev)
> +{
> + return (struct rocket_device *)dev;
Please to a proper upcast with container_of().
> +}
> +
> +#endif
> diff --git a/drivers/accel/rocket/rocket_drv.c b/drivers/accel/rocket/rocket_drv.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..c22d965f20f1239a36b1d823d5fe5f372713555d
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_drv.c
> @@ -0,0 +1,273 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#include <drm/drm_accel.h>
> +#include <drm/drm_drv.h>
> +#include <drm/drm_gem.h>
> +#include <drm/drm_ioctl.h>
> +#include <drm/drm_of.h>
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/dma-mapping.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "rocket_drv.h"
> +
> +static int
> +rocket_open(struct drm_device *dev, struct drm_file *file)
> +{
> + struct rocket_device *rdev = to_rocket_device(dev);
> + struct rocket_file_priv *rocket_priv;
> +
> + rocket_priv = kzalloc(sizeof(*rocket_priv), GFP_KERNEL);
> + if (!rocket_priv)
> + return -ENOMEM;
> +
> + rocket_priv->rdev = rdev;
> + file->driver_priv = rocket_priv;
> +
> + return 0;
> +}
> +
> +static void
> +rocket_postclose(struct drm_device *dev, struct drm_file *file)
> +{
> + struct rocket_file_priv *rocket_priv = file->driver_priv;
> +
> + kfree(rocket_priv);
> +}
> +
> +static const struct drm_ioctl_desc rocket_drm_driver_ioctls[] = {
> +#define ROCKET_IOCTL(n, func) \
> + DRM_IOCTL_DEF_DRV(ROCKET_##n, rocket_ioctl_##func, 0)
> +};
> +
> +DEFINE_DRM_ACCEL_FOPS(rocket_accel_driver_fops);
> +
> +/*
> + * Rocket driver version:
> + * - 1.0 - initial interface
> + */
> +static const struct drm_driver rocket_drm_driver = {
> + .driver_features = DRIVER_COMPUTE_ACCEL,
> + .open = rocket_open,
> + .postclose = rocket_postclose,
> + .ioctls = rocket_drm_driver_ioctls,
> + .num_ioctls = ARRAY_SIZE(rocket_drm_driver_ioctls),
> + .fops = &rocket_accel_driver_fops,
> + .name = "rocket",
> + .desc = "rocket DRM",
> +};
> +
> +static int rocket_drm_bind(struct device *dev)
> +{
> + struct device_node *core_node;
> + struct rocket_device *rdev;
> + struct drm_device *ddev;
> + unsigned int num_cores = 1;
> + int err;
> +
> + rdev = devm_drm_dev_alloc(dev, &rocket_drm_driver, struct rocket_device, ddev);
> + if (IS_ERR(ddev))
> + return PTR_ERR(ddev);
> +
> + ddev = &rdev->ddev;
> + dev_set_drvdata(dev, rdev);
> +
> + for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core")
> + if (of_device_is_available(core_node))
> + num_cores++;
> +
> + rdev->cores = devm_kmalloc_array(dev, num_cores, sizeof(*rdev->cores),
> + GFP_KERNEL | __GFP_ZERO);
> + if (IS_ERR(rdev->cores))
> + return PTR_ERR(rdev->cores);
> +
> + /* Add core 0, any other cores will be added later when they are bound */
> + rdev->cores[0].rdev = rdev;
> + rdev->cores[0].dev = dev;
> + rdev->cores[0].index = 0;
> + rdev->num_cores = 1;
> +
> + err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
> + if (err)
> + return err;
> +
> + err = rocket_device_init(rdev);
> + if (err) {
> + dev_err_probe(dev, err, "Fatal error during NPU init\n");
> + goto err_device_fini;
> + }
> +
> + err = component_bind_all(dev, rdev);
> + if (err)
> + goto err_device_fini;
> +
> + err = drm_dev_register(ddev, 0);
> + if (err < 0)
> + goto err_unbind;
> +
> + return 0;
> +
> +err_unbind:
> + component_unbind_all(dev, rdev);
> +err_device_fini:
> + rocket_device_fini(rdev);
> + return err;
> +}
> +
> +static void rocket_drm_unbind(struct device *dev)
> +{
> + struct rocket_device *rdev = dev_get_drvdata(dev);
> + struct drm_device *ddev = &rdev->ddev;
> +
> + drm_dev_unregister(ddev);
I don't know if that works for accelerators, but for graphics, we often
use drm_dev_unplug() instead of drm_dev_unregister(). The former will
set the device state such that the rest of the driver can detect it.
Makes hot-unplugging work.
> +
> + component_unbind_all(dev, rdev);
> +
> + rocket_device_fini(rdev);
> +}
> +
> +const struct component_master_ops rocket_drm_ops = {
> + .bind = rocket_drm_bind,
> + .unbind = rocket_drm_unbind,
> +};
> +
> +static int rocket_core_bind(struct device *dev, struct device *master, void *data)
> +{
> + struct rocket_device *rdev = data;
> + unsigned int core = rdev->num_cores;
> + int err;
> +
> + dev_set_drvdata(dev, rdev);
> +
> + rdev->cores[core].rdev = rdev;
> + rdev->cores[core].dev = dev;
> + rdev->cores[core].index = core;
> + rdev->cores[core].link = device_link_add(dev, rdev->cores[0].dev,
> + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME);
> +
> + rdev->num_cores++;
> +
> + err = rocket_core_init(&rdev->cores[core]);
> + if (err) {
> + rocket_device_fini(rdev);
num_cores has been incremented already. _fini works correctly with
half-initialized cores?
> + return err;
> + }
> +
> + return 0;
> +}
> +
> +static void rocket_core_unbind(struct device *dev, struct device *master, void *data)
> +{
> + struct rocket_device *rdev = data;
> +
> + for (unsigned int core = 1; core < rdev->num_cores; core++) {
> + if (rdev->cores[core].dev == dev) {
> + rocket_core_fini(&rdev->cores[core]);
> + device_link_del(rdev->cores[core].link);
> + break;
> + }
> + }
> +}
> +
> +const struct component_ops rocket_core_ops = {
> + .bind = rocket_core_bind,
> + .unbind = rocket_core_unbind,
> +};
> +
> +static int rocket_probe(struct platform_device *pdev)
> +{
> + struct component_match *match = NULL;
> + struct device_node *core_node;
> +
> + if (fwnode_device_is_compatible(pdev->dev.fwnode, "rockchip,rk3588-rknn-core"))
> + return component_add(&pdev->dev, &rocket_core_ops);
> +
> + for_each_compatible_node(core_node, NULL, "rockchip,rk3588-rknn-core") {
> + if (!of_device_is_available(core_node))
> + continue;
> +
> + drm_of_component_match_add(&pdev->dev, &match,
> + component_compare_of, core_node);
> + }
> +
> + return component_master_add_with_match(&pdev->dev, &rocket_drm_ops, match);
> +}
> +
> +static void rocket_remove(struct platform_device *pdev)
> +{
> + if (fwnode_device_is_compatible(pdev->dev.fwnode, "rockchip,rk3588-rknn-core-top"))
> + component_master_del(&pdev->dev, &rocket_drm_ops);
> + else if (fwnode_device_is_compatible(pdev->dev.fwnode, "rockchip,rk3588-rknn-core"))
> + component_del(&pdev->dev, &rocket_core_ops);
> +}
> +
> +static const struct of_device_id dt_match[] = {
> + { .compatible = "rockchip,rk3588-rknn-core-top" },
> + { .compatible = "rockchip,rk3588-rknn-core" },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, dt_match);
> +
> +static int rocket_device_runtime_resume(struct device *dev)
> +{
> + struct rocket_device *rdev = dev_get_drvdata(dev);
> +
> + for (unsigned int core = 0; core < rdev->num_cores; core++) {
> + if (dev != rdev->cores[core].dev)
> + continue;
> +
> + if (core == 0) {
> + clk_prepare_enable(rdev->clk_npu);
> + clk_prepare_enable(rdev->pclk);
> + }
> +
> + clk_prepare_enable(rdev->cores[core].a_clk);
> + clk_prepare_enable(rdev->cores[core].h_clk);
> + }
> +
> + return 0;
> +}
> +
> +static int rocket_device_runtime_suspend(struct device *dev)
> +{
> + struct rocket_device *rdev = dev_get_drvdata(dev);
> +
> + for (unsigned int core = 0; core < rdev->num_cores; core++) {
> + if (dev != rdev->cores[core].dev)
> + continue;
> +
> + clk_disable_unprepare(rdev->cores[core].a_clk);
> + clk_disable_unprepare(rdev->cores[core].h_clk);
> +
> + if (core == 0) {
> + clk_disable_unprepare(rdev->pclk);
> + clk_disable_unprepare(rdev->clk_npu);
> + }
> + }
> +
> + return 0;
> +}
> +
> +EXPORT_GPL_DEV_PM_OPS(rocket_pm_ops) = {
> + RUNTIME_PM_OPS(rocket_device_runtime_suspend, rocket_device_runtime_resume, NULL)
> + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
> +};
> +
> +static struct platform_driver rocket_driver = {
> + .probe = rocket_probe,
> + .remove = rocket_remove,
> + .driver = {
> + .name = "rocket",
> + .pm = pm_ptr(&rocket_pm_ops),
> + .of_match_table = dt_match,
> + },
> +};
> +module_platform_driver(rocket_driver);
> +
> +MODULE_LICENSE("GPL");
> +MODULE_DESCRIPTION("DRM driver for the Rockchip NPU IP");
> +MODULE_AUTHOR("Tomeu Vizoso");
> diff --git a/drivers/accel/rocket/rocket_drv.h b/drivers/accel/rocket/rocket_drv.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..ccdd50c69d4c033eea18cb800407fdcfb3bf2e9b
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_drv.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright 2024 Tomeu Vizoso <tomeu(a)tomeuvizoso.net> */
> +
> +#ifndef __ROCKET_DRV_H__
> +#define __ROCKET_DRV_H__
> +
> +#include "rocket_device.h"
> +
> +struct rocket_file_priv {
> + struct rocket_device *rdev;
> +};
> +
> +#endif
> diff --git a/drivers/accel/rocket/rocket_registers.h b/drivers/accel/rocket/rocket_registers.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..498566e9ca9fb7235f1c9035240075027b55a9e3
> --- /dev/null
> +++ b/drivers/accel/rocket/rocket_registers.h
> @@ -0,0 +1,4425 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR MIT */
> +
> +#ifndef __ROCKET_REGISTERS_XML__
> +#define __ROCKET_REGISTERS_XML__
> +
> +/* Autogenerated file, DO NOT EDIT manually!
> +
That is the rest of the patch AFAICT. Could this file be added in a
separate patch? It would make reviewing a bit easier.
Best regards
Thomas
> +This file was generated by the rules-ng-ng gen_header.py tool in this git repository:
> +http://gitlab.freedesktop.org/mesa/mesa/
> +git clone https://gitlab.freedesktop.org/mesa/mesa.git
> +
> +The rules-ng-ng source files this header was generated from are:
> +
> +- /home/tomeu/src/mesa/src/gallium/drivers/rocket/registers.xml ( 60076 bytes, from Wed Jun 12 10:02:25 2024)
> +
> +Copyright (C) 2024-2025 by the following authors:
> +- Tomeu Vizoso <tomeu(a)tomeuvizoso.net> Tomeu Vizoso
> +
> +Permission is hereby granted, free of charge, to any person obtaining
> +a copy of this software and associated documentation files (the
> +"Software"), to deal in the Software without restriction, including
> +without limitation the rights to use, copy, modify, merge, publish,
> +distribute, sublicense, and/or sell copies of the Software, and to
> +permit persons to whom the Software is furnished to do so, subject to
> +the following conditions:
> +
> +The above copyright notice and this permission notice (including the
> +next paragraph) shall be included in all copies or substantial
> +portions of the Software.
> +
> +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
> +IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
> +LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
> +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
> +WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> +
> +*/
> +
> +#define REG_PC_VERSION 0x00000000
> +#define PC_VERSION_VERSION__MASK 0xffffffff
> +#define PC_VERSION_VERSION__SHIFT 0
> +static inline uint32_t PC_VERSION_VERSION(uint32_t val)
> +{
> + return ((val) << PC_VERSION_VERSION__SHIFT) & PC_VERSION_VERSION__MASK;
> +}
> +
> +#define REG_PC_VERSION_NUM 0x00000004
> +#define PC_VERSION_NUM_VERSION_NUM__MASK 0xffffffff
> +#define PC_VERSION_NUM_VERSION_NUM__SHIFT 0
> +static inline uint32_t PC_VERSION_NUM_VERSION_NUM(uint32_t val)
> +{
> + return ((val) << PC_VERSION_NUM_VERSION_NUM__SHIFT) & PC_VERSION_NUM_VERSION_NUM__MASK;
> +}
> +
> +#define REG_PC_OPERATION_ENABLE 0x00000008
> +#define PC_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
> +#define PC_OPERATION_ENABLE_RESERVED_0__SHIFT 1
> +static inline uint32_t PC_OPERATION_ENABLE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_OPERATION_ENABLE_RESERVED_0__SHIFT) & PC_OPERATION_ENABLE_RESERVED_0__MASK;
> +}
> +#define PC_OPERATION_ENABLE_OP_EN__MASK 0x00000001
> +#define PC_OPERATION_ENABLE_OP_EN__SHIFT 0
> +static inline uint32_t PC_OPERATION_ENABLE_OP_EN(uint32_t val)
> +{
> + return ((val) << PC_OPERATION_ENABLE_OP_EN__SHIFT) & PC_OPERATION_ENABLE_OP_EN__MASK;
> +}
> +
> +#define REG_PC_BASE_ADDRESS 0x00000010
> +#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK 0xfffffff0
> +#define PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT 4
> +static inline uint32_t PC_BASE_ADDRESS_PC_SOURCE_ADDR(uint32_t val)
> +{
> + return ((val) << PC_BASE_ADDRESS_PC_SOURCE_ADDR__SHIFT) & PC_BASE_ADDRESS_PC_SOURCE_ADDR__MASK;
> +}
> +#define PC_BASE_ADDRESS_RESERVED_0__MASK 0x0000000e
> +#define PC_BASE_ADDRESS_RESERVED_0__SHIFT 1
> +static inline uint32_t PC_BASE_ADDRESS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_BASE_ADDRESS_RESERVED_0__SHIFT) & PC_BASE_ADDRESS_RESERVED_0__MASK;
> +}
> +#define PC_BASE_ADDRESS_PC_SEL__MASK 0x00000001
> +#define PC_BASE_ADDRESS_PC_SEL__SHIFT 0
> +static inline uint32_t PC_BASE_ADDRESS_PC_SEL(uint32_t val)
> +{
> + return ((val) << PC_BASE_ADDRESS_PC_SEL__SHIFT) & PC_BASE_ADDRESS_PC_SEL__MASK;
> +}
> +
> +#define REG_PC_REGISTER_AMOUNTS 0x00000014
> +#define PC_REGISTER_AMOUNTS_RESERVED_0__MASK 0xffff0000
> +#define PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT 16
> +static inline uint32_t PC_REGISTER_AMOUNTS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_REGISTER_AMOUNTS_RESERVED_0__SHIFT) & PC_REGISTER_AMOUNTS_RESERVED_0__MASK;
> +}
> +#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK 0x0000ffff
> +#define PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT 0
> +static inline uint32_t PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT(uint32_t val)
> +{
> + return ((val) << PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__SHIFT) & PC_REGISTER_AMOUNTS_PC_DATA_AMOUNT__MASK;
> +}
> +
> +#define REG_PC_INTERRUPT_MASK 0x00000020
> +#define PC_INTERRUPT_MASK_RESERVED_0__MASK 0xffffc000
> +#define PC_INTERRUPT_MASK_RESERVED_0__SHIFT 14
> +static inline uint32_t PC_INTERRUPT_MASK_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_INTERRUPT_MASK_RESERVED_0__SHIFT) & PC_INTERRUPT_MASK_RESERVED_0__MASK;
> +}
> +#define PC_INTERRUPT_MASK_DMA_WRITE_ERROR 0x00002000
> +#define PC_INTERRUPT_MASK_DMA_READ_ERROR 0x00001000
> +#define PC_INTERRUPT_MASK_PPU_1 0x00000800
> +#define PC_INTERRUPT_MASK_PPU_0 0x00000400
> +#define PC_INTERRUPT_MASK_DPU_1 0x00000200
> +#define PC_INTERRUPT_MASK_DPU_0 0x00000100
> +#define PC_INTERRUPT_MASK_CORE_1 0x00000080
> +#define PC_INTERRUPT_MASK_CORE_0 0x00000040
> +#define PC_INTERRUPT_MASK_CNA_CSC_1 0x00000020
> +#define PC_INTERRUPT_MASK_CNA_CSC_0 0x00000010
> +#define PC_INTERRUPT_MASK_CNA_WEIGHT_1 0x00000008
> +#define PC_INTERRUPT_MASK_CNA_WEIGHT_0 0x00000004
> +#define PC_INTERRUPT_MASK_CNA_FEATURE_1 0x00000002
> +#define PC_INTERRUPT_MASK_CNA_FEATURE_0 0x00000001
> +
> +#define REG_PC_INTERRUPT_CLEAR 0x00000024
> +#define PC_INTERRUPT_CLEAR_RESERVED_0__MASK 0xffffc000
> +#define PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT 14
> +static inline uint32_t PC_INTERRUPT_CLEAR_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_INTERRUPT_CLEAR_RESERVED_0__SHIFT) & PC_INTERRUPT_CLEAR_RESERVED_0__MASK;
> +}
> +#define PC_INTERRUPT_CLEAR_DMA_WRITE_ERROR 0x00002000
> +#define PC_INTERRUPT_CLEAR_DMA_READ_ERROR 0x00001000
> +#define PC_INTERRUPT_CLEAR_PPU_1 0x00000800
> +#define PC_INTERRUPT_CLEAR_PPU_0 0x00000400
> +#define PC_INTERRUPT_CLEAR_DPU_1 0x00000200
> +#define PC_INTERRUPT_CLEAR_DPU_0 0x00000100
> +#define PC_INTERRUPT_CLEAR_CORE_1 0x00000080
> +#define PC_INTERRUPT_CLEAR_CORE_0 0x00000040
> +#define PC_INTERRUPT_CLEAR_CNA_CSC_1 0x00000020
> +#define PC_INTERRUPT_CLEAR_CNA_CSC_0 0x00000010
> +#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_1 0x00000008
> +#define PC_INTERRUPT_CLEAR_CNA_WEIGHT_0 0x00000004
> +#define PC_INTERRUPT_CLEAR_CNA_FEATURE_1 0x00000002
> +#define PC_INTERRUPT_CLEAR_CNA_FEATURE_0 0x00000001
> +
> +#define REG_PC_INTERRUPT_STATUS 0x00000028
> +#define PC_INTERRUPT_STATUS_RESERVED_0__MASK 0xffffc000
> +#define PC_INTERRUPT_STATUS_RESERVED_0__SHIFT 14
> +static inline uint32_t PC_INTERRUPT_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_INTERRUPT_STATUS_RESERVED_0__SHIFT) & PC_INTERRUPT_STATUS_RESERVED_0__MASK;
> +}
> +#define PC_INTERRUPT_STATUS_DMA_WRITE_ERROR 0x00002000
> +#define PC_INTERRUPT_STATUS_DMA_READ_ERROR 0x00001000
> +#define PC_INTERRUPT_STATUS_PPU_1 0x00000800
> +#define PC_INTERRUPT_STATUS_PPU_0 0x00000400
> +#define PC_INTERRUPT_STATUS_DPU_1 0x00000200
> +#define PC_INTERRUPT_STATUS_DPU_0 0x00000100
> +#define PC_INTERRUPT_STATUS_CORE_1 0x00000080
> +#define PC_INTERRUPT_STATUS_CORE_0 0x00000040
> +#define PC_INTERRUPT_STATUS_CNA_CSC_1 0x00000020
> +#define PC_INTERRUPT_STATUS_CNA_CSC_0 0x00000010
> +#define PC_INTERRUPT_STATUS_CNA_WEIGHT_1 0x00000008
> +#define PC_INTERRUPT_STATUS_CNA_WEIGHT_0 0x00000004
> +#define PC_INTERRUPT_STATUS_CNA_FEATURE_1 0x00000002
> +#define PC_INTERRUPT_STATUS_CNA_FEATURE_0 0x00000001
> +
> +#define REG_PC_INTERRUPT_RAW_STATUS 0x0000002c
> +#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK 0xffffc000
> +#define PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT 14
> +static inline uint32_t PC_INTERRUPT_RAW_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_INTERRUPT_RAW_STATUS_RESERVED_0__SHIFT) & PC_INTERRUPT_RAW_STATUS_RESERVED_0__MASK;
> +}
> +#define PC_INTERRUPT_RAW_STATUS_DMA_WRITE_ERROR 0x00002000
> +#define PC_INTERRUPT_RAW_STATUS_DMA_READ_ERROR 0x00001000
> +#define PC_INTERRUPT_RAW_STATUS_PPU_1 0x00000800
> +#define PC_INTERRUPT_RAW_STATUS_PPU_0 0x00000400
> +#define PC_INTERRUPT_RAW_STATUS_DPU_1 0x00000200
> +#define PC_INTERRUPT_RAW_STATUS_DPU_0 0x00000100
> +#define PC_INTERRUPT_RAW_STATUS_CORE_1 0x00000080
> +#define PC_INTERRUPT_RAW_STATUS_CORE_0 0x00000040
> +#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_1 0x00000020
> +#define PC_INTERRUPT_RAW_STATUS_CNA_CSC_0 0x00000010
> +#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_1 0x00000008
> +#define PC_INTERRUPT_RAW_STATUS_CNA_WEIGHT_0 0x00000004
> +#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_1 0x00000002
> +#define PC_INTERRUPT_RAW_STATUS_CNA_FEATURE_0 0x00000001
> +
> +#define REG_PC_TASK_CON 0x00000030
> +#define PC_TASK_CON_RESERVED_0__MASK 0xffffc000
> +#define PC_TASK_CON_RESERVED_0__SHIFT 14
> +static inline uint32_t PC_TASK_CON_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_TASK_CON_RESERVED_0__SHIFT) & PC_TASK_CON_RESERVED_0__MASK;
> +}
> +#define PC_TASK_CON_TASK_COUNT_CLEAR__MASK 0x00002000
> +#define PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT 13
> +static inline uint32_t PC_TASK_CON_TASK_COUNT_CLEAR(uint32_t val)
> +{
> + return ((val) << PC_TASK_CON_TASK_COUNT_CLEAR__SHIFT) & PC_TASK_CON_TASK_COUNT_CLEAR__MASK;
> +}
> +#define PC_TASK_CON_TASK_PP_EN__MASK 0x00001000
> +#define PC_TASK_CON_TASK_PP_EN__SHIFT 12
> +static inline uint32_t PC_TASK_CON_TASK_PP_EN(uint32_t val)
> +{
> + return ((val) << PC_TASK_CON_TASK_PP_EN__SHIFT) & PC_TASK_CON_TASK_PP_EN__MASK;
> +}
> +#define PC_TASK_CON_TASK_NUMBER__MASK 0x00000fff
> +#define PC_TASK_CON_TASK_NUMBER__SHIFT 0
> +static inline uint32_t PC_TASK_CON_TASK_NUMBER(uint32_t val)
> +{
> + return ((val) << PC_TASK_CON_TASK_NUMBER__SHIFT) & PC_TASK_CON_TASK_NUMBER__MASK;
> +}
> +
> +#define REG_PC_TASK_DMA_BASE_ADDR 0x00000034
> +#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK 0xfffffff0
> +#define PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT 4
> +static inline uint32_t PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__SHIFT) & PC_TASK_DMA_BASE_ADDR_DMA_BASE_ADDR__MASK;
> +}
> +#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK 0x0000000f
> +#define PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT 0
> +static inline uint32_t PC_TASK_DMA_BASE_ADDR_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_TASK_DMA_BASE_ADDR_RESERVED_0__SHIFT) & PC_TASK_DMA_BASE_ADDR_RESERVED_0__MASK;
> +}
> +
> +#define REG_PC_TASK_STATUS 0x0000003c
> +#define PC_TASK_STATUS_RESERVED_0__MASK 0xf0000000
> +#define PC_TASK_STATUS_RESERVED_0__SHIFT 28
> +static inline uint32_t PC_TASK_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PC_TASK_STATUS_RESERVED_0__SHIFT) & PC_TASK_STATUS_RESERVED_0__MASK;
> +}
> +#define PC_TASK_STATUS_TASK_STATUS__MASK 0x0fffffff
> +#define PC_TASK_STATUS_TASK_STATUS__SHIFT 0
> +static inline uint32_t PC_TASK_STATUS_TASK_STATUS(uint32_t val)
> +{
> + return ((val) << PC_TASK_STATUS_TASK_STATUS__SHIFT) & PC_TASK_STATUS_TASK_STATUS__MASK;
> +}
> +
> +#define REG_CNA_S_STATUS 0x00001000
> +#define CNA_S_STATUS_RESERVED_0__MASK 0xfffc0000
> +#define CNA_S_STATUS_RESERVED_0__SHIFT 18
> +static inline uint32_t CNA_S_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_S_STATUS_RESERVED_0__SHIFT) & CNA_S_STATUS_RESERVED_0__MASK;
> +}
> +#define CNA_S_STATUS_STATUS_1__MASK 0x00030000
> +#define CNA_S_STATUS_STATUS_1__SHIFT 16
> +static inline uint32_t CNA_S_STATUS_STATUS_1(uint32_t val)
> +{
> + return ((val) << CNA_S_STATUS_STATUS_1__SHIFT) & CNA_S_STATUS_STATUS_1__MASK;
> +}
> +#define CNA_S_STATUS_RESERVED_1__MASK 0x0000fffc
> +#define CNA_S_STATUS_RESERVED_1__SHIFT 2
> +static inline uint32_t CNA_S_STATUS_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_S_STATUS_RESERVED_1__SHIFT) & CNA_S_STATUS_RESERVED_1__MASK;
> +}
> +#define CNA_S_STATUS_STATUS_0__MASK 0x00000003
> +#define CNA_S_STATUS_STATUS_0__SHIFT 0
> +static inline uint32_t CNA_S_STATUS_STATUS_0(uint32_t val)
> +{
> + return ((val) << CNA_S_STATUS_STATUS_0__SHIFT) & CNA_S_STATUS_STATUS_0__MASK;
> +}
> +
> +#define REG_CNA_S_POINTER 0x00001004
> +#define CNA_S_POINTER_RESERVED_0__MASK 0xfffe0000
> +#define CNA_S_POINTER_RESERVED_0__SHIFT 17
> +static inline uint32_t CNA_S_POINTER_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_RESERVED_0__SHIFT) & CNA_S_POINTER_RESERVED_0__MASK;
> +}
> +#define CNA_S_POINTER_EXECUTER__MASK 0x00010000
> +#define CNA_S_POINTER_EXECUTER__SHIFT 16
> +static inline uint32_t CNA_S_POINTER_EXECUTER(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_EXECUTER__SHIFT) & CNA_S_POINTER_EXECUTER__MASK;
> +}
> +#define CNA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
> +#define CNA_S_POINTER_RESERVED_1__SHIFT 6
> +static inline uint32_t CNA_S_POINTER_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_RESERVED_1__SHIFT) & CNA_S_POINTER_RESERVED_1__MASK;
> +}
> +#define CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
> +#define CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
> +static inline uint32_t CNA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & CNA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
> +}
> +#define CNA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
> +#define CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
> +static inline uint32_t CNA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & CNA_S_POINTER_POINTER_PP_CLEAR__MASK;
> +}
> +#define CNA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
> +#define CNA_S_POINTER_POINTER_PP_MODE__SHIFT 3
> +static inline uint32_t CNA_S_POINTER_POINTER_PP_MODE(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_POINTER_PP_MODE__SHIFT) & CNA_S_POINTER_POINTER_PP_MODE__MASK;
> +}
> +#define CNA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
> +#define CNA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
> +static inline uint32_t CNA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_EXECUTER_PP_EN__SHIFT) & CNA_S_POINTER_EXECUTER_PP_EN__MASK;
> +}
> +#define CNA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
> +#define CNA_S_POINTER_POINTER_PP_EN__SHIFT 1
> +static inline uint32_t CNA_S_POINTER_POINTER_PP_EN(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_POINTER_PP_EN__SHIFT) & CNA_S_POINTER_POINTER_PP_EN__MASK;
> +}
> +#define CNA_S_POINTER_POINTER__MASK 0x00000001
> +#define CNA_S_POINTER_POINTER__SHIFT 0
> +static inline uint32_t CNA_S_POINTER_POINTER(uint32_t val)
> +{
> + return ((val) << CNA_S_POINTER_POINTER__SHIFT) & CNA_S_POINTER_POINTER__MASK;
> +}
> +
> +#define REG_CNA_OPERATION_ENABLE 0x00001008
> +#define CNA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
> +#define CNA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
> +static inline uint32_t CNA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_OPERATION_ENABLE_RESERVED_0__SHIFT) & CNA_OPERATION_ENABLE_RESERVED_0__MASK;
> +}
> +#define CNA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
> +#define CNA_OPERATION_ENABLE_OP_EN__SHIFT 0
> +static inline uint32_t CNA_OPERATION_ENABLE_OP_EN(uint32_t val)
> +{
> + return ((val) << CNA_OPERATION_ENABLE_OP_EN__SHIFT) & CNA_OPERATION_ENABLE_OP_EN__MASK;
> +}
> +
> +#define REG_CNA_CONV_CON1 0x0000100c
> +#define CNA_CONV_CON1_RESERVED_0__MASK 0x80000000
> +#define CNA_CONV_CON1_RESERVED_0__SHIFT 31
> +static inline uint32_t CNA_CONV_CON1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_RESERVED_0__SHIFT) & CNA_CONV_CON1_RESERVED_0__MASK;
> +}
> +#define CNA_CONV_CON1_NONALIGN_DMA__MASK 0x40000000
> +#define CNA_CONV_CON1_NONALIGN_DMA__SHIFT 30
> +static inline uint32_t CNA_CONV_CON1_NONALIGN_DMA(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_NONALIGN_DMA__SHIFT) & CNA_CONV_CON1_NONALIGN_DMA__MASK;
> +}
> +#define CNA_CONV_CON1_GROUP_LINE_OFF__MASK 0x20000000
> +#define CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT 29
> +static inline uint32_t CNA_CONV_CON1_GROUP_LINE_OFF(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_GROUP_LINE_OFF__SHIFT) & CNA_CONV_CON1_GROUP_LINE_OFF__MASK;
> +}
> +#define CNA_CONV_CON1_RESERVED_1__MASK 0x1ffe0000
> +#define CNA_CONV_CON1_RESERVED_1__SHIFT 17
> +static inline uint32_t CNA_CONV_CON1_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_RESERVED_1__SHIFT) & CNA_CONV_CON1_RESERVED_1__MASK;
> +}
> +#define CNA_CONV_CON1_DECONV__MASK 0x00010000
> +#define CNA_CONV_CON1_DECONV__SHIFT 16
> +static inline uint32_t CNA_CONV_CON1_DECONV(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_DECONV__SHIFT) & CNA_CONV_CON1_DECONV__MASK;
> +}
> +#define CNA_CONV_CON1_ARGB_IN__MASK 0x0000f000
> +#define CNA_CONV_CON1_ARGB_IN__SHIFT 12
> +static inline uint32_t CNA_CONV_CON1_ARGB_IN(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_ARGB_IN__SHIFT) & CNA_CONV_CON1_ARGB_IN__MASK;
> +}
> +#define CNA_CONV_CON1_RESERVED_2__MASK 0x00000c00
> +#define CNA_CONV_CON1_RESERVED_2__SHIFT 10
> +static inline uint32_t CNA_CONV_CON1_RESERVED_2(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_RESERVED_2__SHIFT) & CNA_CONV_CON1_RESERVED_2__MASK;
> +}
> +#define CNA_CONV_CON1_PROC_PRECISION__MASK 0x00000380
> +#define CNA_CONV_CON1_PROC_PRECISION__SHIFT 7
> +static inline uint32_t CNA_CONV_CON1_PROC_PRECISION(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_PROC_PRECISION__SHIFT) & CNA_CONV_CON1_PROC_PRECISION__MASK;
> +}
> +#define CNA_CONV_CON1_IN_PRECISION__MASK 0x00000070
> +#define CNA_CONV_CON1_IN_PRECISION__SHIFT 4
> +static inline uint32_t CNA_CONV_CON1_IN_PRECISION(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_IN_PRECISION__SHIFT) & CNA_CONV_CON1_IN_PRECISION__MASK;
> +}
> +#define CNA_CONV_CON1_CONV_MODE__MASK 0x0000000f
> +#define CNA_CONV_CON1_CONV_MODE__SHIFT 0
> +static inline uint32_t CNA_CONV_CON1_CONV_MODE(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON1_CONV_MODE__SHIFT) & CNA_CONV_CON1_CONV_MODE__MASK;
> +}
> +
> +#define REG_CNA_CONV_CON2 0x00001010
> +#define CNA_CONV_CON2_RESERVED_0__MASK 0xff000000
> +#define CNA_CONV_CON2_RESERVED_0__SHIFT 24
> +static inline uint32_t CNA_CONV_CON2_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON2_RESERVED_0__SHIFT) & CNA_CONV_CON2_RESERVED_0__MASK;
> +}
> +#define CNA_CONV_CON2_KERNEL_GROUP__MASK 0x00ff0000
> +#define CNA_CONV_CON2_KERNEL_GROUP__SHIFT 16
> +static inline uint32_t CNA_CONV_CON2_KERNEL_GROUP(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON2_KERNEL_GROUP__SHIFT) & CNA_CONV_CON2_KERNEL_GROUP__MASK;
> +}
> +#define CNA_CONV_CON2_RESERVED_1__MASK 0x0000c000
> +#define CNA_CONV_CON2_RESERVED_1__SHIFT 14
> +static inline uint32_t CNA_CONV_CON2_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON2_RESERVED_1__SHIFT) & CNA_CONV_CON2_RESERVED_1__MASK;
> +}
> +#define CNA_CONV_CON2_FEATURE_GRAINS__MASK 0x00003ff0
> +#define CNA_CONV_CON2_FEATURE_GRAINS__SHIFT 4
> +static inline uint32_t CNA_CONV_CON2_FEATURE_GRAINS(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON2_FEATURE_GRAINS__SHIFT) & CNA_CONV_CON2_FEATURE_GRAINS__MASK;
> +}
> +#define CNA_CONV_CON2_RESERVED_2__MASK 0x00000008
> +#define CNA_CONV_CON2_RESERVED_2__SHIFT 3
> +static inline uint32_t CNA_CONV_CON2_RESERVED_2(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON2_RESERVED_2__SHIFT) & CNA_CONV_CON2_RESERVED_2__MASK;
> +}
> +#define CNA_CONV_CON2_CSC_WO_EN__MASK 0x00000004
> +#define CNA_CONV_CON2_CSC_WO_EN__SHIFT 2
> +static inline uint32_t CNA_CONV_CON2_CSC_WO_EN(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON2_CSC_WO_EN__SHIFT) & CNA_CONV_CON2_CSC_WO_EN__MASK;
> +}
> +#define CNA_CONV_CON2_CSC_DO_EN__MASK 0x00000002
> +#define CNA_CONV_CON2_CSC_DO_EN__SHIFT 1
> +static inline uint32_t CNA_CONV_CON2_CSC_DO_EN(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON2_CSC_DO_EN__SHIFT) & CNA_CONV_CON2_CSC_DO_EN__MASK;
> +}
> +#define CNA_CONV_CON2_CMD_FIFO_SRST__MASK 0x00000001
> +#define CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT 0
> +static inline uint32_t CNA_CONV_CON2_CMD_FIFO_SRST(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON2_CMD_FIFO_SRST__SHIFT) & CNA_CONV_CON2_CMD_FIFO_SRST__MASK;
> +}
> +
> +#define REG_CNA_CONV_CON3 0x00001014
> +#define CNA_CONV_CON3_RESERVED_0__MASK 0x80000000
> +#define CNA_CONV_CON3_RESERVED_0__SHIFT 31
> +static inline uint32_t CNA_CONV_CON3_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_RESERVED_0__SHIFT) & CNA_CONV_CON3_RESERVED_0__MASK;
> +}
> +#define CNA_CONV_CON3_NN_MODE__MASK 0x70000000
> +#define CNA_CONV_CON3_NN_MODE__SHIFT 28
> +static inline uint32_t CNA_CONV_CON3_NN_MODE(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_NN_MODE__SHIFT) & CNA_CONV_CON3_NN_MODE__MASK;
> +}
> +#define CNA_CONV_CON3_RESERVED_1__MASK 0x0c000000
> +#define CNA_CONV_CON3_RESERVED_1__SHIFT 26
> +static inline uint32_t CNA_CONV_CON3_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_RESERVED_1__SHIFT) & CNA_CONV_CON3_RESERVED_1__MASK;
> +}
> +#define CNA_CONV_CON3_ATROUS_Y_DILATION__MASK 0x03e00000
> +#define CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT 21
> +static inline uint32_t CNA_CONV_CON3_ATROUS_Y_DILATION(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_ATROUS_Y_DILATION__SHIFT) & CNA_CONV_CON3_ATROUS_Y_DILATION__MASK;
> +}
> +#define CNA_CONV_CON3_ATROUS_X_DILATION__MASK 0x001f0000
> +#define CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT 16
> +static inline uint32_t CNA_CONV_CON3_ATROUS_X_DILATION(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_ATROUS_X_DILATION__SHIFT) & CNA_CONV_CON3_ATROUS_X_DILATION__MASK;
> +}
> +#define CNA_CONV_CON3_RESERVED_2__MASK 0x0000c000
> +#define CNA_CONV_CON3_RESERVED_2__SHIFT 14
> +static inline uint32_t CNA_CONV_CON3_RESERVED_2(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_RESERVED_2__SHIFT) & CNA_CONV_CON3_RESERVED_2__MASK;
> +}
> +#define CNA_CONV_CON3_DECONV_Y_STRIDE__MASK 0x00003800
> +#define CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT 11
> +static inline uint32_t CNA_CONV_CON3_DECONV_Y_STRIDE(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_DECONV_Y_STRIDE__SHIFT) & CNA_CONV_CON3_DECONV_Y_STRIDE__MASK;
> +}
> +#define CNA_CONV_CON3_DECONV_X_STRIDE__MASK 0x00000700
> +#define CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT 8
> +static inline uint32_t CNA_CONV_CON3_DECONV_X_STRIDE(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_DECONV_X_STRIDE__SHIFT) & CNA_CONV_CON3_DECONV_X_STRIDE__MASK;
> +}
> +#define CNA_CONV_CON3_RESERVED_3__MASK 0x000000c0
> +#define CNA_CONV_CON3_RESERVED_3__SHIFT 6
> +static inline uint32_t CNA_CONV_CON3_RESERVED_3(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_RESERVED_3__SHIFT) & CNA_CONV_CON3_RESERVED_3__MASK;
> +}
> +#define CNA_CONV_CON3_CONV_Y_STRIDE__MASK 0x00000038
> +#define CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT 3
> +static inline uint32_t CNA_CONV_CON3_CONV_Y_STRIDE(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_CONV_Y_STRIDE__SHIFT) & CNA_CONV_CON3_CONV_Y_STRIDE__MASK;
> +}
> +#define CNA_CONV_CON3_CONV_X_STRIDE__MASK 0x00000007
> +#define CNA_CONV_CON3_CONV_X_STRIDE__SHIFT 0
> +static inline uint32_t CNA_CONV_CON3_CONV_X_STRIDE(uint32_t val)
> +{
> + return ((val) << CNA_CONV_CON3_CONV_X_STRIDE__SHIFT) & CNA_CONV_CON3_CONV_X_STRIDE__MASK;
> +}
> +
> +#define REG_CNA_DATA_SIZE0 0x00001020
> +#define CNA_DATA_SIZE0_RESERVED_0__MASK 0xf8000000
> +#define CNA_DATA_SIZE0_RESERVED_0__SHIFT 27
> +static inline uint32_t CNA_DATA_SIZE0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE0_RESERVED_0__SHIFT) & CNA_DATA_SIZE0_RESERVED_0__MASK;
> +}
> +#define CNA_DATA_SIZE0_DATAIN_WIDTH__MASK 0x07ff0000
> +#define CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT 16
> +static inline uint32_t CNA_DATA_SIZE0_DATAIN_WIDTH(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE0_DATAIN_WIDTH__SHIFT) & CNA_DATA_SIZE0_DATAIN_WIDTH__MASK;
> +}
> +#define CNA_DATA_SIZE0_RESERVED_1__MASK 0x0000f800
> +#define CNA_DATA_SIZE0_RESERVED_1__SHIFT 11
> +static inline uint32_t CNA_DATA_SIZE0_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE0_RESERVED_1__SHIFT) & CNA_DATA_SIZE0_RESERVED_1__MASK;
> +}
> +#define CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK 0x000007ff
> +#define CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT 0
> +static inline uint32_t CNA_DATA_SIZE0_DATAIN_HEIGHT(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE0_DATAIN_HEIGHT__SHIFT) & CNA_DATA_SIZE0_DATAIN_HEIGHT__MASK;
> +}
> +
> +#define REG_CNA_DATA_SIZE1 0x00001024
> +#define CNA_DATA_SIZE1_RESERVED_0__MASK 0xc0000000
> +#define CNA_DATA_SIZE1_RESERVED_0__SHIFT 30
> +static inline uint32_t CNA_DATA_SIZE1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE1_RESERVED_0__SHIFT) & CNA_DATA_SIZE1_RESERVED_0__MASK;
> +}
> +#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK 0x3fff0000
> +#define CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT 16
> +static inline uint32_t CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__SHIFT) & CNA_DATA_SIZE1_DATAIN_CHANNEL_REAL__MASK;
> +}
> +#define CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK 0x0000ffff
> +#define CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT 0
> +static inline uint32_t CNA_DATA_SIZE1_DATAIN_CHANNEL(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE1_DATAIN_CHANNEL__SHIFT) & CNA_DATA_SIZE1_DATAIN_CHANNEL__MASK;
> +}
> +
> +#define REG_CNA_DATA_SIZE2 0x00001028
> +#define CNA_DATA_SIZE2_RESERVED_0__MASK 0xfffff800
> +#define CNA_DATA_SIZE2_RESERVED_0__SHIFT 11
> +static inline uint32_t CNA_DATA_SIZE2_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE2_RESERVED_0__SHIFT) & CNA_DATA_SIZE2_RESERVED_0__MASK;
> +}
> +#define CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK 0x000007ff
> +#define CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT 0
> +static inline uint32_t CNA_DATA_SIZE2_DATAOUT_WIDTH(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE2_DATAOUT_WIDTH__SHIFT) & CNA_DATA_SIZE2_DATAOUT_WIDTH__MASK;
> +}
> +
> +#define REG_CNA_DATA_SIZE3 0x0000102c
> +#define CNA_DATA_SIZE3_RESERVED_0__MASK 0xff000000
> +#define CNA_DATA_SIZE3_RESERVED_0__SHIFT 24
> +static inline uint32_t CNA_DATA_SIZE3_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE3_RESERVED_0__SHIFT) & CNA_DATA_SIZE3_RESERVED_0__MASK;
> +}
> +#define CNA_DATA_SIZE3_SURF_MODE__MASK 0x00c00000
> +#define CNA_DATA_SIZE3_SURF_MODE__SHIFT 22
> +static inline uint32_t CNA_DATA_SIZE3_SURF_MODE(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE3_SURF_MODE__SHIFT) & CNA_DATA_SIZE3_SURF_MODE__MASK;
> +}
> +#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK 0x003fffff
> +#define CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT 0
> +static inline uint32_t CNA_DATA_SIZE3_DATAOUT_ATOMICS(uint32_t val)
> +{
> + return ((val) << CNA_DATA_SIZE3_DATAOUT_ATOMICS__SHIFT) & CNA_DATA_SIZE3_DATAOUT_ATOMICS__MASK;
> +}
> +
> +#define REG_CNA_WEIGHT_SIZE0 0x00001030
> +#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK 0xffffffff
> +#define CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT 0
> +static inline uint32_t CNA_WEIGHT_SIZE0_WEIGHT_BYTES(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE0_WEIGHT_BYTES__SHIFT) & CNA_WEIGHT_SIZE0_WEIGHT_BYTES__MASK;
> +}
> +
> +#define REG_CNA_WEIGHT_SIZE1 0x00001034
> +#define CNA_WEIGHT_SIZE1_RESERVED_0__MASK 0xfff80000
> +#define CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT 19
> +static inline uint32_t CNA_WEIGHT_SIZE1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE1_RESERVED_0__SHIFT) & CNA_WEIGHT_SIZE1_RESERVED_0__MASK;
> +}
> +#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK 0x0007ffff
> +#define CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT 0
> +static inline uint32_t CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__SHIFT) & CNA_WEIGHT_SIZE1_WEIGHT_BYTES_PER_KERNEL__MASK;
> +}
> +
> +#define REG_CNA_WEIGHT_SIZE2 0x00001038
> +#define CNA_WEIGHT_SIZE2_RESERVED_0__MASK 0xe0000000
> +#define CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT 29
> +static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE2_RESERVED_0__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_0__MASK;
> +}
> +#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK 0x1f000000
> +#define CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT 24
> +static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_WIDTH(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_WIDTH__MASK;
> +}
> +#define CNA_WEIGHT_SIZE2_RESERVED_1__MASK 0x00e00000
> +#define CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT 21
> +static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE2_RESERVED_1__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_1__MASK;
> +}
> +#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK 0x001f0000
> +#define CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT 16
> +static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_HEIGHT__MASK;
> +}
> +#define CNA_WEIGHT_SIZE2_RESERVED_2__MASK 0x0000c000
> +#define CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT 14
> +static inline uint32_t CNA_WEIGHT_SIZE2_RESERVED_2(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE2_RESERVED_2__SHIFT) & CNA_WEIGHT_SIZE2_RESERVED_2__MASK;
> +}
> +#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK 0x00003fff
> +#define CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT 0
> +static inline uint32_t CNA_WEIGHT_SIZE2_WEIGHT_KERNELS(uint32_t val)
> +{
> + return ((val) << CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__SHIFT) & CNA_WEIGHT_SIZE2_WEIGHT_KERNELS__MASK;
> +}
> +
> +#define REG_CNA_CBUF_CON0 0x00001040
> +#define CNA_CBUF_CON0_RESERVED_0__MASK 0xffffc000
> +#define CNA_CBUF_CON0_RESERVED_0__SHIFT 14
> +static inline uint32_t CNA_CBUF_CON0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON0_RESERVED_0__SHIFT) & CNA_CBUF_CON0_RESERVED_0__MASK;
> +}
> +#define CNA_CBUF_CON0_WEIGHT_REUSE__MASK 0x00002000
> +#define CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT 13
> +static inline uint32_t CNA_CBUF_CON0_WEIGHT_REUSE(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON0_WEIGHT_REUSE__SHIFT) & CNA_CBUF_CON0_WEIGHT_REUSE__MASK;
> +}
> +#define CNA_CBUF_CON0_DATA_REUSE__MASK 0x00001000
> +#define CNA_CBUF_CON0_DATA_REUSE__SHIFT 12
> +static inline uint32_t CNA_CBUF_CON0_DATA_REUSE(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON0_DATA_REUSE__SHIFT) & CNA_CBUF_CON0_DATA_REUSE__MASK;
> +}
> +#define CNA_CBUF_CON0_RESERVED_1__MASK 0x00000800
> +#define CNA_CBUF_CON0_RESERVED_1__SHIFT 11
> +static inline uint32_t CNA_CBUF_CON0_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON0_RESERVED_1__SHIFT) & CNA_CBUF_CON0_RESERVED_1__MASK;
> +}
> +#define CNA_CBUF_CON0_FC_DATA_BANK__MASK 0x00000700
> +#define CNA_CBUF_CON0_FC_DATA_BANK__SHIFT 8
> +static inline uint32_t CNA_CBUF_CON0_FC_DATA_BANK(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON0_FC_DATA_BANK__SHIFT) & CNA_CBUF_CON0_FC_DATA_BANK__MASK;
> +}
> +#define CNA_CBUF_CON0_WEIGHT_BANK__MASK 0x000000f0
> +#define CNA_CBUF_CON0_WEIGHT_BANK__SHIFT 4
> +static inline uint32_t CNA_CBUF_CON0_WEIGHT_BANK(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON0_WEIGHT_BANK__SHIFT) & CNA_CBUF_CON0_WEIGHT_BANK__MASK;
> +}
> +#define CNA_CBUF_CON0_DATA_BANK__MASK 0x0000000f
> +#define CNA_CBUF_CON0_DATA_BANK__SHIFT 0
> +static inline uint32_t CNA_CBUF_CON0_DATA_BANK(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON0_DATA_BANK__SHIFT) & CNA_CBUF_CON0_DATA_BANK__MASK;
> +}
> +
> +#define REG_CNA_CBUF_CON1 0x00001044
> +#define CNA_CBUF_CON1_RESERVED_0__MASK 0xffffc000
> +#define CNA_CBUF_CON1_RESERVED_0__SHIFT 14
> +static inline uint32_t CNA_CBUF_CON1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON1_RESERVED_0__SHIFT) & CNA_CBUF_CON1_RESERVED_0__MASK;
> +}
> +#define CNA_CBUF_CON1_DATA_ENTRIES__MASK 0x00003fff
> +#define CNA_CBUF_CON1_DATA_ENTRIES__SHIFT 0
> +static inline uint32_t CNA_CBUF_CON1_DATA_ENTRIES(uint32_t val)
> +{
> + return ((val) << CNA_CBUF_CON1_DATA_ENTRIES__SHIFT) & CNA_CBUF_CON1_DATA_ENTRIES__MASK;
> +}
> +
> +#define REG_CNA_CVT_CON0 0x0000104c
> +#define CNA_CVT_CON0_RESERVED_0__MASK 0xf0000000
> +#define CNA_CVT_CON0_RESERVED_0__SHIFT 28
> +static inline uint32_t CNA_CVT_CON0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_RESERVED_0__SHIFT) & CNA_CVT_CON0_RESERVED_0__MASK;
> +}
> +#define CNA_CVT_CON0_CVT_TRUNCATE_3__MASK 0x0fc00000
> +#define CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT 22
> +static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_3(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_3__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_3__MASK;
> +}
> +#define CNA_CVT_CON0_CVT_TRUNCATE_2__MASK 0x003f0000
> +#define CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT 16
> +static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_2(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_2__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_2__MASK;
> +}
> +#define CNA_CVT_CON0_CVT_TRUNCATE_1__MASK 0x0000fc00
> +#define CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT 10
> +static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_1(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_1__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_1__MASK;
> +}
> +#define CNA_CVT_CON0_CVT_TRUNCATE_0__MASK 0x000003f0
> +#define CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT 4
> +static inline uint32_t CNA_CVT_CON0_CVT_TRUNCATE_0(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_CVT_TRUNCATE_0__SHIFT) & CNA_CVT_CON0_CVT_TRUNCATE_0__MASK;
> +}
> +#define CNA_CVT_CON0_DATA_SIGN__MASK 0x00000008
> +#define CNA_CVT_CON0_DATA_SIGN__SHIFT 3
> +static inline uint32_t CNA_CVT_CON0_DATA_SIGN(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_DATA_SIGN__SHIFT) & CNA_CVT_CON0_DATA_SIGN__MASK;
> +}
> +#define CNA_CVT_CON0_ROUND_TYPE__MASK 0x00000004
> +#define CNA_CVT_CON0_ROUND_TYPE__SHIFT 2
> +static inline uint32_t CNA_CVT_CON0_ROUND_TYPE(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_ROUND_TYPE__SHIFT) & CNA_CVT_CON0_ROUND_TYPE__MASK;
> +}
> +#define CNA_CVT_CON0_CVT_TYPE__MASK 0x00000002
> +#define CNA_CVT_CON0_CVT_TYPE__SHIFT 1
> +static inline uint32_t CNA_CVT_CON0_CVT_TYPE(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_CVT_TYPE__SHIFT) & CNA_CVT_CON0_CVT_TYPE__MASK;
> +}
> +#define CNA_CVT_CON0_CVT_BYPASS__MASK 0x00000001
> +#define CNA_CVT_CON0_CVT_BYPASS__SHIFT 0
> +static inline uint32_t CNA_CVT_CON0_CVT_BYPASS(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON0_CVT_BYPASS__SHIFT) & CNA_CVT_CON0_CVT_BYPASS__MASK;
> +}
> +
> +#define REG_CNA_CVT_CON1 0x00001050
> +#define CNA_CVT_CON1_CVT_SCALE0__MASK 0xffff0000
> +#define CNA_CVT_CON1_CVT_SCALE0__SHIFT 16
> +static inline uint32_t CNA_CVT_CON1_CVT_SCALE0(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON1_CVT_SCALE0__SHIFT) & CNA_CVT_CON1_CVT_SCALE0__MASK;
> +}
> +#define CNA_CVT_CON1_CVT_OFFSET0__MASK 0x0000ffff
> +#define CNA_CVT_CON1_CVT_OFFSET0__SHIFT 0
> +static inline uint32_t CNA_CVT_CON1_CVT_OFFSET0(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON1_CVT_OFFSET0__SHIFT) & CNA_CVT_CON1_CVT_OFFSET0__MASK;
> +}
> +
> +#define REG_CNA_CVT_CON2 0x00001054
> +#define CNA_CVT_CON2_CVT_SCALE1__MASK 0xffff0000
> +#define CNA_CVT_CON2_CVT_SCALE1__SHIFT 16
> +static inline uint32_t CNA_CVT_CON2_CVT_SCALE1(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON2_CVT_SCALE1__SHIFT) & CNA_CVT_CON2_CVT_SCALE1__MASK;
> +}
> +#define CNA_CVT_CON2_CVT_OFFSET1__MASK 0x0000ffff
> +#define CNA_CVT_CON2_CVT_OFFSET1__SHIFT 0
> +static inline uint32_t CNA_CVT_CON2_CVT_OFFSET1(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON2_CVT_OFFSET1__SHIFT) & CNA_CVT_CON2_CVT_OFFSET1__MASK;
> +}
> +
> +#define REG_CNA_CVT_CON3 0x00001058
> +#define CNA_CVT_CON3_CVT_SCALE2__MASK 0xffff0000
> +#define CNA_CVT_CON3_CVT_SCALE2__SHIFT 16
> +static inline uint32_t CNA_CVT_CON3_CVT_SCALE2(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON3_CVT_SCALE2__SHIFT) & CNA_CVT_CON3_CVT_SCALE2__MASK;
> +}
> +#define CNA_CVT_CON3_CVT_OFFSET2__MASK 0x0000ffff
> +#define CNA_CVT_CON3_CVT_OFFSET2__SHIFT 0
> +static inline uint32_t CNA_CVT_CON3_CVT_OFFSET2(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON3_CVT_OFFSET2__SHIFT) & CNA_CVT_CON3_CVT_OFFSET2__MASK;
> +}
> +
> +#define REG_CNA_CVT_CON4 0x0000105c
> +#define CNA_CVT_CON4_CVT_SCALE3__MASK 0xffff0000
> +#define CNA_CVT_CON4_CVT_SCALE3__SHIFT 16
> +static inline uint32_t CNA_CVT_CON4_CVT_SCALE3(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON4_CVT_SCALE3__SHIFT) & CNA_CVT_CON4_CVT_SCALE3__MASK;
> +}
> +#define CNA_CVT_CON4_CVT_OFFSET3__MASK 0x0000ffff
> +#define CNA_CVT_CON4_CVT_OFFSET3__SHIFT 0
> +static inline uint32_t CNA_CVT_CON4_CVT_OFFSET3(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON4_CVT_OFFSET3__SHIFT) & CNA_CVT_CON4_CVT_OFFSET3__MASK;
> +}
> +
> +#define REG_CNA_FC_CON0 0x00001060
> +#define CNA_FC_CON0_FC_SKIP_DATA__MASK 0xffff0000
> +#define CNA_FC_CON0_FC_SKIP_DATA__SHIFT 16
> +static inline uint32_t CNA_FC_CON0_FC_SKIP_DATA(uint32_t val)
> +{
> + return ((val) << CNA_FC_CON0_FC_SKIP_DATA__SHIFT) & CNA_FC_CON0_FC_SKIP_DATA__MASK;
> +}
> +#define CNA_FC_CON0_RESERVED_0__MASK 0x0000fffe
> +#define CNA_FC_CON0_RESERVED_0__SHIFT 1
> +static inline uint32_t CNA_FC_CON0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_FC_CON0_RESERVED_0__SHIFT) & CNA_FC_CON0_RESERVED_0__MASK;
> +}
> +#define CNA_FC_CON0_FC_SKIP_EN__MASK 0x00000001
> +#define CNA_FC_CON0_FC_SKIP_EN__SHIFT 0
> +static inline uint32_t CNA_FC_CON0_FC_SKIP_EN(uint32_t val)
> +{
> + return ((val) << CNA_FC_CON0_FC_SKIP_EN__SHIFT) & CNA_FC_CON0_FC_SKIP_EN__MASK;
> +}
> +
> +#define REG_CNA_FC_CON1 0x00001064
> +#define CNA_FC_CON1_RESERVED_0__MASK 0xfffe0000
> +#define CNA_FC_CON1_RESERVED_0__SHIFT 17
> +static inline uint32_t CNA_FC_CON1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_FC_CON1_RESERVED_0__SHIFT) & CNA_FC_CON1_RESERVED_0__MASK;
> +}
> +#define CNA_FC_CON1_DATA_OFFSET__MASK 0x0001ffff
> +#define CNA_FC_CON1_DATA_OFFSET__SHIFT 0
> +static inline uint32_t CNA_FC_CON1_DATA_OFFSET(uint32_t val)
> +{
> + return ((val) << CNA_FC_CON1_DATA_OFFSET__SHIFT) & CNA_FC_CON1_DATA_OFFSET__MASK;
> +}
> +
> +#define REG_CNA_PAD_CON0 0x00001068
> +#define CNA_PAD_CON0_RESERVED_0__MASK 0xffffff00
> +#define CNA_PAD_CON0_RESERVED_0__SHIFT 8
> +static inline uint32_t CNA_PAD_CON0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_PAD_CON0_RESERVED_0__SHIFT) & CNA_PAD_CON0_RESERVED_0__MASK;
> +}
> +#define CNA_PAD_CON0_PAD_LEFT__MASK 0x000000f0
> +#define CNA_PAD_CON0_PAD_LEFT__SHIFT 4
> +static inline uint32_t CNA_PAD_CON0_PAD_LEFT(uint32_t val)
> +{
> + return ((val) << CNA_PAD_CON0_PAD_LEFT__SHIFT) & CNA_PAD_CON0_PAD_LEFT__MASK;
> +}
> +#define CNA_PAD_CON0_PAD_TOP__MASK 0x0000000f
> +#define CNA_PAD_CON0_PAD_TOP__SHIFT 0
> +static inline uint32_t CNA_PAD_CON0_PAD_TOP(uint32_t val)
> +{
> + return ((val) << CNA_PAD_CON0_PAD_TOP__SHIFT) & CNA_PAD_CON0_PAD_TOP__MASK;
> +}
> +
> +#define REG_CNA_FEATURE_DATA_ADDR 0x00001070
> +#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK 0xffffffff
> +#define CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT 0
> +static inline uint32_t CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__SHIFT) & CNA_FEATURE_DATA_ADDR_FEATURE_BASE_ADDR__MASK;
> +}
> +
> +#define REG_CNA_FC_CON2 0x00001074
> +#define CNA_FC_CON2_RESERVED_0__MASK 0xfffe0000
> +#define CNA_FC_CON2_RESERVED_0__SHIFT 17
> +static inline uint32_t CNA_FC_CON2_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_FC_CON2_RESERVED_0__SHIFT) & CNA_FC_CON2_RESERVED_0__MASK;
> +}
> +#define CNA_FC_CON2_WEIGHT_OFFSET__MASK 0x0001ffff
> +#define CNA_FC_CON2_WEIGHT_OFFSET__SHIFT 0
> +static inline uint32_t CNA_FC_CON2_WEIGHT_OFFSET(uint32_t val)
> +{
> + return ((val) << CNA_FC_CON2_WEIGHT_OFFSET__SHIFT) & CNA_FC_CON2_WEIGHT_OFFSET__MASK;
> +}
> +
> +#define REG_CNA_DMA_CON0 0x00001078
> +#define CNA_DMA_CON0_OV4K_BYPASS__MASK 0x80000000
> +#define CNA_DMA_CON0_OV4K_BYPASS__SHIFT 31
> +static inline uint32_t CNA_DMA_CON0_OV4K_BYPASS(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON0_OV4K_BYPASS__SHIFT) & CNA_DMA_CON0_OV4K_BYPASS__MASK;
> +}
> +#define CNA_DMA_CON0_RESERVED_0__MASK 0x7ff00000
> +#define CNA_DMA_CON0_RESERVED_0__SHIFT 20
> +static inline uint32_t CNA_DMA_CON0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON0_RESERVED_0__SHIFT) & CNA_DMA_CON0_RESERVED_0__MASK;
> +}
> +#define CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK 0x000f0000
> +#define CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT 16
> +static inline uint32_t CNA_DMA_CON0_WEIGHT_BURST_LEN(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON0_WEIGHT_BURST_LEN__SHIFT) & CNA_DMA_CON0_WEIGHT_BURST_LEN__MASK;
> +}
> +#define CNA_DMA_CON0_RESERVED_1__MASK 0x0000fff0
> +#define CNA_DMA_CON0_RESERVED_1__SHIFT 4
> +static inline uint32_t CNA_DMA_CON0_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON0_RESERVED_1__SHIFT) & CNA_DMA_CON0_RESERVED_1__MASK;
> +}
> +#define CNA_DMA_CON0_DATA_BURST_LEN__MASK 0x0000000f
> +#define CNA_DMA_CON0_DATA_BURST_LEN__SHIFT 0
> +static inline uint32_t CNA_DMA_CON0_DATA_BURST_LEN(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON0_DATA_BURST_LEN__SHIFT) & CNA_DMA_CON0_DATA_BURST_LEN__MASK;
> +}
> +
> +#define REG_CNA_DMA_CON1 0x0000107c
> +#define CNA_DMA_CON1_RESERVED_0__MASK 0xf0000000
> +#define CNA_DMA_CON1_RESERVED_0__SHIFT 28
> +static inline uint32_t CNA_DMA_CON1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON1_RESERVED_0__SHIFT) & CNA_DMA_CON1_RESERVED_0__MASK;
> +}
> +#define CNA_DMA_CON1_LINE_STRIDE__MASK 0x0fffffff
> +#define CNA_DMA_CON1_LINE_STRIDE__SHIFT 0
> +static inline uint32_t CNA_DMA_CON1_LINE_STRIDE(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON1_LINE_STRIDE__SHIFT) & CNA_DMA_CON1_LINE_STRIDE__MASK;
> +}
> +
> +#define REG_CNA_DMA_CON2 0x00001080
> +#define CNA_DMA_CON2_RESERVED_0__MASK 0xf0000000
> +#define CNA_DMA_CON2_RESERVED_0__SHIFT 28
> +static inline uint32_t CNA_DMA_CON2_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON2_RESERVED_0__SHIFT) & CNA_DMA_CON2_RESERVED_0__MASK;
> +}
> +#define CNA_DMA_CON2_SURF_STRIDE__MASK 0x0fffffff
> +#define CNA_DMA_CON2_SURF_STRIDE__SHIFT 0
> +static inline uint32_t CNA_DMA_CON2_SURF_STRIDE(uint32_t val)
> +{
> + return ((val) << CNA_DMA_CON2_SURF_STRIDE__SHIFT) & CNA_DMA_CON2_SURF_STRIDE__MASK;
> +}
> +
> +#define REG_CNA_FC_DATA_SIZE0 0x00001084
> +#define CNA_FC_DATA_SIZE0_RESERVED_0__MASK 0xc0000000
> +#define CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT 30
> +static inline uint32_t CNA_FC_DATA_SIZE0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_FC_DATA_SIZE0_RESERVED_0__SHIFT) & CNA_FC_DATA_SIZE0_RESERVED_0__MASK;
> +}
> +#define CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK 0x3fff0000
> +#define CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT 16
> +static inline uint32_t CNA_FC_DATA_SIZE0_DMA_WIDTH(uint32_t val)
> +{
> + return ((val) << CNA_FC_DATA_SIZE0_DMA_WIDTH__SHIFT) & CNA_FC_DATA_SIZE0_DMA_WIDTH__MASK;
> +}
> +#define CNA_FC_DATA_SIZE0_RESERVED_1__MASK 0x0000f800
> +#define CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT 11
> +static inline uint32_t CNA_FC_DATA_SIZE0_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_FC_DATA_SIZE0_RESERVED_1__SHIFT) & CNA_FC_DATA_SIZE0_RESERVED_1__MASK;
> +}
> +#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK 0x000007ff
> +#define CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT 0
> +static inline uint32_t CNA_FC_DATA_SIZE0_DMA_HEIGHT(uint32_t val)
> +{
> + return ((val) << CNA_FC_DATA_SIZE0_DMA_HEIGHT__SHIFT) & CNA_FC_DATA_SIZE0_DMA_HEIGHT__MASK;
> +}
> +
> +#define REG_CNA_FC_DATA_SIZE1 0x00001088
> +#define CNA_FC_DATA_SIZE1_RESERVED_0__MASK 0xffff0000
> +#define CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT 16
> +static inline uint32_t CNA_FC_DATA_SIZE1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_FC_DATA_SIZE1_RESERVED_0__SHIFT) & CNA_FC_DATA_SIZE1_RESERVED_0__MASK;
> +}
> +#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK 0x0000ffff
> +#define CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT 0
> +static inline uint32_t CNA_FC_DATA_SIZE1_DMA_CHANNEL(uint32_t val)
> +{
> + return ((val) << CNA_FC_DATA_SIZE1_DMA_CHANNEL__SHIFT) & CNA_FC_DATA_SIZE1_DMA_CHANNEL__MASK;
> +}
> +
> +#define REG_CNA_CLK_GATE 0x00001090
> +#define CNA_CLK_GATE_RESERVED_0__MASK 0xffffffe0
> +#define CNA_CLK_GATE_RESERVED_0__SHIFT 5
> +static inline uint32_t CNA_CLK_GATE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_CLK_GATE_RESERVED_0__SHIFT) & CNA_CLK_GATE_RESERVED_0__MASK;
> +}
> +#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK 0x00000010
> +#define CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT 4
> +static inline uint32_t CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE(uint32_t val)
> +{
> + return ((val) << CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CBUF_CS_DISABLE_CLKGATE__MASK;
> +}
> +#define CNA_CLK_GATE_RESERVED_1__MASK 0x00000008
> +#define CNA_CLK_GATE_RESERVED_1__SHIFT 3
> +static inline uint32_t CNA_CLK_GATE_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CNA_CLK_GATE_RESERVED_1__SHIFT) & CNA_CLK_GATE_RESERVED_1__MASK;
> +}
> +#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK 0x00000004
> +#define CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT 2
> +static inline uint32_t CNA_CLK_GATE_CSC_DISABLE_CLKGATE(uint32_t val)
> +{
> + return ((val) << CNA_CLK_GATE_CSC_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CSC_DISABLE_CLKGATE__MASK;
> +}
> +#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK 0x00000002
> +#define CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT 1
> +static inline uint32_t CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE(uint32_t val)
> +{
> + return ((val) << CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CNA_WEIGHT_DISABLE_CLKGATE__MASK;
> +}
> +#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK 0x00000001
> +#define CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT 0
> +static inline uint32_t CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE(uint32_t val)
> +{
> + return ((val) << CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__SHIFT) & CNA_CLK_GATE_CNA_FEATURE_DISABLE_CLKGATE__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_CTRL 0x00001100
> +#define CNA_DCOMP_CTRL_RESERVED_0__MASK 0xfffffff0
> +#define CNA_DCOMP_CTRL_RESERVED_0__SHIFT 4
> +static inline uint32_t CNA_DCOMP_CTRL_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_CTRL_RESERVED_0__SHIFT) & CNA_DCOMP_CTRL_RESERVED_0__MASK;
> +}
> +#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK 0x00000008
> +#define CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT 3
> +static inline uint32_t CNA_DCOMP_CTRL_WT_DEC_BYPASS(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_CTRL_WT_DEC_BYPASS__SHIFT) & CNA_DCOMP_CTRL_WT_DEC_BYPASS__MASK;
> +}
> +#define CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK 0x00000007
> +#define CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT 0
> +static inline uint32_t CNA_DCOMP_CTRL_DECOMP_CONTROL(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_CTRL_DECOMP_CONTROL__SHIFT) & CNA_DCOMP_CTRL_DECOMP_CONTROL__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_REGNUM 0x00001104
> +#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK 0xffffffff
> +#define CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT 0
> +static inline uint32_t CNA_DCOMP_REGNUM_DCOMP_REGNUM(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_REGNUM_DCOMP_REGNUM__SHIFT) & CNA_DCOMP_REGNUM_DCOMP_REGNUM__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_ADDR0 0x00001110
> +#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK 0xffffffff
> +#define CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT 0
> +static inline uint32_t CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__SHIFT) & CNA_DCOMP_ADDR0_DECOMPRESS_ADDR0__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT0 0x00001140
> +#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__SHIFT) & CNA_DCOMP_AMOUNT0_DCOMP_AMOUNT0__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT1 0x00001144
> +#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__SHIFT) & CNA_DCOMP_AMOUNT1_DCOMP_AMOUNT1__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT2 0x00001148
> +#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__SHIFT) & CNA_DCOMP_AMOUNT2_DCOMP_AMOUNT2__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT3 0x0000114c
> +#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__SHIFT) & CNA_DCOMP_AMOUNT3_DCOMP_AMOUNT3__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT4 0x00001150
> +#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__SHIFT) & CNA_DCOMP_AMOUNT4_DCOMP_AMOUNT4__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT5 0x00001154
> +#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__SHIFT) & CNA_DCOMP_AMOUNT5_DCOMP_AMOUNT5__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT6 0x00001158
> +#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__SHIFT) & CNA_DCOMP_AMOUNT6_DCOMP_AMOUNT6__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT7 0x0000115c
> +#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__SHIFT) & CNA_DCOMP_AMOUNT7_DCOMP_AMOUNT7__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT8 0x00001160
> +#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__SHIFT) & CNA_DCOMP_AMOUNT8_DCOMP_AMOUNT8__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT9 0x00001164
> +#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__SHIFT) & CNA_DCOMP_AMOUNT9_DCOMP_AMOUNT9__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT10 0x00001168
> +#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__SHIFT) & CNA_DCOMP_AMOUNT10_DCOMP_AMOUNT10__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT11 0x0000116c
> +#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__SHIFT) & CNA_DCOMP_AMOUNT11_DCOMP_AMOUNT11__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT12 0x00001170
> +#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__SHIFT) & CNA_DCOMP_AMOUNT12_DCOMP_AMOUNT12__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT13 0x00001174
> +#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__SHIFT) & CNA_DCOMP_AMOUNT13_DCOMP_AMOUNT13__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT14 0x00001178
> +#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__SHIFT) & CNA_DCOMP_AMOUNT14_DCOMP_AMOUNT14__MASK;
> +}
> +
> +#define REG_CNA_DCOMP_AMOUNT15 0x0000117c
> +#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK 0xffffffff
> +#define CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT 0
> +static inline uint32_t CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15(uint32_t val)
> +{
> + return ((val) << CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__SHIFT) & CNA_DCOMP_AMOUNT15_DCOMP_AMOUNT15__MASK;
> +}
> +
> +#define REG_CNA_CVT_CON5 0x00001180
> +#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK 0xffffffff
> +#define CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT 0
> +static inline uint32_t CNA_CVT_CON5_PER_CHANNEL_CVT_EN(uint32_t val)
> +{
> + return ((val) << CNA_CVT_CON5_PER_CHANNEL_CVT_EN__SHIFT) & CNA_CVT_CON5_PER_CHANNEL_CVT_EN__MASK;
> +}
> +
> +#define REG_CNA_PAD_CON1 0x00001184
> +#define CNA_PAD_CON1_PAD_VALUE__MASK 0xffffffff
> +#define CNA_PAD_CON1_PAD_VALUE__SHIFT 0
> +static inline uint32_t CNA_PAD_CON1_PAD_VALUE(uint32_t val)
> +{
> + return ((val) << CNA_PAD_CON1_PAD_VALUE__SHIFT) & CNA_PAD_CON1_PAD_VALUE__MASK;
> +}
> +
> +#define REG_CORE_S_STATUS 0x00003000
> +#define CORE_S_STATUS_RESERVED_0__MASK 0xfffc0000
> +#define CORE_S_STATUS_RESERVED_0__SHIFT 18
> +static inline uint32_t CORE_S_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CORE_S_STATUS_RESERVED_0__SHIFT) & CORE_S_STATUS_RESERVED_0__MASK;
> +}
> +#define CORE_S_STATUS_STATUS_1__MASK 0x00030000
> +#define CORE_S_STATUS_STATUS_1__SHIFT 16
> +static inline uint32_t CORE_S_STATUS_STATUS_1(uint32_t val)
> +{
> + return ((val) << CORE_S_STATUS_STATUS_1__SHIFT) & CORE_S_STATUS_STATUS_1__MASK;
> +}
> +#define CORE_S_STATUS_RESERVED_1__MASK 0x0000fffc
> +#define CORE_S_STATUS_RESERVED_1__SHIFT 2
> +static inline uint32_t CORE_S_STATUS_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CORE_S_STATUS_RESERVED_1__SHIFT) & CORE_S_STATUS_RESERVED_1__MASK;
> +}
> +#define CORE_S_STATUS_STATUS_0__MASK 0x00000003
> +#define CORE_S_STATUS_STATUS_0__SHIFT 0
> +static inline uint32_t CORE_S_STATUS_STATUS_0(uint32_t val)
> +{
> + return ((val) << CORE_S_STATUS_STATUS_0__SHIFT) & CORE_S_STATUS_STATUS_0__MASK;
> +}
> +
> +#define REG_CORE_S_POINTER 0x00003004
> +#define CORE_S_POINTER_RESERVED_0__MASK 0xfffe0000
> +#define CORE_S_POINTER_RESERVED_0__SHIFT 17
> +static inline uint32_t CORE_S_POINTER_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_RESERVED_0__SHIFT) & CORE_S_POINTER_RESERVED_0__MASK;
> +}
> +#define CORE_S_POINTER_EXECUTER__MASK 0x00010000
> +#define CORE_S_POINTER_EXECUTER__SHIFT 16
> +static inline uint32_t CORE_S_POINTER_EXECUTER(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_EXECUTER__SHIFT) & CORE_S_POINTER_EXECUTER__MASK;
> +}
> +#define CORE_S_POINTER_RESERVED_1__MASK 0x0000ffc0
> +#define CORE_S_POINTER_RESERVED_1__SHIFT 6
> +static inline uint32_t CORE_S_POINTER_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_RESERVED_1__SHIFT) & CORE_S_POINTER_RESERVED_1__MASK;
> +}
> +#define CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
> +#define CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
> +static inline uint32_t CORE_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & CORE_S_POINTER_EXECUTER_PP_CLEAR__MASK;
> +}
> +#define CORE_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
> +#define CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
> +static inline uint32_t CORE_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_POINTER_PP_CLEAR__SHIFT) & CORE_S_POINTER_POINTER_PP_CLEAR__MASK;
> +}
> +#define CORE_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
> +#define CORE_S_POINTER_POINTER_PP_MODE__SHIFT 3
> +static inline uint32_t CORE_S_POINTER_POINTER_PP_MODE(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_POINTER_PP_MODE__SHIFT) & CORE_S_POINTER_POINTER_PP_MODE__MASK;
> +}
> +#define CORE_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
> +#define CORE_S_POINTER_EXECUTER_PP_EN__SHIFT 2
> +static inline uint32_t CORE_S_POINTER_EXECUTER_PP_EN(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_EXECUTER_PP_EN__SHIFT) & CORE_S_POINTER_EXECUTER_PP_EN__MASK;
> +}
> +#define CORE_S_POINTER_POINTER_PP_EN__MASK 0x00000002
> +#define CORE_S_POINTER_POINTER_PP_EN__SHIFT 1
> +static inline uint32_t CORE_S_POINTER_POINTER_PP_EN(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_POINTER_PP_EN__SHIFT) & CORE_S_POINTER_POINTER_PP_EN__MASK;
> +}
> +#define CORE_S_POINTER_POINTER__MASK 0x00000001
> +#define CORE_S_POINTER_POINTER__SHIFT 0
> +static inline uint32_t CORE_S_POINTER_POINTER(uint32_t val)
> +{
> + return ((val) << CORE_S_POINTER_POINTER__SHIFT) & CORE_S_POINTER_POINTER__MASK;
> +}
> +
> +#define REG_CORE_OPERATION_ENABLE 0x00003008
> +#define CORE_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
> +#define CORE_OPERATION_ENABLE_RESERVED_0__SHIFT 1
> +static inline uint32_t CORE_OPERATION_ENABLE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CORE_OPERATION_ENABLE_RESERVED_0__SHIFT) & CORE_OPERATION_ENABLE_RESERVED_0__MASK;
> +}
> +#define CORE_OPERATION_ENABLE_OP_EN__MASK 0x00000001
> +#define CORE_OPERATION_ENABLE_OP_EN__SHIFT 0
> +static inline uint32_t CORE_OPERATION_ENABLE_OP_EN(uint32_t val)
> +{
> + return ((val) << CORE_OPERATION_ENABLE_OP_EN__SHIFT) & CORE_OPERATION_ENABLE_OP_EN__MASK;
> +}
> +
> +#define REG_CORE_MAC_GATING 0x0000300c
> +#define CORE_MAC_GATING_RESERVED_0__MASK 0xf8000000
> +#define CORE_MAC_GATING_RESERVED_0__SHIFT 27
> +static inline uint32_t CORE_MAC_GATING_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CORE_MAC_GATING_RESERVED_0__SHIFT) & CORE_MAC_GATING_RESERVED_0__MASK;
> +}
> +#define CORE_MAC_GATING_SLCG_OP_EN__MASK 0x07ffffff
> +#define CORE_MAC_GATING_SLCG_OP_EN__SHIFT 0
> +static inline uint32_t CORE_MAC_GATING_SLCG_OP_EN(uint32_t val)
> +{
> + return ((val) << CORE_MAC_GATING_SLCG_OP_EN__SHIFT) & CORE_MAC_GATING_SLCG_OP_EN__MASK;
> +}
> +
> +#define REG_CORE_MISC_CFG 0x00003010
> +#define CORE_MISC_CFG_RESERVED_0__MASK 0xfff00000
> +#define CORE_MISC_CFG_RESERVED_0__SHIFT 20
> +static inline uint32_t CORE_MISC_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CORE_MISC_CFG_RESERVED_0__SHIFT) & CORE_MISC_CFG_RESERVED_0__MASK;
> +}
> +#define CORE_MISC_CFG_SOFT_GATING__MASK 0x000fc000
> +#define CORE_MISC_CFG_SOFT_GATING__SHIFT 14
> +static inline uint32_t CORE_MISC_CFG_SOFT_GATING(uint32_t val)
> +{
> + return ((val) << CORE_MISC_CFG_SOFT_GATING__SHIFT) & CORE_MISC_CFG_SOFT_GATING__MASK;
> +}
> +#define CORE_MISC_CFG_RESERVED_1__MASK 0x00003800
> +#define CORE_MISC_CFG_RESERVED_1__SHIFT 11
> +static inline uint32_t CORE_MISC_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CORE_MISC_CFG_RESERVED_1__SHIFT) & CORE_MISC_CFG_RESERVED_1__MASK;
> +}
> +#define CORE_MISC_CFG_PROC_PRECISION__MASK 0x00000700
> +#define CORE_MISC_CFG_PROC_PRECISION__SHIFT 8
> +static inline uint32_t CORE_MISC_CFG_PROC_PRECISION(uint32_t val)
> +{
> + return ((val) << CORE_MISC_CFG_PROC_PRECISION__SHIFT) & CORE_MISC_CFG_PROC_PRECISION__MASK;
> +}
> +#define CORE_MISC_CFG_RESERVED_2__MASK 0x000000fc
> +#define CORE_MISC_CFG_RESERVED_2__SHIFT 2
> +static inline uint32_t CORE_MISC_CFG_RESERVED_2(uint32_t val)
> +{
> + return ((val) << CORE_MISC_CFG_RESERVED_2__SHIFT) & CORE_MISC_CFG_RESERVED_2__MASK;
> +}
> +#define CORE_MISC_CFG_DW_EN__MASK 0x00000002
> +#define CORE_MISC_CFG_DW_EN__SHIFT 1
> +static inline uint32_t CORE_MISC_CFG_DW_EN(uint32_t val)
> +{
> + return ((val) << CORE_MISC_CFG_DW_EN__SHIFT) & CORE_MISC_CFG_DW_EN__MASK;
> +}
> +#define CORE_MISC_CFG_QD_EN__MASK 0x00000001
> +#define CORE_MISC_CFG_QD_EN__SHIFT 0
> +static inline uint32_t CORE_MISC_CFG_QD_EN(uint32_t val)
> +{
> + return ((val) << CORE_MISC_CFG_QD_EN__SHIFT) & CORE_MISC_CFG_QD_EN__MASK;
> +}
> +
> +#define REG_CORE_DATAOUT_SIZE_0 0x00003014
> +#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK 0xffff0000
> +#define CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT 16
> +static inline uint32_t CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT(uint32_t val)
> +{
> + return ((val) << CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__SHIFT) & CORE_DATAOUT_SIZE_0_DATAOUT_HEIGHT__MASK;
> +}
> +#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK 0x0000ffff
> +#define CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT 0
> +static inline uint32_t CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH(uint32_t val)
> +{
> + return ((val) << CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__SHIFT) & CORE_DATAOUT_SIZE_0_DATAOUT_WIDTH__MASK;
> +}
> +
> +#define REG_CORE_DATAOUT_SIZE_1 0x00003018
> +#define CORE_DATAOUT_SIZE_1_RESERVED_0__MASK 0xffff0000
> +#define CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT 16
> +static inline uint32_t CORE_DATAOUT_SIZE_1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CORE_DATAOUT_SIZE_1_RESERVED_0__SHIFT) & CORE_DATAOUT_SIZE_1_RESERVED_0__MASK;
> +}
> +#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK 0x0000ffff
> +#define CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT 0
> +static inline uint32_t CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL(uint32_t val)
> +{
> + return ((val) << CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__SHIFT) & CORE_DATAOUT_SIZE_1_DATAOUT_CHANNEL__MASK;
> +}
> +
> +#define REG_CORE_CLIP_TRUNCATE 0x0000301c
> +#define CORE_CLIP_TRUNCATE_RESERVED_0__MASK 0xffffff80
> +#define CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT 7
> +static inline uint32_t CORE_CLIP_TRUNCATE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << CORE_CLIP_TRUNCATE_RESERVED_0__SHIFT) & CORE_CLIP_TRUNCATE_RESERVED_0__MASK;
> +}
> +#define CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK 0x00000040
> +#define CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT 6
> +static inline uint32_t CORE_CLIP_TRUNCATE_ROUND_TYPE(uint32_t val)
> +{
> + return ((val) << CORE_CLIP_TRUNCATE_ROUND_TYPE__SHIFT) & CORE_CLIP_TRUNCATE_ROUND_TYPE__MASK;
> +}
> +#define CORE_CLIP_TRUNCATE_RESERVED_1__MASK 0x00000020
> +#define CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT 5
> +static inline uint32_t CORE_CLIP_TRUNCATE_RESERVED_1(uint32_t val)
> +{
> + return ((val) << CORE_CLIP_TRUNCATE_RESERVED_1__SHIFT) & CORE_CLIP_TRUNCATE_RESERVED_1__MASK;
> +}
> +#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK 0x0000001f
> +#define CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT 0
> +static inline uint32_t CORE_CLIP_TRUNCATE_CLIP_TRUNCATE(uint32_t val)
> +{
> + return ((val) << CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__SHIFT) & CORE_CLIP_TRUNCATE_CLIP_TRUNCATE__MASK;
> +}
> +
> +#define REG_DPU_S_STATUS 0x00004000
> +#define DPU_S_STATUS_RESERVED_0__MASK 0xfffc0000
> +#define DPU_S_STATUS_RESERVED_0__SHIFT 18
> +static inline uint32_t DPU_S_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_S_STATUS_RESERVED_0__SHIFT) & DPU_S_STATUS_RESERVED_0__MASK;
> +}
> +#define DPU_S_STATUS_STATUS_1__MASK 0x00030000
> +#define DPU_S_STATUS_STATUS_1__SHIFT 16
> +static inline uint32_t DPU_S_STATUS_STATUS_1(uint32_t val)
> +{
> + return ((val) << DPU_S_STATUS_STATUS_1__SHIFT) & DPU_S_STATUS_STATUS_1__MASK;
> +}
> +#define DPU_S_STATUS_RESERVED_1__MASK 0x0000fffc
> +#define DPU_S_STATUS_RESERVED_1__SHIFT 2
> +static inline uint32_t DPU_S_STATUS_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_S_STATUS_RESERVED_1__SHIFT) & DPU_S_STATUS_RESERVED_1__MASK;
> +}
> +#define DPU_S_STATUS_STATUS_0__MASK 0x00000003
> +#define DPU_S_STATUS_STATUS_0__SHIFT 0
> +static inline uint32_t DPU_S_STATUS_STATUS_0(uint32_t val)
> +{
> + return ((val) << DPU_S_STATUS_STATUS_0__SHIFT) & DPU_S_STATUS_STATUS_0__MASK;
> +}
> +
> +#define REG_DPU_S_POINTER 0x00004004
> +#define DPU_S_POINTER_RESERVED_0__MASK 0xfffe0000
> +#define DPU_S_POINTER_RESERVED_0__SHIFT 17
> +static inline uint32_t DPU_S_POINTER_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_RESERVED_0__SHIFT) & DPU_S_POINTER_RESERVED_0__MASK;
> +}
> +#define DPU_S_POINTER_EXECUTER__MASK 0x00010000
> +#define DPU_S_POINTER_EXECUTER__SHIFT 16
> +static inline uint32_t DPU_S_POINTER_EXECUTER(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_EXECUTER__SHIFT) & DPU_S_POINTER_EXECUTER__MASK;
> +}
> +#define DPU_S_POINTER_RESERVED_1__MASK 0x0000ffc0
> +#define DPU_S_POINTER_RESERVED_1__SHIFT 6
> +static inline uint32_t DPU_S_POINTER_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_RESERVED_1__SHIFT) & DPU_S_POINTER_RESERVED_1__MASK;
> +}
> +#define DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
> +#define DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
> +static inline uint32_t DPU_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & DPU_S_POINTER_EXECUTER_PP_CLEAR__MASK;
> +}
> +#define DPU_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
> +#define DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
> +static inline uint32_t DPU_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_POINTER_PP_CLEAR__SHIFT) & DPU_S_POINTER_POINTER_PP_CLEAR__MASK;
> +}
> +#define DPU_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
> +#define DPU_S_POINTER_POINTER_PP_MODE__SHIFT 3
> +static inline uint32_t DPU_S_POINTER_POINTER_PP_MODE(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_POINTER_PP_MODE__SHIFT) & DPU_S_POINTER_POINTER_PP_MODE__MASK;
> +}
> +#define DPU_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
> +#define DPU_S_POINTER_EXECUTER_PP_EN__SHIFT 2
> +static inline uint32_t DPU_S_POINTER_EXECUTER_PP_EN(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_EXECUTER_PP_EN__SHIFT) & DPU_S_POINTER_EXECUTER_PP_EN__MASK;
> +}
> +#define DPU_S_POINTER_POINTER_PP_EN__MASK 0x00000002
> +#define DPU_S_POINTER_POINTER_PP_EN__SHIFT 1
> +static inline uint32_t DPU_S_POINTER_POINTER_PP_EN(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_POINTER_PP_EN__SHIFT) & DPU_S_POINTER_POINTER_PP_EN__MASK;
> +}
> +#define DPU_S_POINTER_POINTER__MASK 0x00000001
> +#define DPU_S_POINTER_POINTER__SHIFT 0
> +static inline uint32_t DPU_S_POINTER_POINTER(uint32_t val)
> +{
> + return ((val) << DPU_S_POINTER_POINTER__SHIFT) & DPU_S_POINTER_POINTER__MASK;
> +}
> +
> +#define REG_DPU_OPERATION_ENABLE 0x00004008
> +#define DPU_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
> +#define DPU_OPERATION_ENABLE_RESERVED_0__SHIFT 1
> +static inline uint32_t DPU_OPERATION_ENABLE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_OPERATION_ENABLE_RESERVED_0__SHIFT) & DPU_OPERATION_ENABLE_RESERVED_0__MASK;
> +}
> +#define DPU_OPERATION_ENABLE_OP_EN__MASK 0x00000001
> +#define DPU_OPERATION_ENABLE_OP_EN__SHIFT 0
> +static inline uint32_t DPU_OPERATION_ENABLE_OP_EN(uint32_t val)
> +{
> + return ((val) << DPU_OPERATION_ENABLE_OP_EN__SHIFT) & DPU_OPERATION_ENABLE_OP_EN__MASK;
> +}
> +
> +#define REG_DPU_FEATURE_MODE_CFG 0x0000400c
> +#define DPU_FEATURE_MODE_CFG_COMB_USE__MASK 0x80000000
> +#define DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT 31
> +static inline uint32_t DPU_FEATURE_MODE_CFG_COMB_USE(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_COMB_USE__SHIFT) & DPU_FEATURE_MODE_CFG_COMB_USE__MASK;
> +}
> +#define DPU_FEATURE_MODE_CFG_TP_EN__MASK 0x40000000
> +#define DPU_FEATURE_MODE_CFG_TP_EN__SHIFT 30
> +static inline uint32_t DPU_FEATURE_MODE_CFG_TP_EN(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_TP_EN__SHIFT) & DPU_FEATURE_MODE_CFG_TP_EN__MASK;
> +}
> +#define DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK 0x3c000000
> +#define DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT 26
> +static inline uint32_t DPU_FEATURE_MODE_CFG_RGP_TYPE(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_RGP_TYPE__SHIFT) & DPU_FEATURE_MODE_CFG_RGP_TYPE__MASK;
> +}
> +#define DPU_FEATURE_MODE_CFG_NONALIGN__MASK 0x02000000
> +#define DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT 25
> +static inline uint32_t DPU_FEATURE_MODE_CFG_NONALIGN(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_NONALIGN__SHIFT) & DPU_FEATURE_MODE_CFG_NONALIGN__MASK;
> +}
> +#define DPU_FEATURE_MODE_CFG_SURF_LEN__MASK 0x01fffe00
> +#define DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT 9
> +static inline uint32_t DPU_FEATURE_MODE_CFG_SURF_LEN(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_SURF_LEN__SHIFT) & DPU_FEATURE_MODE_CFG_SURF_LEN__MASK;
> +}
> +#define DPU_FEATURE_MODE_CFG_BURST_LEN__MASK 0x000001e0
> +#define DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT 5
> +static inline uint32_t DPU_FEATURE_MODE_CFG_BURST_LEN(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_BURST_LEN__SHIFT) & DPU_FEATURE_MODE_CFG_BURST_LEN__MASK;
> +}
> +#define DPU_FEATURE_MODE_CFG_CONV_MODE__MASK 0x00000018
> +#define DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT 3
> +static inline uint32_t DPU_FEATURE_MODE_CFG_CONV_MODE(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_CONV_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_CONV_MODE__MASK;
> +}
> +#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK 0x00000006
> +#define DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT 1
> +static inline uint32_t DPU_FEATURE_MODE_CFG_OUTPUT_MODE(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_OUTPUT_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_OUTPUT_MODE__MASK;
> +}
> +#define DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK 0x00000001
> +#define DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT 0
> +static inline uint32_t DPU_FEATURE_MODE_CFG_FLYING_MODE(uint32_t val)
> +{
> + return ((val) << DPU_FEATURE_MODE_CFG_FLYING_MODE__SHIFT) & DPU_FEATURE_MODE_CFG_FLYING_MODE__MASK;
> +}
> +
> +#define REG_DPU_DATA_FORMAT 0x00004010
> +#define DPU_DATA_FORMAT_OUT_PRECISION__MASK 0xe0000000
> +#define DPU_DATA_FORMAT_OUT_PRECISION__SHIFT 29
> +static inline uint32_t DPU_DATA_FORMAT_OUT_PRECISION(uint32_t val)
> +{
> + return ((val) << DPU_DATA_FORMAT_OUT_PRECISION__SHIFT) & DPU_DATA_FORMAT_OUT_PRECISION__MASK;
> +}
> +#define DPU_DATA_FORMAT_IN_PRECISION__MASK 0x1c000000
> +#define DPU_DATA_FORMAT_IN_PRECISION__SHIFT 26
> +static inline uint32_t DPU_DATA_FORMAT_IN_PRECISION(uint32_t val)
> +{
> + return ((val) << DPU_DATA_FORMAT_IN_PRECISION__SHIFT) & DPU_DATA_FORMAT_IN_PRECISION__MASK;
> +}
> +#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK 0x03ff0000
> +#define DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT 16
> +static inline uint32_t DPU_DATA_FORMAT_EW_TRUNCATE_NEG(uint32_t val)
> +{
> + return ((val) << DPU_DATA_FORMAT_EW_TRUNCATE_NEG__SHIFT) & DPU_DATA_FORMAT_EW_TRUNCATE_NEG__MASK;
> +}
> +#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK 0x0000fc00
> +#define DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT 10
> +static inline uint32_t DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG(uint32_t val)
> +{
> + return ((val) << DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__SHIFT) & DPU_DATA_FORMAT_BN_MUL_SHIFT_VALUE_NEG__MASK;
> +}
> +#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK 0x000003f0
> +#define DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT 4
> +static inline uint32_t DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG(uint32_t val)
> +{
> + return ((val) << DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__SHIFT) & DPU_DATA_FORMAT_BS_MUL_SHIFT_VALUE_NEG__MASK;
> +}
> +#define DPU_DATA_FORMAT_MC_SURF_OUT__MASK 0x00000008
> +#define DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT 3
> +static inline uint32_t DPU_DATA_FORMAT_MC_SURF_OUT(uint32_t val)
> +{
> + return ((val) << DPU_DATA_FORMAT_MC_SURF_OUT__SHIFT) & DPU_DATA_FORMAT_MC_SURF_OUT__MASK;
> +}
> +#define DPU_DATA_FORMAT_PROC_PRECISION__MASK 0x00000007
> +#define DPU_DATA_FORMAT_PROC_PRECISION__SHIFT 0
> +static inline uint32_t DPU_DATA_FORMAT_PROC_PRECISION(uint32_t val)
> +{
> + return ((val) << DPU_DATA_FORMAT_PROC_PRECISION__SHIFT) & DPU_DATA_FORMAT_PROC_PRECISION__MASK;
> +}
> +
> +#define REG_DPU_OFFSET_PEND 0x00004014
> +#define DPU_OFFSET_PEND_RESERVED_0__MASK 0xffff0000
> +#define DPU_OFFSET_PEND_RESERVED_0__SHIFT 16
> +static inline uint32_t DPU_OFFSET_PEND_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_OFFSET_PEND_RESERVED_0__SHIFT) & DPU_OFFSET_PEND_RESERVED_0__MASK;
> +}
> +#define DPU_OFFSET_PEND_OFFSET_PEND__MASK 0x0000ffff
> +#define DPU_OFFSET_PEND_OFFSET_PEND__SHIFT 0
> +static inline uint32_t DPU_OFFSET_PEND_OFFSET_PEND(uint32_t val)
> +{
> + return ((val) << DPU_OFFSET_PEND_OFFSET_PEND__SHIFT) & DPU_OFFSET_PEND_OFFSET_PEND__MASK;
> +}
> +
> +#define REG_DPU_DST_BASE_ADDR 0x00004020
> +#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK 0xffffffff
> +#define DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT 0
> +static inline uint32_t DPU_DST_BASE_ADDR_DST_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT) & DPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK;
> +}
> +
> +#define REG_DPU_DST_SURF_STRIDE 0x00004024
> +#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK 0xfffffff0
> +#define DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT 4
> +static inline uint32_t DPU_DST_SURF_STRIDE_DST_SURF_STRIDE(uint32_t val)
> +{
> + return ((val) << DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT) & DPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK;
> +}
> +#define DPU_DST_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
> +#define DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT 0
> +static inline uint32_t DPU_DST_SURF_STRIDE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_DST_SURF_STRIDE_RESERVED_0__SHIFT) & DPU_DST_SURF_STRIDE_RESERVED_0__MASK;
> +}
> +
> +#define REG_DPU_DATA_CUBE_WIDTH 0x00004030
> +#define DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK 0xffffe000
> +#define DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT 13
> +static inline uint32_t DPU_DATA_CUBE_WIDTH_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_WIDTH_RESERVED_0__SHIFT) & DPU_DATA_CUBE_WIDTH_RESERVED_0__MASK;
> +}
> +#define DPU_DATA_CUBE_WIDTH_WIDTH__MASK 0x00001fff
> +#define DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT 0
> +static inline uint32_t DPU_DATA_CUBE_WIDTH_WIDTH(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_WIDTH_WIDTH__SHIFT) & DPU_DATA_CUBE_WIDTH_WIDTH__MASK;
> +}
> +
> +#define REG_DPU_DATA_CUBE_HEIGHT 0x00004034
> +#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK 0xfe000000
> +#define DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT 25
> +static inline uint32_t DPU_DATA_CUBE_HEIGHT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT) & DPU_DATA_CUBE_HEIGHT_RESERVED_0__MASK;
> +}
> +#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK 0x01c00000
> +#define DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT 22
> +static inline uint32_t DPU_DATA_CUBE_HEIGHT_MINMAX_CTL(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__SHIFT) & DPU_DATA_CUBE_HEIGHT_MINMAX_CTL__MASK;
> +}
> +#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK 0x003fe000
> +#define DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT 13
> +static inline uint32_t DPU_DATA_CUBE_HEIGHT_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT) & DPU_DATA_CUBE_HEIGHT_RESERVED_1__MASK;
> +}
> +#define DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK 0x00001fff
> +#define DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT 0
> +static inline uint32_t DPU_DATA_CUBE_HEIGHT_HEIGHT(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_HEIGHT_HEIGHT__SHIFT) & DPU_DATA_CUBE_HEIGHT_HEIGHT__MASK;
> +}
> +
> +#define REG_DPU_DATA_CUBE_NOTCH_ADDR 0x00004038
> +#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK 0xe0000000
> +#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT 29
> +static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_0__MASK;
> +}
> +#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK 0x1fff0000
> +#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT 16
> +static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_1__MASK;
> +}
> +#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK 0x0000e000
> +#define DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT 13
> +static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_RESERVED_1__MASK;
> +}
> +#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK 0x00001fff
> +#define DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT 0
> +static inline uint32_t DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__SHIFT) & DPU_DATA_CUBE_NOTCH_ADDR_NOTCH_ADDR_0__MASK;
> +}
> +
> +#define REG_DPU_DATA_CUBE_CHANNEL 0x0000403c
> +#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK 0xe0000000
> +#define DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT 29
> +static inline uint32_t DPU_DATA_CUBE_CHANNEL_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT) & DPU_DATA_CUBE_CHANNEL_RESERVED_0__MASK;
> +}
> +#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK 0x1fff0000
> +#define DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT 16
> +static inline uint32_t DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__SHIFT) & DPU_DATA_CUBE_CHANNEL_ORIG_CHANNEL__MASK;
> +}
> +#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK 0x0000e000
> +#define DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT 13
> +static inline uint32_t DPU_DATA_CUBE_CHANNEL_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_CHANNEL_RESERVED_1__SHIFT) & DPU_DATA_CUBE_CHANNEL_RESERVED_1__MASK;
> +}
> +#define DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK 0x00001fff
> +#define DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT 0
> +static inline uint32_t DPU_DATA_CUBE_CHANNEL_CHANNEL(uint32_t val)
> +{
> + return ((val) << DPU_DATA_CUBE_CHANNEL_CHANNEL__SHIFT) & DPU_DATA_CUBE_CHANNEL_CHANNEL__MASK;
> +}
> +
> +#define REG_DPU_BS_CFG 0x00004040
> +#define DPU_BS_CFG_RESERVED_0__MASK 0xfff00000
> +#define DPU_BS_CFG_RESERVED_0__SHIFT 20
> +static inline uint32_t DPU_BS_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_RESERVED_0__SHIFT) & DPU_BS_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_BS_CFG_BS_ALU_ALGO__MASK 0x000f0000
> +#define DPU_BS_CFG_BS_ALU_ALGO__SHIFT 16
> +static inline uint32_t DPU_BS_CFG_BS_ALU_ALGO(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_BS_ALU_ALGO__SHIFT) & DPU_BS_CFG_BS_ALU_ALGO__MASK;
> +}
> +#define DPU_BS_CFG_RESERVED_1__MASK 0x0000fe00
> +#define DPU_BS_CFG_RESERVED_1__SHIFT 9
> +static inline uint32_t DPU_BS_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_RESERVED_1__SHIFT) & DPU_BS_CFG_RESERVED_1__MASK;
> +}
> +#define DPU_BS_CFG_BS_ALU_SRC__MASK 0x00000100
> +#define DPU_BS_CFG_BS_ALU_SRC__SHIFT 8
> +static inline uint32_t DPU_BS_CFG_BS_ALU_SRC(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_BS_ALU_SRC__SHIFT) & DPU_BS_CFG_BS_ALU_SRC__MASK;
> +}
> +#define DPU_BS_CFG_BS_RELUX_EN__MASK 0x00000080
> +#define DPU_BS_CFG_BS_RELUX_EN__SHIFT 7
> +static inline uint32_t DPU_BS_CFG_BS_RELUX_EN(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_BS_RELUX_EN__SHIFT) & DPU_BS_CFG_BS_RELUX_EN__MASK;
> +}
> +#define DPU_BS_CFG_BS_RELU_BYPASS__MASK 0x00000040
> +#define DPU_BS_CFG_BS_RELU_BYPASS__SHIFT 6
> +static inline uint32_t DPU_BS_CFG_BS_RELU_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_BS_RELU_BYPASS__SHIFT) & DPU_BS_CFG_BS_RELU_BYPASS__MASK;
> +}
> +#define DPU_BS_CFG_BS_MUL_PRELU__MASK 0x00000020
> +#define DPU_BS_CFG_BS_MUL_PRELU__SHIFT 5
> +static inline uint32_t DPU_BS_CFG_BS_MUL_PRELU(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_BS_MUL_PRELU__SHIFT) & DPU_BS_CFG_BS_MUL_PRELU__MASK;
> +}
> +#define DPU_BS_CFG_BS_MUL_BYPASS__MASK 0x00000010
> +#define DPU_BS_CFG_BS_MUL_BYPASS__SHIFT 4
> +static inline uint32_t DPU_BS_CFG_BS_MUL_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_BS_MUL_BYPASS__SHIFT) & DPU_BS_CFG_BS_MUL_BYPASS__MASK;
> +}
> +#define DPU_BS_CFG_RESERVED_2__MASK 0x0000000c
> +#define DPU_BS_CFG_RESERVED_2__SHIFT 2
> +static inline uint32_t DPU_BS_CFG_RESERVED_2(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_RESERVED_2__SHIFT) & DPU_BS_CFG_RESERVED_2__MASK;
> +}
> +#define DPU_BS_CFG_BS_ALU_BYPASS__MASK 0x00000002
> +#define DPU_BS_CFG_BS_ALU_BYPASS__SHIFT 1
> +static inline uint32_t DPU_BS_CFG_BS_ALU_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_BS_ALU_BYPASS__SHIFT) & DPU_BS_CFG_BS_ALU_BYPASS__MASK;
> +}
> +#define DPU_BS_CFG_BS_BYPASS__MASK 0x00000001
> +#define DPU_BS_CFG_BS_BYPASS__SHIFT 0
> +static inline uint32_t DPU_BS_CFG_BS_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BS_CFG_BS_BYPASS__SHIFT) & DPU_BS_CFG_BS_BYPASS__MASK;
> +}
> +
> +#define REG_DPU_BS_ALU_CFG 0x00004044
> +#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK 0xffffffff
> +#define DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT 0
> +static inline uint32_t DPU_BS_ALU_CFG_BS_ALU_OPERAND(uint32_t val)
> +{
> + return ((val) << DPU_BS_ALU_CFG_BS_ALU_OPERAND__SHIFT) & DPU_BS_ALU_CFG_BS_ALU_OPERAND__MASK;
> +}
> +
> +#define REG_DPU_BS_MUL_CFG 0x00004048
> +#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK 0xffff0000
> +#define DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT 16
> +static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_OPERAND(uint32_t val)
> +{
> + return ((val) << DPU_BS_MUL_CFG_BS_MUL_OPERAND__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_OPERAND__MASK;
> +}
> +#define DPU_BS_MUL_CFG_RESERVED_0__MASK 0x0000c000
> +#define DPU_BS_MUL_CFG_RESERVED_0__SHIFT 14
> +static inline uint32_t DPU_BS_MUL_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_BS_MUL_CFG_RESERVED_0__SHIFT) & DPU_BS_MUL_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK 0x00003f00
> +#define DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT 8
> +static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE(uint32_t val)
> +{
> + return ((val) << DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_SHIFT_VALUE__MASK;
> +}
> +#define DPU_BS_MUL_CFG_RESERVED_1__MASK 0x000000fc
> +#define DPU_BS_MUL_CFG_RESERVED_1__SHIFT 2
> +static inline uint32_t DPU_BS_MUL_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_BS_MUL_CFG_RESERVED_1__SHIFT) & DPU_BS_MUL_CFG_RESERVED_1__MASK;
> +}
> +#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK 0x00000002
> +#define DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT 1
> +static inline uint32_t DPU_BS_MUL_CFG_BS_TRUNCATE_SRC(uint32_t val)
> +{
> + return ((val) << DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__SHIFT) & DPU_BS_MUL_CFG_BS_TRUNCATE_SRC__MASK;
> +}
> +#define DPU_BS_MUL_CFG_BS_MUL_SRC__MASK 0x00000001
> +#define DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT 0
> +static inline uint32_t DPU_BS_MUL_CFG_BS_MUL_SRC(uint32_t val)
> +{
> + return ((val) << DPU_BS_MUL_CFG_BS_MUL_SRC__SHIFT) & DPU_BS_MUL_CFG_BS_MUL_SRC__MASK;
> +}
> +
> +#define REG_DPU_BS_RELUX_CMP_VALUE 0x0000404c
> +#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK 0xffffffff
> +#define DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT 0
> +static inline uint32_t DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT(uint32_t val)
> +{
> + return ((val) << DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__SHIFT) & DPU_BS_RELUX_CMP_VALUE_BS_RELUX_CMP_DAT__MASK;
> +}
> +
> +#define REG_DPU_BS_OW_CFG 0x00004050
> +#define DPU_BS_OW_CFG_RGP_CNTER__MASK 0xf0000000
> +#define DPU_BS_OW_CFG_RGP_CNTER__SHIFT 28
> +static inline uint32_t DPU_BS_OW_CFG_RGP_CNTER(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_CFG_RGP_CNTER__SHIFT) & DPU_BS_OW_CFG_RGP_CNTER__MASK;
> +}
> +#define DPU_BS_OW_CFG_TP_ORG_EN__MASK 0x08000000
> +#define DPU_BS_OW_CFG_TP_ORG_EN__SHIFT 27
> +static inline uint32_t DPU_BS_OW_CFG_TP_ORG_EN(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_CFG_TP_ORG_EN__SHIFT) & DPU_BS_OW_CFG_TP_ORG_EN__MASK;
> +}
> +#define DPU_BS_OW_CFG_RESERVED_0__MASK 0x07fff800
> +#define DPU_BS_OW_CFG_RESERVED_0__SHIFT 11
> +static inline uint32_t DPU_BS_OW_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_CFG_RESERVED_0__SHIFT) & DPU_BS_OW_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_BS_OW_CFG_SIZE_E_2__MASK 0x00000700
> +#define DPU_BS_OW_CFG_SIZE_E_2__SHIFT 8
> +static inline uint32_t DPU_BS_OW_CFG_SIZE_E_2(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_CFG_SIZE_E_2__SHIFT) & DPU_BS_OW_CFG_SIZE_E_2__MASK;
> +}
> +#define DPU_BS_OW_CFG_SIZE_E_1__MASK 0x000000e0
> +#define DPU_BS_OW_CFG_SIZE_E_1__SHIFT 5
> +static inline uint32_t DPU_BS_OW_CFG_SIZE_E_1(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_CFG_SIZE_E_1__SHIFT) & DPU_BS_OW_CFG_SIZE_E_1__MASK;
> +}
> +#define DPU_BS_OW_CFG_SIZE_E_0__MASK 0x0000001c
> +#define DPU_BS_OW_CFG_SIZE_E_0__SHIFT 2
> +static inline uint32_t DPU_BS_OW_CFG_SIZE_E_0(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_CFG_SIZE_E_0__SHIFT) & DPU_BS_OW_CFG_SIZE_E_0__MASK;
> +}
> +#define DPU_BS_OW_CFG_OD_BYPASS__MASK 0x00000002
> +#define DPU_BS_OW_CFG_OD_BYPASS__SHIFT 1
> +static inline uint32_t DPU_BS_OW_CFG_OD_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_CFG_OD_BYPASS__SHIFT) & DPU_BS_OW_CFG_OD_BYPASS__MASK;
> +}
> +#define DPU_BS_OW_CFG_OW_SRC__MASK 0x00000001
> +#define DPU_BS_OW_CFG_OW_SRC__SHIFT 0
> +static inline uint32_t DPU_BS_OW_CFG_OW_SRC(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_CFG_OW_SRC__SHIFT) & DPU_BS_OW_CFG_OW_SRC__MASK;
> +}
> +
> +#define REG_DPU_BS_OW_OP 0x00004054
> +#define DPU_BS_OW_OP_RESERVED_0__MASK 0xffff0000
> +#define DPU_BS_OW_OP_RESERVED_0__SHIFT 16
> +static inline uint32_t DPU_BS_OW_OP_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_OP_RESERVED_0__SHIFT) & DPU_BS_OW_OP_RESERVED_0__MASK;
> +}
> +#define DPU_BS_OW_OP_OW_OP__MASK 0x0000ffff
> +#define DPU_BS_OW_OP_OW_OP__SHIFT 0
> +static inline uint32_t DPU_BS_OW_OP_OW_OP(uint32_t val)
> +{
> + return ((val) << DPU_BS_OW_OP_OW_OP__SHIFT) & DPU_BS_OW_OP_OW_OP__MASK;
> +}
> +
> +#define REG_DPU_WDMA_SIZE_0 0x00004058
> +#define DPU_WDMA_SIZE_0_RESERVED_0__MASK 0xf0000000
> +#define DPU_WDMA_SIZE_0_RESERVED_0__SHIFT 28
> +static inline uint32_t DPU_WDMA_SIZE_0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_0_RESERVED_0__SHIFT) & DPU_WDMA_SIZE_0_RESERVED_0__MASK;
> +}
> +#define DPU_WDMA_SIZE_0_TP_PRECISION__MASK 0x08000000
> +#define DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT 27
> +static inline uint32_t DPU_WDMA_SIZE_0_TP_PRECISION(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_0_TP_PRECISION__SHIFT) & DPU_WDMA_SIZE_0_TP_PRECISION__MASK;
> +}
> +#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK 0x07ff0000
> +#define DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT 16
> +static inline uint32_t DPU_WDMA_SIZE_0_SIZE_C_WDMA(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_0_SIZE_C_WDMA__SHIFT) & DPU_WDMA_SIZE_0_SIZE_C_WDMA__MASK;
> +}
> +#define DPU_WDMA_SIZE_0_RESERVED_1__MASK 0x0000e000
> +#define DPU_WDMA_SIZE_0_RESERVED_1__SHIFT 13
> +static inline uint32_t DPU_WDMA_SIZE_0_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_0_RESERVED_1__SHIFT) & DPU_WDMA_SIZE_0_RESERVED_1__MASK;
> +}
> +#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK 0x00001fff
> +#define DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT 0
> +static inline uint32_t DPU_WDMA_SIZE_0_CHANNEL_WDMA(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_0_CHANNEL_WDMA__SHIFT) & DPU_WDMA_SIZE_0_CHANNEL_WDMA__MASK;
> +}
> +
> +#define REG_DPU_WDMA_SIZE_1 0x0000405c
> +#define DPU_WDMA_SIZE_1_RESERVED_0__MASK 0xe0000000
> +#define DPU_WDMA_SIZE_1_RESERVED_0__SHIFT 29
> +static inline uint32_t DPU_WDMA_SIZE_1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_1_RESERVED_0__SHIFT) & DPU_WDMA_SIZE_1_RESERVED_0__MASK;
> +}
> +#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK 0x1fff0000
> +#define DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT 16
> +static inline uint32_t DPU_WDMA_SIZE_1_HEIGHT_WDMA(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_1_HEIGHT_WDMA__SHIFT) & DPU_WDMA_SIZE_1_HEIGHT_WDMA__MASK;
> +}
> +#define DPU_WDMA_SIZE_1_RESERVED_1__MASK 0x0000e000
> +#define DPU_WDMA_SIZE_1_RESERVED_1__SHIFT 13
> +static inline uint32_t DPU_WDMA_SIZE_1_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_1_RESERVED_1__SHIFT) & DPU_WDMA_SIZE_1_RESERVED_1__MASK;
> +}
> +#define DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK 0x00001fff
> +#define DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT 0
> +static inline uint32_t DPU_WDMA_SIZE_1_WIDTH_WDMA(uint32_t val)
> +{
> + return ((val) << DPU_WDMA_SIZE_1_WIDTH_WDMA__SHIFT) & DPU_WDMA_SIZE_1_WIDTH_WDMA__MASK;
> +}
> +
> +#define REG_DPU_BN_CFG 0x00004060
> +#define DPU_BN_CFG_RESERVED_0__MASK 0xfff00000
> +#define DPU_BN_CFG_RESERVED_0__SHIFT 20
> +static inline uint32_t DPU_BN_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_RESERVED_0__SHIFT) & DPU_BN_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_BN_CFG_BN_ALU_ALGO__MASK 0x000f0000
> +#define DPU_BN_CFG_BN_ALU_ALGO__SHIFT 16
> +static inline uint32_t DPU_BN_CFG_BN_ALU_ALGO(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_BN_ALU_ALGO__SHIFT) & DPU_BN_CFG_BN_ALU_ALGO__MASK;
> +}
> +#define DPU_BN_CFG_RESERVED_1__MASK 0x0000fe00
> +#define DPU_BN_CFG_RESERVED_1__SHIFT 9
> +static inline uint32_t DPU_BN_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_RESERVED_1__SHIFT) & DPU_BN_CFG_RESERVED_1__MASK;
> +}
> +#define DPU_BN_CFG_BN_ALU_SRC__MASK 0x00000100
> +#define DPU_BN_CFG_BN_ALU_SRC__SHIFT 8
> +static inline uint32_t DPU_BN_CFG_BN_ALU_SRC(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_BN_ALU_SRC__SHIFT) & DPU_BN_CFG_BN_ALU_SRC__MASK;
> +}
> +#define DPU_BN_CFG_BN_RELUX_EN__MASK 0x00000080
> +#define DPU_BN_CFG_BN_RELUX_EN__SHIFT 7
> +static inline uint32_t DPU_BN_CFG_BN_RELUX_EN(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_BN_RELUX_EN__SHIFT) & DPU_BN_CFG_BN_RELUX_EN__MASK;
> +}
> +#define DPU_BN_CFG_BN_RELU_BYPASS__MASK 0x00000040
> +#define DPU_BN_CFG_BN_RELU_BYPASS__SHIFT 6
> +static inline uint32_t DPU_BN_CFG_BN_RELU_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_BN_RELU_BYPASS__SHIFT) & DPU_BN_CFG_BN_RELU_BYPASS__MASK;
> +}
> +#define DPU_BN_CFG_BN_MUL_PRELU__MASK 0x00000020
> +#define DPU_BN_CFG_BN_MUL_PRELU__SHIFT 5
> +static inline uint32_t DPU_BN_CFG_BN_MUL_PRELU(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_BN_MUL_PRELU__SHIFT) & DPU_BN_CFG_BN_MUL_PRELU__MASK;
> +}
> +#define DPU_BN_CFG_BN_MUL_BYPASS__MASK 0x00000010
> +#define DPU_BN_CFG_BN_MUL_BYPASS__SHIFT 4
> +static inline uint32_t DPU_BN_CFG_BN_MUL_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_BN_MUL_BYPASS__SHIFT) & DPU_BN_CFG_BN_MUL_BYPASS__MASK;
> +}
> +#define DPU_BN_CFG_RESERVED_2__MASK 0x0000000c
> +#define DPU_BN_CFG_RESERVED_2__SHIFT 2
> +static inline uint32_t DPU_BN_CFG_RESERVED_2(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_RESERVED_2__SHIFT) & DPU_BN_CFG_RESERVED_2__MASK;
> +}
> +#define DPU_BN_CFG_BN_ALU_BYPASS__MASK 0x00000002
> +#define DPU_BN_CFG_BN_ALU_BYPASS__SHIFT 1
> +static inline uint32_t DPU_BN_CFG_BN_ALU_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_BN_ALU_BYPASS__SHIFT) & DPU_BN_CFG_BN_ALU_BYPASS__MASK;
> +}
> +#define DPU_BN_CFG_BN_BYPASS__MASK 0x00000001
> +#define DPU_BN_CFG_BN_BYPASS__SHIFT 0
> +static inline uint32_t DPU_BN_CFG_BN_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_BN_CFG_BN_BYPASS__SHIFT) & DPU_BN_CFG_BN_BYPASS__MASK;
> +}
> +
> +#define REG_DPU_BN_ALU_CFG 0x00004064
> +#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK 0xffffffff
> +#define DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT 0
> +static inline uint32_t DPU_BN_ALU_CFG_BN_ALU_OPERAND(uint32_t val)
> +{
> + return ((val) << DPU_BN_ALU_CFG_BN_ALU_OPERAND__SHIFT) & DPU_BN_ALU_CFG_BN_ALU_OPERAND__MASK;
> +}
> +
> +#define REG_DPU_BN_MUL_CFG 0x00004068
> +#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK 0xffff0000
> +#define DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT 16
> +static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_OPERAND(uint32_t val)
> +{
> + return ((val) << DPU_BN_MUL_CFG_BN_MUL_OPERAND__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_OPERAND__MASK;
> +}
> +#define DPU_BN_MUL_CFG_RESERVED_0__MASK 0x0000c000
> +#define DPU_BN_MUL_CFG_RESERVED_0__SHIFT 14
> +static inline uint32_t DPU_BN_MUL_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_BN_MUL_CFG_RESERVED_0__SHIFT) & DPU_BN_MUL_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK 0x00003f00
> +#define DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT 8
> +static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE(uint32_t val)
> +{
> + return ((val) << DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_SHIFT_VALUE__MASK;
> +}
> +#define DPU_BN_MUL_CFG_RESERVED_1__MASK 0x000000fc
> +#define DPU_BN_MUL_CFG_RESERVED_1__SHIFT 2
> +static inline uint32_t DPU_BN_MUL_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_BN_MUL_CFG_RESERVED_1__SHIFT) & DPU_BN_MUL_CFG_RESERVED_1__MASK;
> +}
> +#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK 0x00000002
> +#define DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT 1
> +static inline uint32_t DPU_BN_MUL_CFG_BN_TRUNCATE_SRC(uint32_t val)
> +{
> + return ((val) << DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__SHIFT) & DPU_BN_MUL_CFG_BN_TRUNCATE_SRC__MASK;
> +}
> +#define DPU_BN_MUL_CFG_BN_MUL_SRC__MASK 0x00000001
> +#define DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT 0
> +static inline uint32_t DPU_BN_MUL_CFG_BN_MUL_SRC(uint32_t val)
> +{
> + return ((val) << DPU_BN_MUL_CFG_BN_MUL_SRC__SHIFT) & DPU_BN_MUL_CFG_BN_MUL_SRC__MASK;
> +}
> +
> +#define REG_DPU_BN_RELUX_CMP_VALUE 0x0000406c
> +#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK 0xffffffff
> +#define DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT 0
> +static inline uint32_t DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT(uint32_t val)
> +{
> + return ((val) << DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__SHIFT) & DPU_BN_RELUX_CMP_VALUE_BN_RELUX_CMP_DAT__MASK;
> +}
> +
> +#define REG_DPU_EW_CFG 0x00004070
> +#define DPU_EW_CFG_EW_CVT_TYPE__MASK 0x80000000
> +#define DPU_EW_CFG_EW_CVT_TYPE__SHIFT 31
> +static inline uint32_t DPU_EW_CFG_EW_CVT_TYPE(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_CVT_TYPE__SHIFT) & DPU_EW_CFG_EW_CVT_TYPE__MASK;
> +}
> +#define DPU_EW_CFG_EW_CVT_ROUND__MASK 0x40000000
> +#define DPU_EW_CFG_EW_CVT_ROUND__SHIFT 30
> +static inline uint32_t DPU_EW_CFG_EW_CVT_ROUND(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_CVT_ROUND__SHIFT) & DPU_EW_CFG_EW_CVT_ROUND__MASK;
> +}
> +#define DPU_EW_CFG_EW_DATA_MODE__MASK 0x30000000
> +#define DPU_EW_CFG_EW_DATA_MODE__SHIFT 28
> +static inline uint32_t DPU_EW_CFG_EW_DATA_MODE(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_DATA_MODE__SHIFT) & DPU_EW_CFG_EW_DATA_MODE__MASK;
> +}
> +#define DPU_EW_CFG_RESERVED_0__MASK 0x0f000000
> +#define DPU_EW_CFG_RESERVED_0__SHIFT 24
> +static inline uint32_t DPU_EW_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_RESERVED_0__SHIFT) & DPU_EW_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_EW_CFG_EDATA_SIZE__MASK 0x00c00000
> +#define DPU_EW_CFG_EDATA_SIZE__SHIFT 22
> +static inline uint32_t DPU_EW_CFG_EDATA_SIZE(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EDATA_SIZE__SHIFT) & DPU_EW_CFG_EDATA_SIZE__MASK;
> +}
> +#define DPU_EW_CFG_EW_EQUAL_EN__MASK 0x00200000
> +#define DPU_EW_CFG_EW_EQUAL_EN__SHIFT 21
> +static inline uint32_t DPU_EW_CFG_EW_EQUAL_EN(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_EQUAL_EN__SHIFT) & DPU_EW_CFG_EW_EQUAL_EN__MASK;
> +}
> +#define DPU_EW_CFG_EW_BINARY_EN__MASK 0x00100000
> +#define DPU_EW_CFG_EW_BINARY_EN__SHIFT 20
> +static inline uint32_t DPU_EW_CFG_EW_BINARY_EN(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_BINARY_EN__SHIFT) & DPU_EW_CFG_EW_BINARY_EN__MASK;
> +}
> +#define DPU_EW_CFG_EW_ALU_ALGO__MASK 0x000f0000
> +#define DPU_EW_CFG_EW_ALU_ALGO__SHIFT 16
> +static inline uint32_t DPU_EW_CFG_EW_ALU_ALGO(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_ALU_ALGO__SHIFT) & DPU_EW_CFG_EW_ALU_ALGO__MASK;
> +}
> +#define DPU_EW_CFG_RESERVED_1__MASK 0x0000f800
> +#define DPU_EW_CFG_RESERVED_1__SHIFT 11
> +static inline uint32_t DPU_EW_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_RESERVED_1__SHIFT) & DPU_EW_CFG_RESERVED_1__MASK;
> +}
> +#define DPU_EW_CFG_EW_RELUX_EN__MASK 0x00000400
> +#define DPU_EW_CFG_EW_RELUX_EN__SHIFT 10
> +static inline uint32_t DPU_EW_CFG_EW_RELUX_EN(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_RELUX_EN__SHIFT) & DPU_EW_CFG_EW_RELUX_EN__MASK;
> +}
> +#define DPU_EW_CFG_EW_RELU_BYPASS__MASK 0x00000200
> +#define DPU_EW_CFG_EW_RELU_BYPASS__SHIFT 9
> +static inline uint32_t DPU_EW_CFG_EW_RELU_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_RELU_BYPASS__SHIFT) & DPU_EW_CFG_EW_RELU_BYPASS__MASK;
> +}
> +#define DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK 0x00000100
> +#define DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT 8
> +static inline uint32_t DPU_EW_CFG_EW_OP_CVT_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_OP_CVT_BYPASS__SHIFT) & DPU_EW_CFG_EW_OP_CVT_BYPASS__MASK;
> +}
> +#define DPU_EW_CFG_EW_LUT_BYPASS__MASK 0x00000080
> +#define DPU_EW_CFG_EW_LUT_BYPASS__SHIFT 7
> +static inline uint32_t DPU_EW_CFG_EW_LUT_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_LUT_BYPASS__SHIFT) & DPU_EW_CFG_EW_LUT_BYPASS__MASK;
> +}
> +#define DPU_EW_CFG_EW_OP_SRC__MASK 0x00000040
> +#define DPU_EW_CFG_EW_OP_SRC__SHIFT 6
> +static inline uint32_t DPU_EW_CFG_EW_OP_SRC(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_OP_SRC__SHIFT) & DPU_EW_CFG_EW_OP_SRC__MASK;
> +}
> +#define DPU_EW_CFG_EW_MUL_PRELU__MASK 0x00000020
> +#define DPU_EW_CFG_EW_MUL_PRELU__SHIFT 5
> +static inline uint32_t DPU_EW_CFG_EW_MUL_PRELU(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_MUL_PRELU__SHIFT) & DPU_EW_CFG_EW_MUL_PRELU__MASK;
> +}
> +#define DPU_EW_CFG_RESERVED_2__MASK 0x00000018
> +#define DPU_EW_CFG_RESERVED_2__SHIFT 3
> +static inline uint32_t DPU_EW_CFG_RESERVED_2(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_RESERVED_2__SHIFT) & DPU_EW_CFG_RESERVED_2__MASK;
> +}
> +#define DPU_EW_CFG_EW_OP_TYPE__MASK 0x00000004
> +#define DPU_EW_CFG_EW_OP_TYPE__SHIFT 2
> +static inline uint32_t DPU_EW_CFG_EW_OP_TYPE(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_OP_TYPE__SHIFT) & DPU_EW_CFG_EW_OP_TYPE__MASK;
> +}
> +#define DPU_EW_CFG_EW_OP_BYPASS__MASK 0x00000002
> +#define DPU_EW_CFG_EW_OP_BYPASS__SHIFT 1
> +static inline uint32_t DPU_EW_CFG_EW_OP_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_OP_BYPASS__SHIFT) & DPU_EW_CFG_EW_OP_BYPASS__MASK;
> +}
> +#define DPU_EW_CFG_EW_BYPASS__MASK 0x00000001
> +#define DPU_EW_CFG_EW_BYPASS__SHIFT 0
> +static inline uint32_t DPU_EW_CFG_EW_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_EW_CFG_EW_BYPASS__SHIFT) & DPU_EW_CFG_EW_BYPASS__MASK;
> +}
> +
> +#define REG_DPU_EW_CVT_OFFSET_VALUE 0x00004074
> +#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK 0xffffffff
> +#define DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT 0
> +static inline uint32_t DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET(uint32_t val)
> +{
> + return ((val) << DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__SHIFT) & DPU_EW_CVT_OFFSET_VALUE_EW_OP_CVT_OFFSET__MASK;
> +}
> +
> +#define REG_DPU_EW_CVT_SCALE_VALUE 0x00004078
> +#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK 0xffc00000
> +#define DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT 22
> +static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE(uint32_t val)
> +{
> + return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_TRUNCATE__MASK;
> +}
> +#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK 0x003f0000
> +#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT 16
> +static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT(uint32_t val)
> +{
> + return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SHIFT__MASK;
> +}
> +#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK 0x0000ffff
> +#define DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT 0
> +static inline uint32_t DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE(uint32_t val)
> +{
> + return ((val) << DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__SHIFT) & DPU_EW_CVT_SCALE_VALUE_EW_OP_CVT_SCALE__MASK;
> +}
> +
> +#define REG_DPU_EW_RELUX_CMP_VALUE 0x0000407c
> +#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK 0xffffffff
> +#define DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT 0
> +static inline uint32_t DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT(uint32_t val)
> +{
> + return ((val) << DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__SHIFT) & DPU_EW_RELUX_CMP_VALUE_EW_RELUX_CMP_DAT__MASK;
> +}
> +
> +#define REG_DPU_OUT_CVT_OFFSET 0x00004080
> +#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK 0xffffffff
> +#define DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT 0
> +static inline uint32_t DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__SHIFT) & DPU_OUT_CVT_OFFSET_OUT_CVT_OFFSET__MASK;
> +}
> +
> +#define REG_DPU_OUT_CVT_SCALE 0x00004084
> +#define DPU_OUT_CVT_SCALE_RESERVED_0__MASK 0xfffe0000
> +#define DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT 17
> +static inline uint32_t DPU_OUT_CVT_SCALE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_SCALE_RESERVED_0__SHIFT) & DPU_OUT_CVT_SCALE_RESERVED_0__MASK;
> +}
> +#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK 0x00010000
> +#define DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT 16
> +static inline uint32_t DPU_OUT_CVT_SCALE_FP32TOFP16_EN(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_SCALE_FP32TOFP16_EN__SHIFT) & DPU_OUT_CVT_SCALE_FP32TOFP16_EN__MASK;
> +}
> +#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK 0x0000ffff
> +#define DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT 0
> +static inline uint32_t DPU_OUT_CVT_SCALE_OUT_CVT_SCALE(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__SHIFT) & DPU_OUT_CVT_SCALE_OUT_CVT_SCALE__MASK;
> +}
> +
> +#define REG_DPU_OUT_CVT_SHIFT 0x00004088
> +#define DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK 0x80000000
> +#define DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT 31
> +static inline uint32_t DPU_OUT_CVT_SHIFT_CVT_TYPE(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_SHIFT_CVT_TYPE__SHIFT) & DPU_OUT_CVT_SHIFT_CVT_TYPE__MASK;
> +}
> +#define DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK 0x40000000
> +#define DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT 30
> +static inline uint32_t DPU_OUT_CVT_SHIFT_CVT_ROUND(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_SHIFT_CVT_ROUND__SHIFT) & DPU_OUT_CVT_SHIFT_CVT_ROUND__MASK;
> +}
> +#define DPU_OUT_CVT_SHIFT_RESERVED_0__MASK 0x3ff00000
> +#define DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT 20
> +static inline uint32_t DPU_OUT_CVT_SHIFT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_SHIFT_RESERVED_0__SHIFT) & DPU_OUT_CVT_SHIFT_RESERVED_0__MASK;
> +}
> +#define DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK 0x000ff000
> +#define DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT 12
> +static inline uint32_t DPU_OUT_CVT_SHIFT_MINUS_EXP(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_SHIFT_MINUS_EXP__SHIFT) & DPU_OUT_CVT_SHIFT_MINUS_EXP__MASK;
> +}
> +#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK 0x00000fff
> +#define DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT 0
> +static inline uint32_t DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT(uint32_t val)
> +{
> + return ((val) << DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__SHIFT) & DPU_OUT_CVT_SHIFT_OUT_CVT_SHIFT__MASK;
> +}
> +
> +#define REG_DPU_EW_OP_VALUE_0 0x00004090
> +#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK 0xffffffff
> +#define DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT 0
> +static inline uint32_t DPU_EW_OP_VALUE_0_EW_OPERAND_0(uint32_t val)
> +{
> + return ((val) << DPU_EW_OP_VALUE_0_EW_OPERAND_0__SHIFT) & DPU_EW_OP_VALUE_0_EW_OPERAND_0__MASK;
> +}
> +
> +#define REG_DPU_EW_OP_VALUE_1 0x00004094
> +#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK 0xffffffff
> +#define DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT 0
> +static inline uint32_t DPU_EW_OP_VALUE_1_EW_OPERAND_1(uint32_t val)
> +{
> + return ((val) << DPU_EW_OP_VALUE_1_EW_OPERAND_1__SHIFT) & DPU_EW_OP_VALUE_1_EW_OPERAND_1__MASK;
> +}
> +
> +#define REG_DPU_EW_OP_VALUE_2 0x00004098
> +#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK 0xffffffff
> +#define DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT 0
> +static inline uint32_t DPU_EW_OP_VALUE_2_EW_OPERAND_2(uint32_t val)
> +{
> + return ((val) << DPU_EW_OP_VALUE_2_EW_OPERAND_2__SHIFT) & DPU_EW_OP_VALUE_2_EW_OPERAND_2__MASK;
> +}
> +
> +#define REG_DPU_EW_OP_VALUE_3 0x0000409c
> +#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK 0xffffffff
> +#define DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT 0
> +static inline uint32_t DPU_EW_OP_VALUE_3_EW_OPERAND_3(uint32_t val)
> +{
> + return ((val) << DPU_EW_OP_VALUE_3_EW_OPERAND_3__SHIFT) & DPU_EW_OP_VALUE_3_EW_OPERAND_3__MASK;
> +}
> +
> +#define REG_DPU_EW_OP_VALUE_4 0x000040a0
> +#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK 0xffffffff
> +#define DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT 0
> +static inline uint32_t DPU_EW_OP_VALUE_4_EW_OPERAND_4(uint32_t val)
> +{
> + return ((val) << DPU_EW_OP_VALUE_4_EW_OPERAND_4__SHIFT) & DPU_EW_OP_VALUE_4_EW_OPERAND_4__MASK;
> +}
> +
> +#define REG_DPU_EW_OP_VALUE_5 0x000040a4
> +#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK 0xffffffff
> +#define DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT 0
> +static inline uint32_t DPU_EW_OP_VALUE_5_EW_OPERAND_5(uint32_t val)
> +{
> + return ((val) << DPU_EW_OP_VALUE_5_EW_OPERAND_5__SHIFT) & DPU_EW_OP_VALUE_5_EW_OPERAND_5__MASK;
> +}
> +
> +#define REG_DPU_EW_OP_VALUE_6 0x000040a8
> +#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK 0xffffffff
> +#define DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT 0
> +static inline uint32_t DPU_EW_OP_VALUE_6_EW_OPERAND_6(uint32_t val)
> +{
> + return ((val) << DPU_EW_OP_VALUE_6_EW_OPERAND_6__SHIFT) & DPU_EW_OP_VALUE_6_EW_OPERAND_6__MASK;
> +}
> +
> +#define REG_DPU_EW_OP_VALUE_7 0x000040ac
> +#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK 0xffffffff
> +#define DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT 0
> +static inline uint32_t DPU_EW_OP_VALUE_7_EW_OPERAND_7(uint32_t val)
> +{
> + return ((val) << DPU_EW_OP_VALUE_7_EW_OPERAND_7__SHIFT) & DPU_EW_OP_VALUE_7_EW_OPERAND_7__MASK;
> +}
> +
> +#define REG_DPU_SURFACE_ADD 0x000040c0
> +#define DPU_SURFACE_ADD_SURF_ADD__MASK 0xfffffff0
> +#define DPU_SURFACE_ADD_SURF_ADD__SHIFT 4
> +static inline uint32_t DPU_SURFACE_ADD_SURF_ADD(uint32_t val)
> +{
> + return ((val) << DPU_SURFACE_ADD_SURF_ADD__SHIFT) & DPU_SURFACE_ADD_SURF_ADD__MASK;
> +}
> +#define DPU_SURFACE_ADD_RESERVED_0__MASK 0x0000000f
> +#define DPU_SURFACE_ADD_RESERVED_0__SHIFT 0
> +static inline uint32_t DPU_SURFACE_ADD_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_SURFACE_ADD_RESERVED_0__SHIFT) & DPU_SURFACE_ADD_RESERVED_0__MASK;
> +}
> +
> +#define REG_DPU_LUT_ACCESS_CFG 0x00004100
> +#define DPU_LUT_ACCESS_CFG_RESERVED_0__MASK 0xfffc0000
> +#define DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT 18
> +static inline uint32_t DPU_LUT_ACCESS_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_LUT_ACCESS_CFG_RESERVED_0__SHIFT) & DPU_LUT_ACCESS_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK 0x00020000
> +#define DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT 17
> +static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE(uint32_t val)
> +{
> + return ((val) << DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_ACCESS_TYPE__MASK;
> +}
> +#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK 0x00010000
> +#define DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT 16
> +static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_TABLE_ID(uint32_t val)
> +{
> + return ((val) << DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_TABLE_ID__MASK;
> +}
> +#define DPU_LUT_ACCESS_CFG_RESERVED_1__MASK 0x0000fc00
> +#define DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT 10
> +static inline uint32_t DPU_LUT_ACCESS_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_LUT_ACCESS_CFG_RESERVED_1__SHIFT) & DPU_LUT_ACCESS_CFG_RESERVED_1__MASK;
> +}
> +#define DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK 0x000003ff
> +#define DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT 0
> +static inline uint32_t DPU_LUT_ACCESS_CFG_LUT_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_LUT_ACCESS_CFG_LUT_ADDR__SHIFT) & DPU_LUT_ACCESS_CFG_LUT_ADDR__MASK;
> +}
> +
> +#define REG_DPU_LUT_ACCESS_DATA 0x00004104
> +#define DPU_LUT_ACCESS_DATA_RESERVED_0__MASK 0xffff0000
> +#define DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT 16
> +static inline uint32_t DPU_LUT_ACCESS_DATA_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_LUT_ACCESS_DATA_RESERVED_0__SHIFT) & DPU_LUT_ACCESS_DATA_RESERVED_0__MASK;
> +}
> +#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK 0x0000ffff
> +#define DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT 0
> +static inline uint32_t DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA(uint32_t val)
> +{
> + return ((val) << DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__SHIFT) & DPU_LUT_ACCESS_DATA_LUT_ACCESS_DATA__MASK;
> +}
> +
> +#define REG_DPU_LUT_CFG 0x00004108
> +#define DPU_LUT_CFG_RESERVED_0__MASK 0xffffff00
> +#define DPU_LUT_CFG_RESERVED_0__SHIFT 8
> +static inline uint32_t DPU_LUT_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_LUT_CFG_RESERVED_0__SHIFT) & DPU_LUT_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_LUT_CFG_LUT_CAL_SEL__MASK 0x00000080
> +#define DPU_LUT_CFG_LUT_CAL_SEL__SHIFT 7
> +static inline uint32_t DPU_LUT_CFG_LUT_CAL_SEL(uint32_t val)
> +{
> + return ((val) << DPU_LUT_CFG_LUT_CAL_SEL__SHIFT) & DPU_LUT_CFG_LUT_CAL_SEL__MASK;
> +}
> +#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK 0x00000040
> +#define DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT 6
> +static inline uint32_t DPU_LUT_CFG_LUT_HYBRID_PRIORITY(uint32_t val)
> +{
> + return ((val) << DPU_LUT_CFG_LUT_HYBRID_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_HYBRID_PRIORITY__MASK;
> +}
> +#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK 0x00000020
> +#define DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT 5
> +static inline uint32_t DPU_LUT_CFG_LUT_OFLOW_PRIORITY(uint32_t val)
> +{
> + return ((val) << DPU_LUT_CFG_LUT_OFLOW_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_OFLOW_PRIORITY__MASK;
> +}
> +#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK 0x00000010
> +#define DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT 4
> +static inline uint32_t DPU_LUT_CFG_LUT_UFLOW_PRIORITY(uint32_t val)
> +{
> + return ((val) << DPU_LUT_CFG_LUT_UFLOW_PRIORITY__SHIFT) & DPU_LUT_CFG_LUT_UFLOW_PRIORITY__MASK;
> +}
> +#define DPU_LUT_CFG_LUT_LO_LE_MUX__MASK 0x0000000c
> +#define DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT 2
> +static inline uint32_t DPU_LUT_CFG_LUT_LO_LE_MUX(uint32_t val)
> +{
> + return ((val) << DPU_LUT_CFG_LUT_LO_LE_MUX__SHIFT) & DPU_LUT_CFG_LUT_LO_LE_MUX__MASK;
> +}
> +#define DPU_LUT_CFG_LUT_EXPAND_EN__MASK 0x00000002
> +#define DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT 1
> +static inline uint32_t DPU_LUT_CFG_LUT_EXPAND_EN(uint32_t val)
> +{
> + return ((val) << DPU_LUT_CFG_LUT_EXPAND_EN__SHIFT) & DPU_LUT_CFG_LUT_EXPAND_EN__MASK;
> +}
> +#define DPU_LUT_CFG_LUT_ROAD_SEL__MASK 0x00000001
> +#define DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT 0
> +static inline uint32_t DPU_LUT_CFG_LUT_ROAD_SEL(uint32_t val)
> +{
> + return ((val) << DPU_LUT_CFG_LUT_ROAD_SEL__SHIFT) & DPU_LUT_CFG_LUT_ROAD_SEL__MASK;
> +}
> +
> +#define REG_DPU_LUT_INFO 0x0000410c
> +#define DPU_LUT_INFO_RESERVED_0__MASK 0xff000000
> +#define DPU_LUT_INFO_RESERVED_0__SHIFT 24
> +static inline uint32_t DPU_LUT_INFO_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_LUT_INFO_RESERVED_0__SHIFT) & DPU_LUT_INFO_RESERVED_0__MASK;
> +}
> +#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK 0x00ff0000
> +#define DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT 16
> +static inline uint32_t DPU_LUT_INFO_LUT_LO_INDEX_SELECT(uint32_t val)
> +{
> + return ((val) << DPU_LUT_INFO_LUT_LO_INDEX_SELECT__SHIFT) & DPU_LUT_INFO_LUT_LO_INDEX_SELECT__MASK;
> +}
> +#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK 0x0000ff00
> +#define DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT 8
> +static inline uint32_t DPU_LUT_INFO_LUT_LE_INDEX_SELECT(uint32_t val)
> +{
> + return ((val) << DPU_LUT_INFO_LUT_LE_INDEX_SELECT__SHIFT) & DPU_LUT_INFO_LUT_LE_INDEX_SELECT__MASK;
> +}
> +#define DPU_LUT_INFO_RESERVED_1__MASK 0x000000ff
> +#define DPU_LUT_INFO_RESERVED_1__SHIFT 0
> +static inline uint32_t DPU_LUT_INFO_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_LUT_INFO_RESERVED_1__SHIFT) & DPU_LUT_INFO_RESERVED_1__MASK;
> +}
> +
> +#define REG_DPU_LUT_LE_START 0x00004110
> +#define DPU_LUT_LE_START_LUT_LE_START__MASK 0xffffffff
> +#define DPU_LUT_LE_START_LUT_LE_START__SHIFT 0
> +static inline uint32_t DPU_LUT_LE_START_LUT_LE_START(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LE_START_LUT_LE_START__SHIFT) & DPU_LUT_LE_START_LUT_LE_START__MASK;
> +}
> +
> +#define REG_DPU_LUT_LE_END 0x00004114
> +#define DPU_LUT_LE_END_LUT_LE_END__MASK 0xffffffff
> +#define DPU_LUT_LE_END_LUT_LE_END__SHIFT 0
> +static inline uint32_t DPU_LUT_LE_END_LUT_LE_END(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LE_END_LUT_LE_END__SHIFT) & DPU_LUT_LE_END_LUT_LE_END__MASK;
> +}
> +
> +#define REG_DPU_LUT_LO_START 0x00004118
> +#define DPU_LUT_LO_START_LUT_LO_START__MASK 0xffffffff
> +#define DPU_LUT_LO_START_LUT_LO_START__SHIFT 0
> +static inline uint32_t DPU_LUT_LO_START_LUT_LO_START(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LO_START_LUT_LO_START__SHIFT) & DPU_LUT_LO_START_LUT_LO_START__MASK;
> +}
> +
> +#define REG_DPU_LUT_LO_END 0x0000411c
> +#define DPU_LUT_LO_END_LUT_LO_END__MASK 0xffffffff
> +#define DPU_LUT_LO_END_LUT_LO_END__SHIFT 0
> +static inline uint32_t DPU_LUT_LO_END_LUT_LO_END(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LO_END_LUT_LO_END__SHIFT) & DPU_LUT_LO_END_LUT_LO_END__MASK;
> +}
> +
> +#define REG_DPU_LUT_LE_SLOPE_SCALE 0x00004120
> +#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK 0xffff0000
> +#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT 16
> +static inline uint32_t DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__SHIFT) & DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_OFLOW_SCALE__MASK;
> +}
> +#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK 0x0000ffff
> +#define DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT 0
> +static inline uint32_t DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__SHIFT) & DPU_LUT_LE_SLOPE_SCALE_LUT_LE_SLOPE_UFLOW_SCALE__MASK;
> +}
> +
> +#define REG_DPU_LUT_LE_SLOPE_SHIFT 0x00004124
> +#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK 0xfffffc00
> +#define DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT 10
> +static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_RESERVED_0__MASK;
> +}
> +#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK 0x000003e0
> +#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT 5
> +static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_OFLOW_SHIFT__MASK;
> +}
> +#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK 0x0000001f
> +#define DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT 0
> +static inline uint32_t DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__SHIFT) & DPU_LUT_LE_SLOPE_SHIFT_LUT_LE_SLOPE_UFLOW_SHIFT__MASK;
> +}
> +
> +#define REG_DPU_LUT_LO_SLOPE_SCALE 0x00004128
> +#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK 0xffff0000
> +#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT 16
> +static inline uint32_t DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__SHIFT) & DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_OFLOW_SCALE__MASK;
> +}
> +#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK 0x0000ffff
> +#define DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT 0
> +static inline uint32_t DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__SHIFT) & DPU_LUT_LO_SLOPE_SCALE_LUT_LO_SLOPE_UFLOW_SCALE__MASK;
> +}
> +
> +#define REG_DPU_LUT_LO_SLOPE_SHIFT 0x0000412c
> +#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK 0xfffffc00
> +#define DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT 10
> +static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_RESERVED_0__MASK;
> +}
> +#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK 0x000003e0
> +#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT 5
> +static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_OFLOW_SHIFT__MASK;
> +}
> +#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK 0x0000001f
> +#define DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT 0
> +static inline uint32_t DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT(uint32_t val)
> +{
> + return ((val) << DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__SHIFT) & DPU_LUT_LO_SLOPE_SHIFT_LUT_LO_SLOPE_UFLOW_SHIFT__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_S_STATUS 0x00005000
> +#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK 0xfffc0000
> +#define DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT 18
> +static inline uint32_t DPU_RDMA_RDMA_S_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK 0x00030000
> +#define DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT 16
> +static inline uint32_t DPU_RDMA_RDMA_S_STATUS_STATUS_1(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT) & DPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK 0x0000fffc
> +#define DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT 2
> +static inline uint32_t DPU_RDMA_RDMA_S_STATUS_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK 0x00000003
> +#define DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_S_STATUS_STATUS_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT) & DPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_S_POINTER 0x00005004
> +#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK 0xfffe0000
> +#define DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT 17
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK 0x00010000
> +#define DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT 16
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
> +#define DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT 6
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
> +#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
> +#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
> +#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT 3
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
> +#define DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT) & DPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
> +#define DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT 1
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK;
> +}
> +#define DPU_RDMA_RDMA_S_POINTER_POINTER__MASK 0x00000001
> +#define DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_S_POINTER_POINTER(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT) & DPU_RDMA_RDMA_S_POINTER_POINTER__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_OPERATION_ENABLE 0x00005008
> +#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
> +#define DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
> +static inline uint32_t DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
> +#define DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT) & DPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_DATA_CUBE_WIDTH 0x0000500c
> +#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK 0xffffe000
> +#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT 13
> +static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_WIDTH_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK 0x00001fff
> +#define DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_WIDTH_WIDTH__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_DATA_CUBE_HEIGHT 0x00005010
> +#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK 0xe0000000
> +#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT 29
> +static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK 0x1fff0000
> +#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT 16
> +static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_EW_LINE_NOTCH_ADDR__MASK;
> +}
> +#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK 0x0000e000
> +#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT 13
> +static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_RESERVED_1__MASK;
> +}
> +#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK 0x00001fff
> +#define DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_HEIGHT_HEIGHT__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_DATA_CUBE_CHANNEL 0x00005014
> +#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK 0xffffe000
> +#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT 13
> +static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK 0x00001fff
> +#define DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__SHIFT) & DPU_RDMA_RDMA_DATA_CUBE_CHANNEL_CHANNEL__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_SRC_BASE_ADDR 0x00005018
> +#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK 0xffffffff
> +#define DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_BRDMA_CFG 0x0000501c
> +#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK 0xffffffe0
> +#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT 5
> +static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK 0x0000001e
> +#define DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT 1
> +static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_BRDMA_DATA_USE__MASK;
> +}
> +#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK 0x00000001
> +#define DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_BRDMA_CFG_RESERVED_1__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_BS_BASE_ADDR 0x00005020
> +#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK 0xffffffff
> +#define DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_BS_BASE_ADDR_BS_BASE_ADDR__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_NRDMA_CFG 0x00005028
> +#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK 0xffffffe0
> +#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT 5
> +static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK 0x0000001e
> +#define DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT 1
> +static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_NRDMA_DATA_USE__MASK;
> +}
> +#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK 0x00000001
> +#define DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_NRDMA_CFG_RESERVED_1__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_BN_BASE_ADDR 0x0000502c
> +#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK 0xffffffff
> +#define DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_BN_BASE_ADDR_BN_BASE_ADDR__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_ERDMA_CFG 0x00005034
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK 0xc0000000
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT 30
> +static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_MODE__MASK;
> +}
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK 0x20000000
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT 29
> +static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_SURF_MODE__MASK;
> +}
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK 0x10000000
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT 28
> +static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_NONALIGN__MASK;
> +}
> +#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK 0x0ffffff0
> +#define DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT 4
> +static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK 0x0000000c
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT 2
> +static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DATA_SIZE__MASK;
> +}
> +#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK 0x00000002
> +#define DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT 1
> +static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_OV4K_BYPASS__MASK;
> +}
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK 0x00000001
> +#define DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__SHIFT) & DPU_RDMA_RDMA_ERDMA_CFG_ERDMA_DISABLE__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_EW_BASE_ADDR 0x00005038
> +#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK 0xffffffff
> +#define DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__SHIFT) & DPU_RDMA_RDMA_EW_BASE_ADDR_EW_BASE_ADDR__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_EW_SURF_STRIDE 0x00005040
> +#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK 0xfffffff0
> +#define DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT 4
> +static inline uint32_t DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__SHIFT) & DPU_RDMA_RDMA_EW_SURF_STRIDE_EW_SURF_STRIDE__MASK;
> +}
> +#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
> +#define DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_EW_SURF_STRIDE_RESERVED_0__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_FEATURE_MODE_CFG 0x00005044
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK 0xfffc0000
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT 18
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK 0x00038000
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT 15
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_IN_PRECISION__MASK;
> +}
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK 0x00007800
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT 11
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_BURST_LEN__MASK;
> +}
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK 0x00000700
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT 8
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_COMB_USE__MASK;
> +}
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK 0x000000e0
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT 5
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_PROC_PRECISION__MASK;
> +}
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK 0x00000010
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT 4
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_DISABLE__MASK;
> +}
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK 0x00000008
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT 3
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_MRDMA_FP16TOFP32_EN__MASK;
> +}
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK 0x00000006
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT 1
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_CONV_MODE__MASK;
> +}
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK 0x00000001
> +#define DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__SHIFT) & DPU_RDMA_RDMA_FEATURE_MODE_CFG_FLYING_MODE__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_SRC_DMA_CFG 0x00005048
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK 0xfff80000
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT 19
> +static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_LINE_NOTCH_ADDR__MASK;
> +}
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK 0x0007c000
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT 14
> +static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK 0x00002000
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT 13
> +static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_POOLING_METHOD__MASK;
> +}
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK 0x00001000
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT 12
> +static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_UNPOOLING_EN__MASK;
> +}
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK 0x00000e00
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT 9
> +static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_HEIGHT__MASK;
> +}
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK 0x000001c0
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT 6
> +static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_STRIDE_WIDTH__MASK;
> +}
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK 0x00000038
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT 3
> +static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_HEIGHT__MASK;
> +}
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK 0x00000007
> +#define DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__SHIFT) & DPU_RDMA_RDMA_SRC_DMA_CFG_KERNEL_WIDTH__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_SURF_NOTCH 0x0000504c
> +#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK 0xfffffff0
> +#define DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT 4
> +static inline uint32_t DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__SHIFT) & DPU_RDMA_RDMA_SURF_NOTCH_SURF_NOTCH_ADDR__MASK;
> +}
> +#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
> +#define DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_SURF_NOTCH_RESERVED_0__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_PAD_CFG 0x00005064
> +#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK 0xffff0000
> +#define DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT 16
> +static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_VALUE__MASK;
> +}
> +#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK 0x0000ff80
> +#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT 7
> +static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_RESERVED_0__MASK;
> +}
> +#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK 0x00000070
> +#define DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT 4
> +static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_TOP(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_TOP__MASK;
> +}
> +#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK 0x00000008
> +#define DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT 3
> +static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_RESERVED_1__MASK;
> +}
> +#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK 0x00000007
> +#define DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__SHIFT) & DPU_RDMA_RDMA_PAD_CFG_PAD_LEFT__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_WEIGHT 0x00005068
> +#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK 0xff000000
> +#define DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT 24
> +static inline uint32_t DPU_RDMA_RDMA_WEIGHT_E_WEIGHT(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_E_WEIGHT__MASK;
> +}
> +#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK 0x00ff0000
> +#define DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT 16
> +static inline uint32_t DPU_RDMA_RDMA_WEIGHT_N_WEIGHT(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_N_WEIGHT__MASK;
> +}
> +#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK 0x0000ff00
> +#define DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT 8
> +static inline uint32_t DPU_RDMA_RDMA_WEIGHT_B_WEIGHT(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_B_WEIGHT__MASK;
> +}
> +#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK 0x000000ff
> +#define DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_WEIGHT_M_WEIGHT(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__SHIFT) & DPU_RDMA_RDMA_WEIGHT_M_WEIGHT__MASK;
> +}
> +
> +#define REG_DPU_RDMA_RDMA_EW_SURF_NOTCH 0x0000506c
> +#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK 0xfffffff0
> +#define DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT 4
> +static inline uint32_t DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__SHIFT) & DPU_RDMA_RDMA_EW_SURF_NOTCH_EW_SURF_NOTCH__MASK;
> +}
> +#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK 0x0000000f
> +#define DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT 0
> +static inline uint32_t DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__SHIFT) & DPU_RDMA_RDMA_EW_SURF_NOTCH_RESERVED_0__MASK;
> +}
> +
> +#define REG_PPU_S_STATUS 0x00006000
> +#define PPU_S_STATUS_RESERVED_0__MASK 0xfffc0000
> +#define PPU_S_STATUS_RESERVED_0__SHIFT 18
> +static inline uint32_t PPU_S_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_S_STATUS_RESERVED_0__SHIFT) & PPU_S_STATUS_RESERVED_0__MASK;
> +}
> +#define PPU_S_STATUS_STATUS_1__MASK 0x00030000
> +#define PPU_S_STATUS_STATUS_1__SHIFT 16
> +static inline uint32_t PPU_S_STATUS_STATUS_1(uint32_t val)
> +{
> + return ((val) << PPU_S_STATUS_STATUS_1__SHIFT) & PPU_S_STATUS_STATUS_1__MASK;
> +}
> +#define PPU_S_STATUS_RESERVED_1__MASK 0x0000fffc
> +#define PPU_S_STATUS_RESERVED_1__SHIFT 2
> +static inline uint32_t PPU_S_STATUS_RESERVED_1(uint32_t val)
> +{
> + return ((val) << PPU_S_STATUS_RESERVED_1__SHIFT) & PPU_S_STATUS_RESERVED_1__MASK;
> +}
> +#define PPU_S_STATUS_STATUS_0__MASK 0x00000003
> +#define PPU_S_STATUS_STATUS_0__SHIFT 0
> +static inline uint32_t PPU_S_STATUS_STATUS_0(uint32_t val)
> +{
> + return ((val) << PPU_S_STATUS_STATUS_0__SHIFT) & PPU_S_STATUS_STATUS_0__MASK;
> +}
> +
> +#define REG_PPU_S_POINTER 0x00006004
> +#define PPU_S_POINTER_RESERVED_0__MASK 0xfffe0000
> +#define PPU_S_POINTER_RESERVED_0__SHIFT 17
> +static inline uint32_t PPU_S_POINTER_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_RESERVED_0__SHIFT) & PPU_S_POINTER_RESERVED_0__MASK;
> +}
> +#define PPU_S_POINTER_EXECUTER__MASK 0x00010000
> +#define PPU_S_POINTER_EXECUTER__SHIFT 16
> +static inline uint32_t PPU_S_POINTER_EXECUTER(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_EXECUTER__SHIFT) & PPU_S_POINTER_EXECUTER__MASK;
> +}
> +#define PPU_S_POINTER_RESERVED_1__MASK 0x0000ffc0
> +#define PPU_S_POINTER_RESERVED_1__SHIFT 6
> +static inline uint32_t PPU_S_POINTER_RESERVED_1(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_RESERVED_1__SHIFT) & PPU_S_POINTER_RESERVED_1__MASK;
> +}
> +#define PPU_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
> +#define PPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
> +static inline uint32_t PPU_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & PPU_S_POINTER_EXECUTER_PP_CLEAR__MASK;
> +}
> +#define PPU_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
> +#define PPU_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
> +static inline uint32_t PPU_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_POINTER_PP_CLEAR__SHIFT) & PPU_S_POINTER_POINTER_PP_CLEAR__MASK;
> +}
> +#define PPU_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
> +#define PPU_S_POINTER_POINTER_PP_MODE__SHIFT 3
> +static inline uint32_t PPU_S_POINTER_POINTER_PP_MODE(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_POINTER_PP_MODE__SHIFT) & PPU_S_POINTER_POINTER_PP_MODE__MASK;
> +}
> +#define PPU_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
> +#define PPU_S_POINTER_EXECUTER_PP_EN__SHIFT 2
> +static inline uint32_t PPU_S_POINTER_EXECUTER_PP_EN(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_EXECUTER_PP_EN__SHIFT) & PPU_S_POINTER_EXECUTER_PP_EN__MASK;
> +}
> +#define PPU_S_POINTER_POINTER_PP_EN__MASK 0x00000002
> +#define PPU_S_POINTER_POINTER_PP_EN__SHIFT 1
> +static inline uint32_t PPU_S_POINTER_POINTER_PP_EN(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_POINTER_PP_EN__SHIFT) & PPU_S_POINTER_POINTER_PP_EN__MASK;
> +}
> +#define PPU_S_POINTER_POINTER__MASK 0x00000001
> +#define PPU_S_POINTER_POINTER__SHIFT 0
> +static inline uint32_t PPU_S_POINTER_POINTER(uint32_t val)
> +{
> + return ((val) << PPU_S_POINTER_POINTER__SHIFT) & PPU_S_POINTER_POINTER__MASK;
> +}
> +
> +#define REG_PPU_OPERATION_ENABLE 0x00006008
> +#define PPU_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
> +#define PPU_OPERATION_ENABLE_RESERVED_0__SHIFT 1
> +static inline uint32_t PPU_OPERATION_ENABLE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_ENABLE_RESERVED_0__SHIFT) & PPU_OPERATION_ENABLE_RESERVED_0__MASK;
> +}
> +#define PPU_OPERATION_ENABLE_OP_EN__MASK 0x00000001
> +#define PPU_OPERATION_ENABLE_OP_EN__SHIFT 0
> +static inline uint32_t PPU_OPERATION_ENABLE_OP_EN(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_ENABLE_OP_EN__SHIFT) & PPU_OPERATION_ENABLE_OP_EN__MASK;
> +}
> +
> +#define REG_PPU_DATA_CUBE_IN_WIDTH 0x0000600c
> +#define PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__MASK 0xffffe000
> +#define PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_DATA_CUBE_IN_WIDTH_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_WIDTH_RESERVED_0__MASK;
> +}
> +#define PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK 0x00001fff
> +#define PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT 0
> +static inline uint32_t PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT) & PPU_DATA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK;
> +}
> +
> +#define REG_PPU_DATA_CUBE_IN_HEIGHT 0x00006010
> +#define PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__MASK 0xffffe000
> +#define PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_HEIGHT_RESERVED_0__MASK;
> +}
> +#define PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK 0x00001fff
> +#define PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT 0
> +static inline uint32_t PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT) & PPU_DATA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK;
> +}
> +
> +#define REG_PPU_DATA_CUBE_IN_CHANNEL 0x00006014
> +#define PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__MASK 0xffffe000
> +#define PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT) & PPU_DATA_CUBE_IN_CHANNEL_RESERVED_0__MASK;
> +}
> +#define PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK 0x00001fff
> +#define PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT 0
> +static inline uint32_t PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT) & PPU_DATA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK;
> +}
> +
> +#define REG_PPU_DATA_CUBE_OUT_WIDTH 0x00006018
> +#define PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__MASK 0xffffe000
> +#define PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_WIDTH_RESERVED_0__MASK;
> +}
> +#define PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__MASK 0x00001fff
> +#define PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__SHIFT 0
> +static inline uint32_t PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__SHIFT) & PPU_DATA_CUBE_OUT_WIDTH_CUBE_OUT_WIDTH__MASK;
> +}
> +
> +#define REG_PPU_DATA_CUBE_OUT_HEIGHT 0x0000601c
> +#define PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__MASK 0xffffe000
> +#define PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_HEIGHT_RESERVED_0__MASK;
> +}
> +#define PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__MASK 0x00001fff
> +#define PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__SHIFT 0
> +static inline uint32_t PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__SHIFT) & PPU_DATA_CUBE_OUT_HEIGHT_CUBE_OUT_HEIGHT__MASK;
> +}
> +
> +#define REG_PPU_DATA_CUBE_OUT_CHANNEL 0x00006020
> +#define PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__MASK 0xffffe000
> +#define PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__SHIFT) & PPU_DATA_CUBE_OUT_CHANNEL_RESERVED_0__MASK;
> +}
> +#define PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__MASK 0x00001fff
> +#define PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__SHIFT 0
> +static inline uint32_t PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL(uint32_t val)
> +{
> + return ((val) << PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__SHIFT) & PPU_DATA_CUBE_OUT_CHANNEL_CUBE_OUT_CHANNEL__MASK;
> +}
> +
> +#define REG_PPU_OPERATION_MODE_CFG 0x00006024
> +#define PPU_OPERATION_MODE_CFG_RESERVED_0__MASK 0x80000000
> +#define PPU_OPERATION_MODE_CFG_RESERVED_0__SHIFT 31
> +static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_0__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_0__MASK;
> +}
> +#define PPU_OPERATION_MODE_CFG_INDEX_EN__MASK 0x40000000
> +#define PPU_OPERATION_MODE_CFG_INDEX_EN__SHIFT 30
> +static inline uint32_t PPU_OPERATION_MODE_CFG_INDEX_EN(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_INDEX_EN__SHIFT) & PPU_OPERATION_MODE_CFG_INDEX_EN__MASK;
> +}
> +#define PPU_OPERATION_MODE_CFG_RESERVED_1__MASK 0x20000000
> +#define PPU_OPERATION_MODE_CFG_RESERVED_1__SHIFT 29
> +static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_1__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_1__MASK;
> +}
> +#define PPU_OPERATION_MODE_CFG_NOTCH_ADDR__MASK 0x1fff0000
> +#define PPU_OPERATION_MODE_CFG_NOTCH_ADDR__SHIFT 16
> +static inline uint32_t PPU_OPERATION_MODE_CFG_NOTCH_ADDR(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_NOTCH_ADDR__SHIFT) & PPU_OPERATION_MODE_CFG_NOTCH_ADDR__MASK;
> +}
> +#define PPU_OPERATION_MODE_CFG_RESERVED_2__MASK 0x0000ff00
> +#define PPU_OPERATION_MODE_CFG_RESERVED_2__SHIFT 8
> +static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_2(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_2__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_2__MASK;
> +}
> +#define PPU_OPERATION_MODE_CFG_USE_CNT__MASK 0x000000e0
> +#define PPU_OPERATION_MODE_CFG_USE_CNT__SHIFT 5
> +static inline uint32_t PPU_OPERATION_MODE_CFG_USE_CNT(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_USE_CNT__SHIFT) & PPU_OPERATION_MODE_CFG_USE_CNT__MASK;
> +}
> +#define PPU_OPERATION_MODE_CFG_FLYING_MODE__MASK 0x00000010
> +#define PPU_OPERATION_MODE_CFG_FLYING_MODE__SHIFT 4
> +static inline uint32_t PPU_OPERATION_MODE_CFG_FLYING_MODE(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_FLYING_MODE__SHIFT) & PPU_OPERATION_MODE_CFG_FLYING_MODE__MASK;
> +}
> +#define PPU_OPERATION_MODE_CFG_RESERVED_3__MASK 0x0000000c
> +#define PPU_OPERATION_MODE_CFG_RESERVED_3__SHIFT 2
> +static inline uint32_t PPU_OPERATION_MODE_CFG_RESERVED_3(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_RESERVED_3__SHIFT) & PPU_OPERATION_MODE_CFG_RESERVED_3__MASK;
> +}
> +#define PPU_OPERATION_MODE_CFG_POOLING_METHOD__MASK 0x00000003
> +#define PPU_OPERATION_MODE_CFG_POOLING_METHOD__SHIFT 0
> +static inline uint32_t PPU_OPERATION_MODE_CFG_POOLING_METHOD(uint32_t val)
> +{
> + return ((val) << PPU_OPERATION_MODE_CFG_POOLING_METHOD__SHIFT) & PPU_OPERATION_MODE_CFG_POOLING_METHOD__MASK;
> +}
> +
> +#define REG_PPU_POOLING_KERNEL_CFG 0x00006034
> +#define PPU_POOLING_KERNEL_CFG_RESERVED_0__MASK 0xff000000
> +#define PPU_POOLING_KERNEL_CFG_RESERVED_0__SHIFT 24
> +static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_0__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_0__MASK;
> +}
> +#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__MASK 0x00f00000
> +#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__SHIFT 20
> +static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_HEIGHT__MASK;
> +}
> +#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__MASK 0x000f0000
> +#define PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__SHIFT 16
> +static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_STRIDE_WIDTH__MASK;
> +}
> +#define PPU_POOLING_KERNEL_CFG_RESERVED_1__MASK 0x0000f000
> +#define PPU_POOLING_KERNEL_CFG_RESERVED_1__SHIFT 12
> +static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_1__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_1__MASK;
> +}
> +#define PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__MASK 0x00000f00
> +#define PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__SHIFT 8
> +static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_HEIGHT__MASK;
> +}
> +#define PPU_POOLING_KERNEL_CFG_RESERVED_2__MASK 0x000000f0
> +#define PPU_POOLING_KERNEL_CFG_RESERVED_2__SHIFT 4
> +static inline uint32_t PPU_POOLING_KERNEL_CFG_RESERVED_2(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_KERNEL_CFG_RESERVED_2__SHIFT) & PPU_POOLING_KERNEL_CFG_RESERVED_2__MASK;
> +}
> +#define PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__MASK 0x0000000f
> +#define PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__SHIFT 0
> +static inline uint32_t PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__SHIFT) & PPU_POOLING_KERNEL_CFG_KERNEL_WIDTH__MASK;
> +}
> +
> +#define REG_PPU_RECIP_KERNEL_WIDTH 0x00006038
> +#define PPU_RECIP_KERNEL_WIDTH_RESERVED_0__MASK 0xfffe0000
> +#define PPU_RECIP_KERNEL_WIDTH_RESERVED_0__SHIFT 17
> +static inline uint32_t PPU_RECIP_KERNEL_WIDTH_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RECIP_KERNEL_WIDTH_RESERVED_0__SHIFT) & PPU_RECIP_KERNEL_WIDTH_RESERVED_0__MASK;
> +}
> +#define PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__MASK 0x0001ffff
> +#define PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__SHIFT 0
> +static inline uint32_t PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH(uint32_t val)
> +{
> + return ((val) << PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__SHIFT) & PPU_RECIP_KERNEL_WIDTH_RECIP_KERNEL_WIDTH__MASK;
> +}
> +
> +#define REG_PPU_RECIP_KERNEL_HEIGHT 0x0000603c
> +#define PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__MASK 0xfffe0000
> +#define PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__SHIFT 17
> +static inline uint32_t PPU_RECIP_KERNEL_HEIGHT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__SHIFT) & PPU_RECIP_KERNEL_HEIGHT_RESERVED_0__MASK;
> +}
> +#define PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__MASK 0x0001ffff
> +#define PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__SHIFT 0
> +static inline uint32_t PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT(uint32_t val)
> +{
> + return ((val) << PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__SHIFT) & PPU_RECIP_KERNEL_HEIGHT_RECIP_KERNEL_HEIGHT__MASK;
> +}
> +
> +#define REG_PPU_POOLING_PADDING_CFG 0x00006040
> +#define PPU_POOLING_PADDING_CFG_RESERVED_0__MASK 0xffff8000
> +#define PPU_POOLING_PADDING_CFG_RESERVED_0__SHIFT 15
> +static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_0__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_0__MASK;
> +}
> +#define PPU_POOLING_PADDING_CFG_PAD_BOTTOM__MASK 0x00007000
> +#define PPU_POOLING_PADDING_CFG_PAD_BOTTOM__SHIFT 12
> +static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_BOTTOM(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_PADDING_CFG_PAD_BOTTOM__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_BOTTOM__MASK;
> +}
> +#define PPU_POOLING_PADDING_CFG_RESERVED_1__MASK 0x00000800
> +#define PPU_POOLING_PADDING_CFG_RESERVED_1__SHIFT 11
> +static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_1(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_1__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_1__MASK;
> +}
> +#define PPU_POOLING_PADDING_CFG_PAD_RIGHT__MASK 0x00000700
> +#define PPU_POOLING_PADDING_CFG_PAD_RIGHT__SHIFT 8
> +static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_RIGHT(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_PADDING_CFG_PAD_RIGHT__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_RIGHT__MASK;
> +}
> +#define PPU_POOLING_PADDING_CFG_RESERVED_2__MASK 0x00000080
> +#define PPU_POOLING_PADDING_CFG_RESERVED_2__SHIFT 7
> +static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_2(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_2__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_2__MASK;
> +}
> +#define PPU_POOLING_PADDING_CFG_PAD_TOP__MASK 0x00000070
> +#define PPU_POOLING_PADDING_CFG_PAD_TOP__SHIFT 4
> +static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_TOP(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_PADDING_CFG_PAD_TOP__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_TOP__MASK;
> +}
> +#define PPU_POOLING_PADDING_CFG_RESERVED_3__MASK 0x00000008
> +#define PPU_POOLING_PADDING_CFG_RESERVED_3__SHIFT 3
> +static inline uint32_t PPU_POOLING_PADDING_CFG_RESERVED_3(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_PADDING_CFG_RESERVED_3__SHIFT) & PPU_POOLING_PADDING_CFG_RESERVED_3__MASK;
> +}
> +#define PPU_POOLING_PADDING_CFG_PAD_LEFT__MASK 0x00000007
> +#define PPU_POOLING_PADDING_CFG_PAD_LEFT__SHIFT 0
> +static inline uint32_t PPU_POOLING_PADDING_CFG_PAD_LEFT(uint32_t val)
> +{
> + return ((val) << PPU_POOLING_PADDING_CFG_PAD_LEFT__SHIFT) & PPU_POOLING_PADDING_CFG_PAD_LEFT__MASK;
> +}
> +
> +#define REG_PPU_PADDING_VALUE_1_CFG 0x00006044
> +#define PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__MASK 0xffffffff
> +#define PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__SHIFT 0
> +static inline uint32_t PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0(uint32_t val)
> +{
> + return ((val) << PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__SHIFT) & PPU_PADDING_VALUE_1_CFG_PAD_VALUE_0__MASK;
> +}
> +
> +#define REG_PPU_PADDING_VALUE_2_CFG 0x00006048
> +#define PPU_PADDING_VALUE_2_CFG_RESERVED_0__MASK 0xfffffff8
> +#define PPU_PADDING_VALUE_2_CFG_RESERVED_0__SHIFT 3
> +static inline uint32_t PPU_PADDING_VALUE_2_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_PADDING_VALUE_2_CFG_RESERVED_0__SHIFT) & PPU_PADDING_VALUE_2_CFG_RESERVED_0__MASK;
> +}
> +#define PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__MASK 0x00000007
> +#define PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__SHIFT 0
> +static inline uint32_t PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1(uint32_t val)
> +{
> + return ((val) << PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__SHIFT) & PPU_PADDING_VALUE_2_CFG_PAD_VALUE_1__MASK;
> +}
> +
> +#define REG_PPU_DST_BASE_ADDR 0x00006070
> +#define PPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK 0xfffffff0
> +#define PPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT 4
> +static inline uint32_t PPU_DST_BASE_ADDR_DST_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << PPU_DST_BASE_ADDR_DST_BASE_ADDR__SHIFT) & PPU_DST_BASE_ADDR_DST_BASE_ADDR__MASK;
> +}
> +#define PPU_DST_BASE_ADDR_RESERVED_0__MASK 0x0000000f
> +#define PPU_DST_BASE_ADDR_RESERVED_0__SHIFT 0
> +static inline uint32_t PPU_DST_BASE_ADDR_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_DST_BASE_ADDR_RESERVED_0__SHIFT) & PPU_DST_BASE_ADDR_RESERVED_0__MASK;
> +}
> +
> +#define REG_PPU_DST_SURF_STRIDE 0x0000607c
> +#define PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK 0xfffffff0
> +#define PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT 4
> +static inline uint32_t PPU_DST_SURF_STRIDE_DST_SURF_STRIDE(uint32_t val)
> +{
> + return ((val) << PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__SHIFT) & PPU_DST_SURF_STRIDE_DST_SURF_STRIDE__MASK;
> +}
> +#define PPU_DST_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
> +#define PPU_DST_SURF_STRIDE_RESERVED_0__SHIFT 0
> +static inline uint32_t PPU_DST_SURF_STRIDE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_DST_SURF_STRIDE_RESERVED_0__SHIFT) & PPU_DST_SURF_STRIDE_RESERVED_0__MASK;
> +}
> +
> +#define REG_PPU_DATA_FORMAT 0x00006084
> +#define PPU_DATA_FORMAT_INDEX_ADD__MASK 0xfffffff0
> +#define PPU_DATA_FORMAT_INDEX_ADD__SHIFT 4
> +static inline uint32_t PPU_DATA_FORMAT_INDEX_ADD(uint32_t val)
> +{
> + return ((val) << PPU_DATA_FORMAT_INDEX_ADD__SHIFT) & PPU_DATA_FORMAT_INDEX_ADD__MASK;
> +}
> +#define PPU_DATA_FORMAT_DPU_FLYIN__MASK 0x00000008
> +#define PPU_DATA_FORMAT_DPU_FLYIN__SHIFT 3
> +static inline uint32_t PPU_DATA_FORMAT_DPU_FLYIN(uint32_t val)
> +{
> + return ((val) << PPU_DATA_FORMAT_DPU_FLYIN__SHIFT) & PPU_DATA_FORMAT_DPU_FLYIN__MASK;
> +}
> +#define PPU_DATA_FORMAT_PROC_PRECISION__MASK 0x00000007
> +#define PPU_DATA_FORMAT_PROC_PRECISION__SHIFT 0
> +static inline uint32_t PPU_DATA_FORMAT_PROC_PRECISION(uint32_t val)
> +{
> + return ((val) << PPU_DATA_FORMAT_PROC_PRECISION__SHIFT) & PPU_DATA_FORMAT_PROC_PRECISION__MASK;
> +}
> +
> +#define REG_PPU_MISC_CTRL 0x000060dc
> +#define PPU_MISC_CTRL_SURF_LEN__MASK 0xffff0000
> +#define PPU_MISC_CTRL_SURF_LEN__SHIFT 16
> +static inline uint32_t PPU_MISC_CTRL_SURF_LEN(uint32_t val)
> +{
> + return ((val) << PPU_MISC_CTRL_SURF_LEN__SHIFT) & PPU_MISC_CTRL_SURF_LEN__MASK;
> +}
> +#define PPU_MISC_CTRL_RESERVED_0__MASK 0x0000fe00
> +#define PPU_MISC_CTRL_RESERVED_0__SHIFT 9
> +static inline uint32_t PPU_MISC_CTRL_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_MISC_CTRL_RESERVED_0__SHIFT) & PPU_MISC_CTRL_RESERVED_0__MASK;
> +}
> +#define PPU_MISC_CTRL_MC_SURF_OUT__MASK 0x00000100
> +#define PPU_MISC_CTRL_MC_SURF_OUT__SHIFT 8
> +static inline uint32_t PPU_MISC_CTRL_MC_SURF_OUT(uint32_t val)
> +{
> + return ((val) << PPU_MISC_CTRL_MC_SURF_OUT__SHIFT) & PPU_MISC_CTRL_MC_SURF_OUT__MASK;
> +}
> +#define PPU_MISC_CTRL_NONALIGN__MASK 0x00000080
> +#define PPU_MISC_CTRL_NONALIGN__SHIFT 7
> +static inline uint32_t PPU_MISC_CTRL_NONALIGN(uint32_t val)
> +{
> + return ((val) << PPU_MISC_CTRL_NONALIGN__SHIFT) & PPU_MISC_CTRL_NONALIGN__MASK;
> +}
> +#define PPU_MISC_CTRL_RESERVED_1__MASK 0x00000070
> +#define PPU_MISC_CTRL_RESERVED_1__SHIFT 4
> +static inline uint32_t PPU_MISC_CTRL_RESERVED_1(uint32_t val)
> +{
> + return ((val) << PPU_MISC_CTRL_RESERVED_1__SHIFT) & PPU_MISC_CTRL_RESERVED_1__MASK;
> +}
> +#define PPU_MISC_CTRL_BURST_LEN__MASK 0x0000000f
> +#define PPU_MISC_CTRL_BURST_LEN__SHIFT 0
> +static inline uint32_t PPU_MISC_CTRL_BURST_LEN(uint32_t val)
> +{
> + return ((val) << PPU_MISC_CTRL_BURST_LEN__SHIFT) & PPU_MISC_CTRL_BURST_LEN__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_S_STATUS 0x00007000
> +#define PPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK 0xfffc0000
> +#define PPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT 18
> +static inline uint32_t PPU_RDMA_RDMA_S_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_STATUS_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_S_STATUS_RESERVED_0__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK 0x00030000
> +#define PPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT 16
> +static inline uint32_t PPU_RDMA_RDMA_S_STATUS_STATUS_1(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_STATUS_STATUS_1__SHIFT) & PPU_RDMA_RDMA_S_STATUS_STATUS_1__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK 0x0000fffc
> +#define PPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT 2
> +static inline uint32_t PPU_RDMA_RDMA_S_STATUS_RESERVED_1(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_STATUS_RESERVED_1__SHIFT) & PPU_RDMA_RDMA_S_STATUS_RESERVED_1__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK 0x00000003
> +#define PPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_S_STATUS_STATUS_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_STATUS_STATUS_0__SHIFT) & PPU_RDMA_RDMA_S_STATUS_STATUS_0__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_S_POINTER 0x00007004
> +#define PPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK 0xfffe0000
> +#define PPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT 17
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_S_POINTER_RESERVED_0__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK 0x00010000
> +#define PPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT 16
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK 0x0000ffc0
> +#define PPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT 6
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_RESERVED_1(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_RESERVED_1__SHIFT) & PPU_RDMA_RDMA_S_POINTER_RESERVED_1__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK 0x00000020
> +#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT 5
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_CLEAR__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK 0x00000010
> +#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT 4
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_CLEAR__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK 0x00000008
> +#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT 3
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_MODE__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK 0x00000004
> +#define PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT 2
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__SHIFT) & PPU_RDMA_RDMA_S_POINTER_EXECUTER_PP_EN__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK 0x00000002
> +#define PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT 1
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER_PP_EN__MASK;
> +}
> +#define PPU_RDMA_RDMA_S_POINTER_POINTER__MASK 0x00000001
> +#define PPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_S_POINTER_POINTER(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_S_POINTER_POINTER__SHIFT) & PPU_RDMA_RDMA_S_POINTER_POINTER__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_OPERATION_ENABLE 0x00007008
> +#define PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK 0xfffffffe
> +#define PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT 1
> +static inline uint32_t PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_OPERATION_ENABLE_RESERVED_0__MASK;
> +}
> +#define PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK 0x00000001
> +#define PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__SHIFT) & PPU_RDMA_RDMA_OPERATION_ENABLE_OP_EN__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_CUBE_IN_WIDTH 0x0000700c
> +#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__MASK 0xffffe000
> +#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_WIDTH_RESERVED_0__MASK;
> +}
> +#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK 0x00001fff
> +#define PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_WIDTH_CUBE_IN_WIDTH__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_CUBE_IN_HEIGHT 0x00007010
> +#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__MASK 0xffffe000
> +#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_HEIGHT_RESERVED_0__MASK;
> +}
> +#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK 0x00001fff
> +#define PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_HEIGHT_CUBE_IN_HEIGHT__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_CUBE_IN_CHANNEL 0x00007014
> +#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__MASK 0xffffe000
> +#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT 13
> +static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_CHANNEL_RESERVED_0__MASK;
> +}
> +#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK 0x00001fff
> +#define PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__SHIFT) & PPU_RDMA_RDMA_CUBE_IN_CHANNEL_CUBE_IN_CHANNEL__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_SRC_BASE_ADDR 0x0000701c
> +#define PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK 0xffffffff
> +#define PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__SHIFT) & PPU_RDMA_RDMA_SRC_BASE_ADDR_SRC_BASE_ADDR__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_SRC_LINE_STRIDE 0x00007024
> +#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__MASK 0xfffffff0
> +#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__SHIFT 4
> +static inline uint32_t PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__SHIFT) & PPU_RDMA_RDMA_SRC_LINE_STRIDE_SRC_LINE_STRIDE__MASK;
> +}
> +#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__MASK 0x0000000f
> +#define PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_SRC_LINE_STRIDE_RESERVED_0__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_SRC_SURF_STRIDE 0x00007028
> +#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__MASK 0xfffffff0
> +#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__SHIFT 4
> +static inline uint32_t PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__SHIFT) & PPU_RDMA_RDMA_SRC_SURF_STRIDE_SRC_SURF_STRIDE__MASK;
> +}
> +#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__MASK 0x0000000f
> +#define PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_SRC_SURF_STRIDE_RESERVED_0__MASK;
> +}
> +
> +#define REG_PPU_RDMA_RDMA_DATA_FORMAT 0x00007030
> +#define PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__MASK 0xfffffffc
> +#define PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__SHIFT 2
> +static inline uint32_t PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__SHIFT) & PPU_RDMA_RDMA_DATA_FORMAT_RESERVED_0__MASK;
> +}
> +#define PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__MASK 0x00000003
> +#define PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__SHIFT 0
> +static inline uint32_t PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION(uint32_t val)
> +{
> + return ((val) << PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__SHIFT) & PPU_RDMA_RDMA_DATA_FORMAT_IN_PRECISION__MASK;
> +}
> +
> +#define REG_DDMA_CFG_OUTSTANDING 0x00008000
> +#define DDMA_CFG_OUTSTANDING_RESERVED_0__MASK 0xffff0000
> +#define DDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT 16
> +static inline uint32_t DDMA_CFG_OUTSTANDING_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT) & DDMA_CFG_OUTSTANDING_RESERVED_0__MASK;
> +}
> +#define DDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK 0x0000ff00
> +#define DDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT 8
> +static inline uint32_t DDMA_CFG_OUTSTANDING_WR_OS_CNT(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT) & DDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK;
> +}
> +#define DDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK 0x000000ff
> +#define DDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT 0
> +static inline uint32_t DDMA_CFG_OUTSTANDING_RD_OS_CNT(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT) & DDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK;
> +}
> +
> +#define REG_DDMA_RD_WEIGHT_0 0x00008004
> +#define DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK 0xff000000
> +#define DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT 24
> +static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP(uint32_t val)
> +{
> + return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK;
> +}
> +#define DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK 0x00ff0000
> +#define DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT 16
> +static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU(uint32_t val)
> +{
> + return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK;
> +}
> +#define DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK 0x0000ff00
> +#define DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT 8
> +static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL(uint32_t val)
> +{
> + return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK;
> +}
> +#define DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK 0x000000ff
> +#define DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT 0
> +static inline uint32_t DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE(uint32_t val)
> +{
> + return ((val) << DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT) & DDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK;
> +}
> +
> +#define REG_DDMA_WR_WEIGHT_0 0x00008008
> +#define DDMA_WR_WEIGHT_0_RESERVED_0__MASK 0xffff0000
> +#define DDMA_WR_WEIGHT_0_RESERVED_0__SHIFT 16
> +static inline uint32_t DDMA_WR_WEIGHT_0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_WR_WEIGHT_0_RESERVED_0__SHIFT) & DDMA_WR_WEIGHT_0_RESERVED_0__MASK;
> +}
> +#define DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK 0x0000ff00
> +#define DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT 8
> +static inline uint32_t DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP(uint32_t val)
> +{
> + return ((val) << DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT) & DDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK;
> +}
> +#define DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK 0x000000ff
> +#define DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT 0
> +static inline uint32_t DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU(uint32_t val)
> +{
> + return ((val) << DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT) & DDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK;
> +}
> +
> +#define REG_DDMA_CFG_ID_ERROR 0x0000800c
> +#define DDMA_CFG_ID_ERROR_RESERVED_0__MASK 0xfffffc00
> +#define DDMA_CFG_ID_ERROR_RESERVED_0__SHIFT 10
> +static inline uint32_t DDMA_CFG_ID_ERROR_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_ID_ERROR_RESERVED_0__SHIFT) & DDMA_CFG_ID_ERROR_RESERVED_0__MASK;
> +}
> +#define DDMA_CFG_ID_ERROR_WR_RESP_ID__MASK 0x000003c0
> +#define DDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT 6
> +static inline uint32_t DDMA_CFG_ID_ERROR_WR_RESP_ID(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT) & DDMA_CFG_ID_ERROR_WR_RESP_ID__MASK;
> +}
> +#define DDMA_CFG_ID_ERROR_RESERVED_1__MASK 0x00000020
> +#define DDMA_CFG_ID_ERROR_RESERVED_1__SHIFT 5
> +static inline uint32_t DDMA_CFG_ID_ERROR_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_ID_ERROR_RESERVED_1__SHIFT) & DDMA_CFG_ID_ERROR_RESERVED_1__MASK;
> +}
> +#define DDMA_CFG_ID_ERROR_RD_RESP_ID__MASK 0x0000001f
> +#define DDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT 0
> +static inline uint32_t DDMA_CFG_ID_ERROR_RD_RESP_ID(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT) & DDMA_CFG_ID_ERROR_RD_RESP_ID__MASK;
> +}
> +
> +#define REG_DDMA_RD_WEIGHT_1 0x00008010
> +#define DDMA_RD_WEIGHT_1_RESERVED_0__MASK 0xffffff00
> +#define DDMA_RD_WEIGHT_1_RESERVED_0__SHIFT 8
> +static inline uint32_t DDMA_RD_WEIGHT_1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_RD_WEIGHT_1_RESERVED_0__SHIFT) & DDMA_RD_WEIGHT_1_RESERVED_0__MASK;
> +}
> +#define DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK 0x000000ff
> +#define DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT 0
> +static inline uint32_t DDMA_RD_WEIGHT_1_RD_WEIGHT_PC(uint32_t val)
> +{
> + return ((val) << DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT) & DDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK;
> +}
> +
> +#define REG_DDMA_CFG_DMA_FIFO_CLR 0x00008014
> +#define DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK 0xfffffffe
> +#define DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT 1
> +static inline uint32_t DDMA_CFG_DMA_FIFO_CLR_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT) & DDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK;
> +}
> +#define DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK 0x00000001
> +#define DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT 0
> +static inline uint32_t DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT) & DDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK;
> +}
> +
> +#define REG_DDMA_CFG_DMA_ARB 0x00008018
> +#define DDMA_CFG_DMA_ARB_RESERVED_0__MASK 0xfffffc00
> +#define DDMA_CFG_DMA_ARB_RESERVED_0__SHIFT 10
> +static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_ARB_RESERVED_0__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_0__MASK;
> +}
> +#define DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK 0x00000200
> +#define DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT 9
> +static inline uint32_t DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT) & DDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK;
> +}
> +#define DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK 0x00000100
> +#define DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT 8
> +static inline uint32_t DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT) & DDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK;
> +}
> +#define DDMA_CFG_DMA_ARB_RESERVED_1__MASK 0x00000080
> +#define DDMA_CFG_DMA_ARB_RESERVED_1__SHIFT 7
> +static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_ARB_RESERVED_1__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_1__MASK;
> +}
> +#define DDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK 0x00000070
> +#define DDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT 4
> +static inline uint32_t DDMA_CFG_DMA_ARB_WR_FIX_ARB(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT) & DDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK;
> +}
> +#define DDMA_CFG_DMA_ARB_RESERVED_2__MASK 0x00000008
> +#define DDMA_CFG_DMA_ARB_RESERVED_2__SHIFT 3
> +static inline uint32_t DDMA_CFG_DMA_ARB_RESERVED_2(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_ARB_RESERVED_2__SHIFT) & DDMA_CFG_DMA_ARB_RESERVED_2__MASK;
> +}
> +#define DDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK 0x00000007
> +#define DDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT 0
> +static inline uint32_t DDMA_CFG_DMA_ARB_RD_FIX_ARB(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT) & DDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK;
> +}
> +
> +#define REG_DDMA_CFG_DMA_RD_QOS 0x00008020
> +#define DDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK 0xfffffc00
> +#define DDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT 10
> +static inline uint32_t DDMA_CFG_DMA_RD_QOS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT) & DDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK 0x00000300
> +#define DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT 8
> +static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_PC_QOS(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK 0x000000c0
> +#define DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT 6
> +static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK 0x00000030
> +#define DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT 4
> +static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK 0x0000000c
> +#define DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT 2
> +static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK 0x00000003
> +#define DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT 0
> +static inline uint32_t DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT) & DDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK;
> +}
> +
> +#define REG_DDMA_CFG_DMA_RD_CFG 0x00008024
> +#define DDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK 0xffffe000
> +#define DDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT 13
> +static inline uint32_t DDMA_CFG_DMA_RD_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT) & DDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK 0x00001000
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT 12
> +static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARLOCK(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK 0x00000f00
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT 8
> +static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARCACHE(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK 0x000000e0
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT 5
> +static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARPROT(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK 0x00000018
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT 3
> +static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARBURST(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK;
> +}
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK 0x00000007
> +#define DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT 0
> +static inline uint32_t DDMA_CFG_DMA_RD_CFG_RD_ARSIZE(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT) & DDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK;
> +}
> +
> +#define REG_DDMA_CFG_DMA_WR_CFG 0x00008028
> +#define DDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK 0xffffe000
> +#define DDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT 13
> +static inline uint32_t DDMA_CFG_DMA_WR_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT) & DDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK;
> +}
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK 0x00001000
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT 12
> +static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWLOCK(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK;
> +}
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK 0x00000f00
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT 8
> +static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWCACHE(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK;
> +}
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK 0x000000e0
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT 5
> +static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWPROT(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK;
> +}
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK 0x00000018
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT 3
> +static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWBURST(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK;
> +}
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK 0x00000007
> +#define DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT 0
> +static inline uint32_t DDMA_CFG_DMA_WR_CFG_WR_AWSIZE(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT) & DDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK;
> +}
> +
> +#define REG_DDMA_CFG_DMA_WSTRB 0x0000802c
> +#define DDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK 0xffffffff
> +#define DDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT 0
> +static inline uint32_t DDMA_CFG_DMA_WSTRB_WR_WSTRB(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT) & DDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK;
> +}
> +
> +#define REG_DDMA_CFG_STATUS 0x00008030
> +#define DDMA_CFG_STATUS_RESERVED_0__MASK 0xfffffe00
> +#define DDMA_CFG_STATUS_RESERVED_0__SHIFT 9
> +static inline uint32_t DDMA_CFG_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_STATUS_RESERVED_0__SHIFT) & DDMA_CFG_STATUS_RESERVED_0__MASK;
> +}
> +#define DDMA_CFG_STATUS_IDEL__MASK 0x00000100
> +#define DDMA_CFG_STATUS_IDEL__SHIFT 8
> +static inline uint32_t DDMA_CFG_STATUS_IDEL(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_STATUS_IDEL__SHIFT) & DDMA_CFG_STATUS_IDEL__MASK;
> +}
> +#define DDMA_CFG_STATUS_RESERVED_1__MASK 0x000000ff
> +#define DDMA_CFG_STATUS_RESERVED_1__SHIFT 0
> +static inline uint32_t DDMA_CFG_STATUS_RESERVED_1(uint32_t val)
> +{
> + return ((val) << DDMA_CFG_STATUS_RESERVED_1__SHIFT) & DDMA_CFG_STATUS_RESERVED_1__MASK;
> +}
> +
> +#define REG_SDMA_CFG_OUTSTANDING 0x00009000
> +#define SDMA_CFG_OUTSTANDING_RESERVED_0__MASK 0xffff0000
> +#define SDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT 16
> +static inline uint32_t SDMA_CFG_OUTSTANDING_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_OUTSTANDING_RESERVED_0__SHIFT) & SDMA_CFG_OUTSTANDING_RESERVED_0__MASK;
> +}
> +#define SDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK 0x0000ff00
> +#define SDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT 8
> +static inline uint32_t SDMA_CFG_OUTSTANDING_WR_OS_CNT(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_OUTSTANDING_WR_OS_CNT__SHIFT) & SDMA_CFG_OUTSTANDING_WR_OS_CNT__MASK;
> +}
> +#define SDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK 0x000000ff
> +#define SDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT 0
> +static inline uint32_t SDMA_CFG_OUTSTANDING_RD_OS_CNT(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_OUTSTANDING_RD_OS_CNT__SHIFT) & SDMA_CFG_OUTSTANDING_RD_OS_CNT__MASK;
> +}
> +
> +#define REG_SDMA_RD_WEIGHT_0 0x00009004
> +#define SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK 0xff000000
> +#define SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT 24
> +static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP(uint32_t val)
> +{
> + return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_PDP__MASK;
> +}
> +#define SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK 0x00ff0000
> +#define SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT 16
> +static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU(uint32_t val)
> +{
> + return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_DPU__MASK;
> +}
> +#define SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK 0x0000ff00
> +#define SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT 8
> +static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL(uint32_t val)
> +{
> + return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_KERNEL__MASK;
> +}
> +#define SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK 0x000000ff
> +#define SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT 0
> +static inline uint32_t SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE(uint32_t val)
> +{
> + return ((val) << SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__SHIFT) & SDMA_RD_WEIGHT_0_RD_WEIGHT_FEATURE__MASK;
> +}
> +
> +#define REG_SDMA_WR_WEIGHT_0 0x00009008
> +#define SDMA_WR_WEIGHT_0_RESERVED_0__MASK 0xffff0000
> +#define SDMA_WR_WEIGHT_0_RESERVED_0__SHIFT 16
> +static inline uint32_t SDMA_WR_WEIGHT_0_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_WR_WEIGHT_0_RESERVED_0__SHIFT) & SDMA_WR_WEIGHT_0_RESERVED_0__MASK;
> +}
> +#define SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK 0x0000ff00
> +#define SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT 8
> +static inline uint32_t SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP(uint32_t val)
> +{
> + return ((val) << SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__SHIFT) & SDMA_WR_WEIGHT_0_WR_WEIGHT_PDP__MASK;
> +}
> +#define SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK 0x000000ff
> +#define SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT 0
> +static inline uint32_t SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU(uint32_t val)
> +{
> + return ((val) << SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__SHIFT) & SDMA_WR_WEIGHT_0_WR_WEIGHT_DPU__MASK;
> +}
> +
> +#define REG_SDMA_CFG_ID_ERROR 0x0000900c
> +#define SDMA_CFG_ID_ERROR_RESERVED_0__MASK 0xfffffc00
> +#define SDMA_CFG_ID_ERROR_RESERVED_0__SHIFT 10
> +static inline uint32_t SDMA_CFG_ID_ERROR_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_ID_ERROR_RESERVED_0__SHIFT) & SDMA_CFG_ID_ERROR_RESERVED_0__MASK;
> +}
> +#define SDMA_CFG_ID_ERROR_WR_RESP_ID__MASK 0x000003c0
> +#define SDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT 6
> +static inline uint32_t SDMA_CFG_ID_ERROR_WR_RESP_ID(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_ID_ERROR_WR_RESP_ID__SHIFT) & SDMA_CFG_ID_ERROR_WR_RESP_ID__MASK;
> +}
> +#define SDMA_CFG_ID_ERROR_RESERVED_1__MASK 0x00000020
> +#define SDMA_CFG_ID_ERROR_RESERVED_1__SHIFT 5
> +static inline uint32_t SDMA_CFG_ID_ERROR_RESERVED_1(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_ID_ERROR_RESERVED_1__SHIFT) & SDMA_CFG_ID_ERROR_RESERVED_1__MASK;
> +}
> +#define SDMA_CFG_ID_ERROR_RD_RESP_ID__MASK 0x0000001f
> +#define SDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT 0
> +static inline uint32_t SDMA_CFG_ID_ERROR_RD_RESP_ID(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_ID_ERROR_RD_RESP_ID__SHIFT) & SDMA_CFG_ID_ERROR_RD_RESP_ID__MASK;
> +}
> +
> +#define REG_SDMA_RD_WEIGHT_1 0x00009010
> +#define SDMA_RD_WEIGHT_1_RESERVED_0__MASK 0xffffff00
> +#define SDMA_RD_WEIGHT_1_RESERVED_0__SHIFT 8
> +static inline uint32_t SDMA_RD_WEIGHT_1_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_RD_WEIGHT_1_RESERVED_0__SHIFT) & SDMA_RD_WEIGHT_1_RESERVED_0__MASK;
> +}
> +#define SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK 0x000000ff
> +#define SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT 0
> +static inline uint32_t SDMA_RD_WEIGHT_1_RD_WEIGHT_PC(uint32_t val)
> +{
> + return ((val) << SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__SHIFT) & SDMA_RD_WEIGHT_1_RD_WEIGHT_PC__MASK;
> +}
> +
> +#define REG_SDMA_CFG_DMA_FIFO_CLR 0x00009014
> +#define SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK 0xfffffffe
> +#define SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT 1
> +static inline uint32_t SDMA_CFG_DMA_FIFO_CLR_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__SHIFT) & SDMA_CFG_DMA_FIFO_CLR_RESERVED_0__MASK;
> +}
> +#define SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK 0x00000001
> +#define SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT 0
> +static inline uint32_t SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__SHIFT) & SDMA_CFG_DMA_FIFO_CLR_DMA_FIFO_CLR__MASK;
> +}
> +
> +#define REG_SDMA_CFG_DMA_ARB 0x00009018
> +#define SDMA_CFG_DMA_ARB_RESERVED_0__MASK 0xfffffc00
> +#define SDMA_CFG_DMA_ARB_RESERVED_0__SHIFT 10
> +static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_ARB_RESERVED_0__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_0__MASK;
> +}
> +#define SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK 0x00000200
> +#define SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT 9
> +static inline uint32_t SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__SHIFT) & SDMA_CFG_DMA_ARB_WR_ARBIT_MODEL__MASK;
> +}
> +#define SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK 0x00000100
> +#define SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT 8
> +static inline uint32_t SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__SHIFT) & SDMA_CFG_DMA_ARB_RD_ARBIT_MODEL__MASK;
> +}
> +#define SDMA_CFG_DMA_ARB_RESERVED_1__MASK 0x00000080
> +#define SDMA_CFG_DMA_ARB_RESERVED_1__SHIFT 7
> +static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_1(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_ARB_RESERVED_1__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_1__MASK;
> +}
> +#define SDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK 0x00000070
> +#define SDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT 4
> +static inline uint32_t SDMA_CFG_DMA_ARB_WR_FIX_ARB(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_ARB_WR_FIX_ARB__SHIFT) & SDMA_CFG_DMA_ARB_WR_FIX_ARB__MASK;
> +}
> +#define SDMA_CFG_DMA_ARB_RESERVED_2__MASK 0x00000008
> +#define SDMA_CFG_DMA_ARB_RESERVED_2__SHIFT 3
> +static inline uint32_t SDMA_CFG_DMA_ARB_RESERVED_2(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_ARB_RESERVED_2__SHIFT) & SDMA_CFG_DMA_ARB_RESERVED_2__MASK;
> +}
> +#define SDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK 0x00000007
> +#define SDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT 0
> +static inline uint32_t SDMA_CFG_DMA_ARB_RD_FIX_ARB(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_ARB_RD_FIX_ARB__SHIFT) & SDMA_CFG_DMA_ARB_RD_FIX_ARB__MASK;
> +}
> +
> +#define REG_SDMA_CFG_DMA_RD_QOS 0x00009020
> +#define SDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK 0xfffffc00
> +#define SDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT 10
> +static inline uint32_t SDMA_CFG_DMA_RD_QOS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_QOS_RESERVED_0__SHIFT) & SDMA_CFG_DMA_RD_QOS_RESERVED_0__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK 0x00000300
> +#define SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT 8
> +static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_PC_QOS(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_PC_QOS__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK 0x000000c0
> +#define SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT 6
> +static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_PPU_QOS__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK 0x00000030
> +#define SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT 4
> +static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_DPU_QOS__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK 0x0000000c
> +#define SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT 2
> +static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_KERNEL_QOS__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK 0x00000003
> +#define SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT 0
> +static inline uint32_t SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__SHIFT) & SDMA_CFG_DMA_RD_QOS_RD_FEATURE_QOS__MASK;
> +}
> +
> +#define REG_SDMA_CFG_DMA_RD_CFG 0x00009024
> +#define SDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK 0xffffe000
> +#define SDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT 13
> +static inline uint32_t SDMA_CFG_DMA_RD_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_CFG_RESERVED_0__SHIFT) & SDMA_CFG_DMA_RD_CFG_RESERVED_0__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK 0x00001000
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT 12
> +static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARLOCK(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARLOCK__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK 0x00000f00
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT 8
> +static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARCACHE(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARCACHE__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK 0x000000e0
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT 5
> +static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARPROT(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARPROT__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARPROT__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK 0x00000018
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT 3
> +static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARBURST(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARBURST__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARBURST__MASK;
> +}
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK 0x00000007
> +#define SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT 0
> +static inline uint32_t SDMA_CFG_DMA_RD_CFG_RD_ARSIZE(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__SHIFT) & SDMA_CFG_DMA_RD_CFG_RD_ARSIZE__MASK;
> +}
> +
> +#define REG_SDMA_CFG_DMA_WR_CFG 0x00009028
> +#define SDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK 0xffffe000
> +#define SDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT 13
> +static inline uint32_t SDMA_CFG_DMA_WR_CFG_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_WR_CFG_RESERVED_0__SHIFT) & SDMA_CFG_DMA_WR_CFG_RESERVED_0__MASK;
> +}
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK 0x00001000
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT 12
> +static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWLOCK(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWLOCK__MASK;
> +}
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK 0x00000f00
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT 8
> +static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWCACHE(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWCACHE__MASK;
> +}
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK 0x000000e0
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT 5
> +static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWPROT(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWPROT__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWPROT__MASK;
> +}
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK 0x00000018
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT 3
> +static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWBURST(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWBURST__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWBURST__MASK;
> +}
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK 0x00000007
> +#define SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT 0
> +static inline uint32_t SDMA_CFG_DMA_WR_CFG_WR_AWSIZE(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__SHIFT) & SDMA_CFG_DMA_WR_CFG_WR_AWSIZE__MASK;
> +}
> +
> +#define REG_SDMA_CFG_DMA_WSTRB 0x0000902c
> +#define SDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK 0xffffffff
> +#define SDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT 0
> +static inline uint32_t SDMA_CFG_DMA_WSTRB_WR_WSTRB(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_DMA_WSTRB_WR_WSTRB__SHIFT) & SDMA_CFG_DMA_WSTRB_WR_WSTRB__MASK;
> +}
> +
> +#define REG_SDMA_CFG_STATUS 0x00009030
> +#define SDMA_CFG_STATUS_RESERVED_0__MASK 0xfffffe00
> +#define SDMA_CFG_STATUS_RESERVED_0__SHIFT 9
> +static inline uint32_t SDMA_CFG_STATUS_RESERVED_0(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_STATUS_RESERVED_0__SHIFT) & SDMA_CFG_STATUS_RESERVED_0__MASK;
> +}
> +#define SDMA_CFG_STATUS_IDEL__MASK 0x00000100
> +#define SDMA_CFG_STATUS_IDEL__SHIFT 8
> +static inline uint32_t SDMA_CFG_STATUS_IDEL(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_STATUS_IDEL__SHIFT) & SDMA_CFG_STATUS_IDEL__MASK;
> +}
> +#define SDMA_CFG_STATUS_RESERVED_1__MASK 0x000000ff
> +#define SDMA_CFG_STATUS_RESERVED_1__SHIFT 0
> +static inline uint32_t SDMA_CFG_STATUS_RESERVED_1(uint32_t val)
> +{
> + return ((val) << SDMA_CFG_STATUS_RESERVED_1__SHIFT) & SDMA_CFG_STATUS_RESERVED_1__MASK;
> +}
> +
> +#define REG_GLOBAL_OPERATION_ENABLE 0x0000f008
> +#define GLOBAL_OPERATION_ENABLE_RESERVED_0__MASK 0xffffff80
> +#define GLOBAL_OPERATION_ENABLE_RESERVED_0__SHIFT 7
> +static inline uint32_t GLOBAL_OPERATION_ENABLE_RESERVED_0(uint32_t val)
> +{
> + return ((val) << GLOBAL_OPERATION_ENABLE_RESERVED_0__SHIFT) & GLOBAL_OPERATION_ENABLE_RESERVED_0__MASK;
> +}
> +#define GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__MASK 0x00000040
> +#define GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__SHIFT 6
> +static inline uint32_t GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN(uint32_t val)
> +{
> + return ((val) << GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_PPU_RDMA_OP_EN__MASK;
> +}
> +#define GLOBAL_OPERATION_ENABLE_PPU_OP_EN__MASK 0x00000020
> +#define GLOBAL_OPERATION_ENABLE_PPU_OP_EN__SHIFT 5
> +static inline uint32_t GLOBAL_OPERATION_ENABLE_PPU_OP_EN(uint32_t val)
> +{
> + return ((val) << GLOBAL_OPERATION_ENABLE_PPU_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_PPU_OP_EN__MASK;
> +}
> +#define GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__MASK 0x00000010
> +#define GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__SHIFT 4
> +static inline uint32_t GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN(uint32_t val)
> +{
> + return ((val) << GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_DPU_RDMA_OP_EN__MASK;
> +}
> +#define GLOBAL_OPERATION_ENABLE_DPU_OP_EN__MASK 0x00000008
> +#define GLOBAL_OPERATION_ENABLE_DPU_OP_EN__SHIFT 3
> +static inline uint32_t GLOBAL_OPERATION_ENABLE_DPU_OP_EN(uint32_t val)
> +{
> + return ((val) << GLOBAL_OPERATION_ENABLE_DPU_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_DPU_OP_EN__MASK;
> +}
> +#define GLOBAL_OPERATION_ENABLE_CORE_OP_EN__MASK 0x00000004
> +#define GLOBAL_OPERATION_ENABLE_CORE_OP_EN__SHIFT 2
> +static inline uint32_t GLOBAL_OPERATION_ENABLE_CORE_OP_EN(uint32_t val)
> +{
> + return ((val) << GLOBAL_OPERATION_ENABLE_CORE_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_CORE_OP_EN__MASK;
> +}
> +#define GLOBAL_OPERATION_ENABLE_RESERVED_1__MASK 0x00000002
> +#define GLOBAL_OPERATION_ENABLE_RESERVED_1__SHIFT 1
> +static inline uint32_t GLOBAL_OPERATION_ENABLE_RESERVED_1(uint32_t val)
> +{
> + return ((val) << GLOBAL_OPERATION_ENABLE_RESERVED_1__SHIFT) & GLOBAL_OPERATION_ENABLE_RESERVED_1__MASK;
> +}
> +#define GLOBAL_OPERATION_ENABLE_CNA_OP_EN__MASK 0x00000001
> +#define GLOBAL_OPERATION_ENABLE_CNA_OP_EN__SHIFT 0
> +static inline uint32_t GLOBAL_OPERATION_ENABLE_CNA_OP_EN(uint32_t val)
> +{
> + return ((val) << GLOBAL_OPERATION_ENABLE_CNA_OP_EN__SHIFT) & GLOBAL_OPERATION_ENABLE_CNA_OP_EN__MASK;
> +}
> +
> +#endif /* __ROCKET_REGISTERS_XML__ */
>
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
11 months, 3 weeks
- 1
- 0
Re: [PATCH v3 1/3] drm/format-helper: Add conversion from XRGB8888 to BGR888
by Thomas Zimmermann
Hi
Am 21.02.25 um 16:51 schrieb andriy.shevchenko(a)linux.intel.com:
> On Fri, Feb 21, 2025 at 11:36:00AM +0000, Aditya Garg wrote:
>> From: Kerem Karabay <kekrby(a)gmail.com>
>>
>> Add XRGB8888 emulation helper for devices that only support BGR888.
> ...
>
>> + for (x = 0; x < pixels; x++) {
>> + pix = le32_to_cpu(sbuf32[x]);
>> + /* write red-green-blue to output in little endianness */
>> + *dbuf8++ = (pix & 0x00ff0000) >> 16;
>> + *dbuf8++ = (pix & 0x0000ff00) >> 8;
>> + *dbuf8++ = (pix & 0x000000ff) >> 0;
> put_unaligned_be24()
I'm all for sharing helper code, but maybe not here.
- DRM pixel formats are always little endian.
- CPU encoding is LE or BE.
- Pixel-component order can be anything: RGB/BGR/etc.
So the code has a comment to explain what happens here. Adding that call
with the _be24 postfix into the mix would make it more confusing.
>
>> + }
> ...
>
>> + static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = {
>> + 3,
>> + };
> One line?
>
> static const u8 dst_pixsize[DRM_FORMAT_MAX_PLANES] = { 3 };
I'd be ok, if there's a string preference in the kernel to use thins
style. Most of DRM doesn't AFAIK.
Best regards
Thomas
>
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
11 months, 3 weeks
- 1
- 0
Re: [PATCH v3 3/3] drm/tiny: add driver for Apple Touch Bars in x86 Macs
by Thomas Zimmermann
Hi
Am 21.02.25 um 12:37 schrieb Aditya Garg:
> From: Kerem Karabay <kekrby(a)gmail.com>
>
> The Touch Bars found on x86 Macs support two USB configurations: one
> where the device presents itself as a HID keyboard and can display
> predefined sets of keys, and one where the operating system has full
> control over what is displayed.
>
> This commit adds support for the display functionality of the second
> configuration. Functionality for the first configuration has been
> merged in the HID tree.
>
> Note that this driver has only been tested on T2 Macs, and only includes
> the USB device ID for these devices. Testing on T1 Macs would be
> appreciated.
>
> Credit goes to Ben (Bingxing) Wang on GitHub [1] for reverse engineering
> most of the protocol.
>
> [1]: https://github.com/imbushuo/DFRDisplayKm
>
> Signed-off-by: Kerem Karabay <kekrby(a)gmail.com>
> Co-developed-by: Atharva Tiwari <evepolonium(a)gmail.com>
> Signed-off-by: Atharva Tiwari <evepolonium(a)gmail.com>
> Co-developed-by: Aditya Garg <gargaditya08(a)live.com>
> Signed-off-by: Aditya Garg <gargaditya08(a)live.com>
> Signed-off-by: Aun-Ali Zaidi <admin(a)kodeit.net>
> ---
> v2 ->
> - Add the driver to MAINTAINERS.
> - Allocate memory for request and response in plane's atomic-check helper
> - Void the use of drm_fb_blit()
> - Implement atomic_disable
> - Make PRIME work
> - Remove the date field from struct drm_driver
> - intersect damage with dst_clip
> - Register DRM device in appletbdrm_probe
> - Clear the display as the final call in probe
> - Select hid_multitouch as well in kconfig
>
> v3 ->
> - Change commit message to credit Ben (Bingxing) Wang
> MAINTAINERS | 7 +
> drivers/gpu/drm/tiny/Kconfig | 14 +
> drivers/gpu/drm/tiny/Makefile | 1 +
> drivers/gpu/drm/tiny/appletbdrm.c | 806 ++++++++++++++++++++++++++++++
> 4 files changed, 828 insertions(+)
> create mode 100644 drivers/gpu/drm/tiny/appletbdrm.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index efee40ea5..43fafaab3 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -7148,6 +7148,13 @@ S: Supported
> T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
> F: drivers/gpu/drm/sun4i/sun8i*
>
> +DRM DRIVER FOR APPLE TOUCH BARS
> +M: Aun-Ali Zaidi <admin(a)kodeit.net>
You cannot put someone else here. Who is that?
> +L: dri-devel(a)lists.freedesktop.org
> +S: Maintained
> +T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
> +F: drivers/gpu/drm/tiny/appletbdrm.c
> +
> DRM DRIVER FOR ARM PL111 CLCD
> M: Linus Walleij <linus.walleij(a)linaro.org>
> S: Maintained
> diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig
> index 94cbdb133..25471791c 100644
> --- a/drivers/gpu/drm/tiny/Kconfig
> +++ b/drivers/gpu/drm/tiny/Kconfig
> @@ -1,5 +1,19 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> +config DRM_APPLETBDRM
> + tristate "DRM support for Apple Touch Bars"
> + depends on DRM && USB && MMU
> + select DRM_GEM_SHMEM_HELPER
> + select DRM_KMS_HELPER
> + select HID_APPLETB_BL
> + select HID_MULTITOUCH
> + help
> + Say Y here if you want support for the display of Touch Bars on x86
> + MacBook Pros.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called appletbdrm.
> +
> config DRM_ARCPGU
> tristate "ARC PGU"
> depends on DRM && OF
> diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile
> index 60816d2eb..0a3a7837a 100644
> --- a/drivers/gpu/drm/tiny/Makefile
> +++ b/drivers/gpu/drm/tiny/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0-only
>
> +obj-$(CONFIG_DRM_APPLETBDRM) += appletbdrm.o
> obj-$(CONFIG_DRM_ARCPGU) += arcpgu.o
> obj-$(CONFIG_DRM_BOCHS) += bochs.o
> obj-$(CONFIG_DRM_CIRRUS_QEMU) += cirrus-qemu.o
> diff --git a/drivers/gpu/drm/tiny/appletbdrm.c b/drivers/gpu/drm/tiny/appletbdrm.c
Putting this driver into tiny is ok. It's the preferred place for
single-file DRM drivers like this one.
> new file mode 100644
> index 000000000..a17a3ecc3
> --- /dev/null
> +++ b/drivers/gpu/drm/tiny/appletbdrm.c
> @@ -0,0 +1,806 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Apple Touch Bar DRM Driver
> + *
> + * Copyright (c) 2023 Kerem Karabay <kekrby(a)gmail.com>
> + */
> +
> +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
> +
> +#include <linux/module.h>
> +#include <linux/unaligned.h>
> +#include <linux/usb.h>
> +
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_damage_helper.h>
> +#include <drm/drm_drv.h>
> +#include <drm/drm_encoder.h>
> +#include <drm/drm_format_helper.h>
> +#include <drm/drm_fourcc.h>
> +#include <drm/drm_framebuffer.h>
> +#include <drm/drm_gem_atomic_helper.h>
> +#include <drm/drm_gem_framebuffer_helper.h>
> +#include <drm/drm_gem_shmem_helper.h>
> +#include <drm/drm_plane.h>
> +#include <drm/drm_probe_helper.h>
> +
> +#define __APPLETBDRM_MSG_STR4(str4) ((__le32 __force)((str4[0] << 24) | (str4[1] << 16) | (str4[2] << 8) | str4[3]))
> +#define __APPLETBDRM_MSG_TOK4(tok4) __APPLETBDRM_MSG_STR4(#tok4)
> +
> +#define APPLETBDRM_PIXEL_FORMAT __APPLETBDRM_MSG_TOK4(RGBA) /* The actual format is BGR888 */
> +#define APPLETBDRM_BITS_PER_PIXEL 24
> +
> +#define APPLETBDRM_MSG_CLEAR_DISPLAY __APPLETBDRM_MSG_TOK4(CLRD)
> +#define APPLETBDRM_MSG_GET_INFORMATION __APPLETBDRM_MSG_TOK4(GINF)
> +#define APPLETBDRM_MSG_UPDATE_COMPLETE __APPLETBDRM_MSG_TOK4(UDCL)
> +#define APPLETBDRM_MSG_SIGNAL_READINESS __APPLETBDRM_MSG_TOK4(REDY)
> +
> +#define APPLETBDRM_BULK_MSG_TIMEOUT 1000
> +
> +#define drm_to_adev(_drm) container_of(_drm, struct appletbdrm_device, drm)
> +#define adev_to_udev(adev) interface_to_usbdev(to_usb_interface(adev->dev))
> +
> +struct appletbdrm_msg_request_header {
> + __le16 unk_00;
> + __le16 unk_02;
> + __le32 unk_04;
> + __le32 unk_08;
> + __le32 size;
> +} __packed;
> +
> +struct appletbdrm_msg_response_header {
> + u8 unk_00[16];
> + __le32 msg;
> +} __packed;
> +
> +struct appletbdrm_msg_simple_request {
> + struct appletbdrm_msg_request_header header;
> + __le32 msg;
> + u8 unk_14[8];
> + __le32 size;
> +} __packed;
> +
> +struct appletbdrm_msg_information {
> + struct appletbdrm_msg_response_header header;
> + u8 unk_14[12];
> + __le32 width;
> + __le32 height;
> + u8 bits_per_pixel;
> + __le32 bytes_per_row;
> + __le32 orientation;
> + __le32 bitmap_info;
> + __le32 pixel_format;
> + __le32 width_inches; /* floating point */
> + __le32 height_inches; /* floating point */
> +} __packed;
> +
> +struct appletbdrm_frame {
> + __le16 begin_x;
> + __le16 begin_y;
> + __le16 width;
> + __le16 height;
> + __le32 buf_size;
> + u8 buf[];
> +} __packed;
> +
> +struct appletbdrm_fb_request_footer {
> + u8 unk_00[12];
> + __le32 unk_0c;
> + u8 unk_10[12];
> + __le32 unk_1c;
> + __le64 timestamp;
> + u8 unk_28[12];
> + __le32 unk_34;
> + u8 unk_38[20];
> + __le32 unk_4c;
> +} __packed;
> +
> +struct appletbdrm_fb_request {
> + struct appletbdrm_msg_request_header header;
> + __le16 unk_10;
> + u8 msg_id;
> + u8 unk_13[29];
> + /*
> + * Contents of `data`:
> + * - struct appletbdrm_frame frames[];
> + * - struct appletbdrm_fb_request_footer footer;
> + * - padding to make the total size a multiple of 16
> + */
> + u8 data[];
> +} __packed;
> +
> +struct appletbdrm_fb_request_response {
> + struct appletbdrm_msg_response_header header;
> + u8 unk_14[12];
> + __le64 timestamp;
> +} __packed;
> +
> +struct appletbdrm_device {
> + struct device *dev;
This field should not be here. The Linux device is already available at
drm.dev.
> + struct device *dmadev;
> +
> + unsigned int in_ep;
> + unsigned int out_ep;
> +
> + unsigned int width;
> + unsigned int height;
> +
> + struct drm_device drm;
> + struct drm_display_mode mode;
> + struct drm_connector connector;
> + struct drm_plane primary_plane;
> + struct drm_crtc crtc;
> + struct drm_encoder encoder;
> +};
> +
> +struct appletbdrm_plane_state {
> + struct drm_shadow_plane_state base;
> + struct appletbdrm_fb_request *request;
> + struct appletbdrm_fb_request_response *response;
> + size_t request_size;
> + size_t frames_size;
> +};
> +
> +static inline struct appletbdrm_plane_state *to_appletbdrm_plane_state(struct drm_plane_state *state)
> +{
> + return container_of(state, struct appletbdrm_plane_state, base.base);
> +}
> +
> +static int appletbdrm_send_request(struct appletbdrm_device *adev,
> + struct appletbdrm_msg_request_header *request, size_t size)
> +{
> + struct usb_device *udev = adev_to_udev(adev);
> + struct drm_device *drm = &adev->drm;
> + int ret, actual_size;
> +
> + ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, adev->out_ep),
> + request, size, &actual_size, APPLETBDRM_BULK_MSG_TIMEOUT);
> + if (ret) {
> + drm_err(drm, "Failed to send message (%d)\n", ret);
> + return ret;
> + }
> +
> + if (actual_size != size) {
> + drm_err(drm, "Actual size (%d) doesn't match expected size (%lu)\n",
> + actual_size, size);
> + return -EIO;
> + }
> +
> + return ret;
> +}
> +
> +static int appletbdrm_read_response(struct appletbdrm_device *adev,
> + struct appletbdrm_msg_response_header *response,
> + size_t size, u32 expected_response)
> +{
> + struct usb_device *udev = adev_to_udev(adev);
> + struct drm_device *drm = &adev->drm;
> + int ret, actual_size;
> + bool readiness_signal_received = false;
> +
> +retry:
> + ret = usb_bulk_msg(udev, usb_rcvbulkpipe(udev, adev->in_ep),
> + response, size, &actual_size, APPLETBDRM_BULK_MSG_TIMEOUT);
> + if (ret) {
> + drm_err(drm, "Failed to read response (%d)\n", ret);
> + return ret;
> + }
> +
> + /*
> + * The device responds to the first request sent in a particular
> + * timeframe after the USB device configuration is set with a readiness
> + * signal, in which case the response should be read again
> + */
> + if (response->msg == APPLETBDRM_MSG_SIGNAL_READINESS) {
> + if (!readiness_signal_received) {
> + readiness_signal_received = true;
> + goto retry;
> + }
> +
> + drm_err(drm, "Encountered unexpected readiness signal\n");
> + return -EIO;
> + }
> +
> + if (actual_size != size) {
> + drm_err(drm, "Actual size (%d) doesn't match expected size (%lu)\n",
> + actual_size, size);
> + return -EIO;
> + }
> +
> + if (response->msg != expected_response) {
> + drm_err(drm, "Unexpected response from device (expected %p4ch found %p4ch)\n",
> + &expected_response, &response->msg);
> + return -EIO;
> + }
> +
> + return 0;
> +}
> +
> +static int appletbdrm_send_msg(struct appletbdrm_device *adev, u32 msg)
> +{
> + struct appletbdrm_msg_simple_request *request;
> + int ret;
> +
> + request = kzalloc(sizeof(*request), GFP_KERNEL);
> + if (!request)
> + return -ENOMEM;
> +
> + request->header.unk_00 = cpu_to_le16(2);
> + request->header.unk_02 = cpu_to_le16(0x1512);
> + request->header.size = cpu_to_le32(sizeof(*request) - sizeof(request->header));
> + request->msg = msg;
> + request->size = request->header.size;
> +
> + ret = appletbdrm_send_request(adev, &request->header, sizeof(*request));
> +
> + kfree(request);
> +
> + return ret;
> +}
> +
> +static int appletbdrm_clear_display(struct appletbdrm_device *adev)
> +{
> + return appletbdrm_send_msg(adev, APPLETBDRM_MSG_CLEAR_DISPLAY);
> +}
> +
> +static int appletbdrm_signal_readiness(struct appletbdrm_device *adev)
> +{
> + return appletbdrm_send_msg(adev, APPLETBDRM_MSG_SIGNAL_READINESS);
> +}
> +
> +static int appletbdrm_get_information(struct appletbdrm_device *adev)
> +{
> + struct appletbdrm_msg_information *info;
> + struct drm_device *drm = &adev->drm;
> + u8 bits_per_pixel;
> + u32 pixel_format;
> + int ret;
> +
> + info = kzalloc(sizeof(*info), GFP_KERNEL);
> + if (!info)
> + return -ENOMEM;
> +
> + ret = appletbdrm_send_msg(adev, APPLETBDRM_MSG_GET_INFORMATION);
> + if (ret)
> + return ret;
> +
> + ret = appletbdrm_read_response(adev, &info->header, sizeof(*info),
> + APPLETBDRM_MSG_GET_INFORMATION);
> + if (ret)
> + goto free_info;
> +
> + bits_per_pixel = info->bits_per_pixel;
> + pixel_format = get_unaligned(&info->pixel_format);
> +
> + adev->width = get_unaligned_le32(&info->width);
> + adev->height = get_unaligned_le32(&info->height);
> +
> + if (bits_per_pixel != APPLETBDRM_BITS_PER_PIXEL) {
> + drm_err(drm, "Encountered unexpected bits per pixel value (%d)\n", bits_per_pixel);
> + ret = -EINVAL;
> + goto free_info;
> + }
> +
> + if (pixel_format != APPLETBDRM_PIXEL_FORMAT) {
> + drm_err(drm, "Encountered unknown pixel format (%p4ch)\n", &pixel_format);
> + ret = -EINVAL;
> + goto free_info;
> + }
> +
> +free_info:
> + kfree(info);
> +
> + return ret;
> +}
> +
> +static u32 rect_size(struct drm_rect *rect)
> +{
> + return drm_rect_width(rect) * drm_rect_height(rect) * (APPLETBDRM_BITS_PER_PIXEL / 8);
> +}
> +
> +static int appletbdrm_connector_helper_get_modes(struct drm_connector *connector)
> +{
> + struct appletbdrm_device *adev = drm_to_adev(connector->dev);
> +
> + return drm_connector_helper_get_modes_fixed(connector, &adev->mode);
> +}
> +
> +static const u32 appletbdrm_primary_plane_formats[] = {
> + DRM_FORMAT_BGR888,
> + DRM_FORMAT_XRGB8888, /* emulated */
> +};
> +
> +static int appletbdrm_primary_plane_helper_atomic_check(struct drm_plane *plane,
> + struct drm_atomic_state *state)
> +{
> + struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
> + struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
> + struct drm_crtc *new_crtc = new_plane_state->crtc;
> + struct drm_crtc_state *new_crtc_state = NULL;
> + struct appletbdrm_plane_state *appletbdrm_state = to_appletbdrm_plane_state(new_plane_state);
> + struct drm_atomic_helper_damage_iter iter;
> + struct drm_rect damage;
> + size_t frames_size = 0;
> + size_t request_size;
> + int ret;
> +
> + if (new_crtc)
> + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc);
> +
> + ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
> + DRM_PLANE_NO_SCALING,
> + DRM_PLANE_NO_SCALING,
> + false, false);
> + if (ret)
> + return ret;
> + else if (!new_plane_state->visible)
> + return 0;
> +
> + drm_atomic_helper_damage_iter_init(&iter, old_plane_state, new_plane_state);
> + drm_atomic_for_each_plane_damage(&iter, &damage) {
> + frames_size += struct_size((struct appletbdrm_frame *)0, buf, rect_size(&damage));
> + }
> +
> + if (!frames_size)
> + return 0;
> +
> + request_size = ALIGN(sizeof(struct appletbdrm_fb_request) +
> + frames_size +
> + sizeof(struct appletbdrm_fb_request_footer), 16);
> +
> + appletbdrm_state->request = kzalloc(request_size, GFP_KERNEL);
> +
> + if (!appletbdrm_state->request)
> + return -ENOMEM;
> +
> + appletbdrm_state->response = kzalloc(sizeof(*appletbdrm_state->response), GFP_KERNEL);
> +
> + if (!appletbdrm_state->response)
> + return -ENOMEM;
> +
> + appletbdrm_state->request_size = request_size;
> + appletbdrm_state->frames_size = frames_size;
AFAIU you're preallocating the memory for the drawing commands. Makes
sense to me.
> +
> + return 0;
> +}
> +
> +static int appletbdrm_flush_damage(struct appletbdrm_device *adev,
> + struct drm_plane_state *old_state,
> + struct drm_plane_state *state)
> +{
> + struct appletbdrm_plane_state *appletbdrm_state = to_appletbdrm_plane_state(state);
> + struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(state);
> + struct appletbdrm_fb_request_response *response = appletbdrm_state->response;
> + struct appletbdrm_fb_request_footer *footer;
> + struct drm_atomic_helper_damage_iter iter;
> + struct drm_framebuffer *fb = state->fb;
> + struct appletbdrm_fb_request *request = appletbdrm_state->request;
> + struct drm_device *drm = &adev->drm;
> + struct appletbdrm_frame *frame;
> + u64 timestamp = ktime_get_ns();
> + struct drm_rect damage;
> + size_t frames_size = appletbdrm_state->frames_size;
> + size_t request_size = appletbdrm_state->request_size;
> + int ret;
> +
> + if (!frames_size)
> + return 0;
> +
> + ret = drm_gem_fb_begin_cpu_access(fb, DMA_FROM_DEVICE);
> + if (ret) {
> + drm_err(drm, "Failed to start CPU framebuffer access (%d)\n", ret);
> + goto end_fb_cpu_access;
> + }
> +
> + request->header.unk_00 = cpu_to_le16(2);
> + request->header.unk_02 = cpu_to_le16(0x12);
> + request->header.unk_04 = cpu_to_le32(9);
> + request->header.size = cpu_to_le32(request_size - sizeof(request->header));
> + request->unk_10 = cpu_to_le16(1);
> + request->msg_id = timestamp & 0xff;
> +
> + frame = (struct appletbdrm_frame *)request->data;
> +
> + drm_atomic_helper_damage_iter_init(&iter, old_state, state);
> + drm_atomic_for_each_plane_damage(&iter, &damage) {
> + struct drm_rect dst_clip = state->dst;
> + struct iosys_map dst = IOSYS_MAP_INIT_VADDR(frame->buf);
> + u32 buf_size = rect_size(&damage);
> +
> + if (!drm_rect_intersect(&dst_clip, &damage))
> + continue;
> +
> + /*
> + * The coordinates need to be translated to the coordinate
> + * system the device expects, see the comment in
> + * appletbdrm_setup_mode_config
> + */
> + frame->begin_x = cpu_to_le16(damage.y1);
> + frame->begin_y = cpu_to_le16(adev->height - damage.x2);
> + frame->width = cpu_to_le16(drm_rect_height(&damage));
> + frame->height = cpu_to_le16(drm_rect_width(&damage));
> + frame->buf_size = cpu_to_le32(buf_size);
> +
> + switch (fb->format->format) {
> + case DRM_FORMAT_XRGB8888:
> + drm_fb_xrgb8888_to_bgr888(&dst, NULL, &shadow_plane_state->data[0], fb, &damage, &shadow_plane_state->fmtcnv_state);
> + break;
> + default:
> + drm_fb_memcpy(&dst, NULL, &shadow_plane_state->data[0], fb, &damage);
> + break;
> + }
> +
> + frame = (void *)frame + struct_size(frame, buf, buf_size);
> + }
> +
> + footer = (struct appletbdrm_fb_request_footer *)&request->data[frames_size];
> +
> + footer->unk_0c = cpu_to_le32(0xfffe);
> + footer->unk_1c = cpu_to_le32(0x80001);
> + footer->unk_34 = cpu_to_le32(0x80002);
> + footer->unk_4c = cpu_to_le32(0xffff);
> + footer->timestamp = cpu_to_le64(timestamp);
And here you're building the drawing commands from the allocated frame
memory. Also makes sense.
> +
> + ret = appletbdrm_send_request(adev, &request->header, request_size);
> + if (ret)
> + goto end_fb_cpu_access;
> +
> + ret = appletbdrm_read_response(adev, &response->header, sizeof(*response),
> + APPLETBDRM_MSG_UPDATE_COMPLETE);
> + if (ret)
> + goto end_fb_cpu_access;
> +
> + if (response->timestamp != footer->timestamp) {
> + drm_err(drm, "Response timestamp (%llu) doesn't match request timestamp (%llu)\n",
> + le64_to_cpu(response->timestamp), timestamp);
> + goto end_fb_cpu_access;
> + }
> +
> +end_fb_cpu_access:
> + drm_gem_fb_end_cpu_access(fb, DMA_FROM_DEVICE);
> +
> + return ret;
> +}
> +
> +static void appletbdrm_primary_plane_helper_atomic_update(struct drm_plane *plane,
> + struct drm_atomic_state *old_state)
> +{
> + struct appletbdrm_device *adev = drm_to_adev(plane->dev);
> + struct drm_device *drm = plane->dev;
> + struct drm_plane_state *plane_state = plane->state;
> + struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(old_state, plane);
> + int idx;
> +
> + if (!drm_dev_enter(drm, &idx))
> + return;
> +
> + appletbdrm_flush_damage(adev, old_plane_state, plane_state);
> +
> + drm_dev_exit(idx);
> +}
> +
> +static void appletbdrm_primary_plane_helper_atomic_disable(struct drm_plane *plane,
> + struct drm_atomic_state *state)
> +{
> + struct drm_device *dev = plane->dev;
> + struct appletbdrm_device *adev = drm_to_adev(dev);
> + int idx;
> +
> + if (!drm_dev_enter(dev, &idx))
> + return;
> +
> + appletbdrm_clear_display(adev);
> +
> + drm_dev_exit(idx);
> +}
> +
> +static void appletbdrm_primary_plane_reset(struct drm_plane *plane)
> +{
> + struct appletbdrm_plane_state *appletbdrm_state;
> +
> + WARN_ON(plane->state);
> +
> + appletbdrm_state = kzalloc(sizeof(*appletbdrm_state), GFP_KERNEL);
> + if (!appletbdrm_state)
> + return;
> +
> + __drm_gem_reset_shadow_plane(plane, &appletbdrm_state->base);
> +}
> +
> +static struct drm_plane_state *appletbdrm_primary_plane_duplicate_state(struct drm_plane *plane)
> +{
> + struct drm_shadow_plane_state *new_shadow_plane_state;
> + struct appletbdrm_plane_state *old_appletbdrm_state;
> + struct appletbdrm_plane_state *appletbdrm_state;
> +
> + if (WARN_ON(!plane->state))
> + return NULL;
> +
> + old_appletbdrm_state = to_appletbdrm_plane_state(plane->state);
> + appletbdrm_state = kmemdup(old_appletbdrm_state, sizeof(*appletbdrm_state), GFP_KERNEL);
> + if (!appletbdrm_state)
> + return NULL;
> +
> + /* Request and response are not duplicated and are allocated in .atomic_check */
> + appletbdrm_state->request = NULL;
> + appletbdrm_state->response = NULL;
You also have to clear the frame and request size, I think.
Duplicated state will be processed by the atomic_check before being
used. So you'll have a chance of recomputing these temporary buffers.
Simply allocate with kzalloc instead of kmemdup() and you'll be fine.
> +
> + new_shadow_plane_state = &appletbdrm_state->base;
> +
> + __drm_gem_duplicate_shadow_plane_state(plane, new_shadow_plane_state);
This call is important to do.
> +
> + return &new_shadow_plane_state->base;
> +}
> +
> +static void appletbdrm_primary_plane_destroy_state(struct drm_plane *plane,
> + struct drm_plane_state *state)
> +{
> + struct appletbdrm_plane_state *appletbdrm_state = to_appletbdrm_plane_state(state);
> +
> + kfree(appletbdrm_state->request);
> + kfree(appletbdrm_state->response);
> +
> + __drm_gem_destroy_shadow_plane_state(&appletbdrm_state->base);
> +
> + kfree(appletbdrm_state);
> +}
> +
> +static const struct drm_plane_helper_funcs appletbdrm_primary_plane_helper_funcs = {
> + DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
> + .atomic_check = appletbdrm_primary_plane_helper_atomic_check,
> + .atomic_update = appletbdrm_primary_plane_helper_atomic_update,
> + .atomic_disable = appletbdrm_primary_plane_helper_atomic_disable,
> +};
> +
> +static const struct drm_plane_funcs appletbdrm_primary_plane_funcs = {
> + .update_plane = drm_atomic_helper_update_plane,
> + .disable_plane = drm_atomic_helper_disable_plane,
> + .reset = appletbdrm_primary_plane_reset,
> + .atomic_duplicate_state = appletbdrm_primary_plane_duplicate_state,
> + .atomic_destroy_state = appletbdrm_primary_plane_destroy_state,
> + .destroy = drm_plane_cleanup,
> +};
> +
> +static enum drm_mode_status appletbdrm_crtc_helper_mode_valid(struct drm_crtc *crtc,
> + const struct drm_display_mode *mode)
> +{
> + struct appletbdrm_device *adev = drm_to_adev(crtc->dev);
> +
> + return drm_crtc_helper_mode_valid_fixed(crtc, mode, &adev->mode);
> +}
> +
> +static const struct drm_mode_config_funcs appletbdrm_mode_config_funcs = {
> + .fb_create = drm_gem_fb_create_with_dirty,
> + .atomic_check = drm_atomic_helper_check,
> + .atomic_commit = drm_atomic_helper_commit,
> +};
> +
> +static const struct drm_connector_funcs appletbdrm_connector_funcs = {
> + .reset = drm_atomic_helper_connector_reset,
> + .destroy = drm_connector_cleanup,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> +};
> +
> +static const struct drm_connector_helper_funcs appletbdrm_connector_helper_funcs = {
> + .get_modes = appletbdrm_connector_helper_get_modes,
> +};
> +
> +static const struct drm_crtc_helper_funcs appletbdrm_crtc_helper_funcs = {
> + .mode_valid = appletbdrm_crtc_helper_mode_valid,
> +};
> +
> +static const struct drm_crtc_funcs appletbdrm_crtc_funcs = {
> + .reset = drm_atomic_helper_crtc_reset,
> + .destroy = drm_crtc_cleanup,
> + .set_config = drm_atomic_helper_set_config,
> + .page_flip = drm_atomic_helper_page_flip,
> + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> +};
> +
> +static const struct drm_encoder_funcs appletbdrm_encoder_funcs = {
> + .destroy = drm_encoder_cleanup,
> +};
> +
> +static struct drm_gem_object *appletbdrm_driver_gem_prime_import(struct drm_device *dev,
> + struct dma_buf *dma_buf)
> +{
> + struct appletbdrm_device *adev = drm_to_adev(dev);
> +
> + if (!adev->dmadev)
> + return ERR_PTR(-ENODEV);
> +
> + return drm_gem_prime_import_dev(dev, dma_buf, adev->dmadev);
> +}
> +
> +DEFINE_DRM_GEM_FOPS(appletbdrm_drm_fops);
> +
> +static const struct drm_driver appletbdrm_drm_driver = {
> + DRM_GEM_SHMEM_DRIVER_OPS,
> + .gem_prime_import = appletbdrm_driver_gem_prime_import,
> + .name = "appletbdrm",
> + .desc = "Apple Touch Bar DRM Driver",
> + .major = 1,
> + .minor = 0,
> + .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
> + .fops = &appletbdrm_drm_fops,
> +};
> +
> +static int appletbdrm_setup_mode_config(struct appletbdrm_device *adev)
> +{
> + struct drm_connector *connector = &adev->connector;
> + struct drm_plane *primary_plane;
> + struct drm_crtc *crtc;
> + struct drm_encoder *encoder;
> + struct drm_device *drm = &adev->drm;
> + struct device *dev = adev->dev;
> + int ret;
> +
> + ret = drmm_mode_config_init(drm);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to initialize mode configuration\n");
Use drm_err() here. It does the right thing. We don't have a
drm_dev_probe() yet, but you're discouraged from useing the dev_() print
helpers.
Same below.
> +
> + primary_plane = &adev->primary_plane;
> + ret = drm_universal_plane_init(drm, primary_plane, 0,
> + &appletbdrm_primary_plane_funcs,
> + appletbdrm_primary_plane_formats,
> + ARRAY_SIZE(appletbdrm_primary_plane_formats),
> + NULL,
> + DRM_PLANE_TYPE_PRIMARY, NULL);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to initialize universal plane object\n");
> + drm_plane_helper_add(primary_plane, &appletbdrm_primary_plane_helper_funcs);
> + drm_plane_enable_fb_damage_clips(primary_plane);
> +
> + crtc = &adev->crtc;
> + ret = drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
> + &appletbdrm_crtc_funcs, NULL);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to initialize CRTC object\n");
> + drm_crtc_helper_add(crtc, &appletbdrm_crtc_helper_funcs);
> +
> + encoder = &adev->encoder;
> + ret = drm_encoder_init(drm, encoder, &appletbdrm_encoder_funcs,
> + DRM_MODE_ENCODER_DAC, NULL);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to initialize encoder\n");
> + encoder->possible_crtcs = drm_crtc_mask(crtc);
> +
> + /*
> + * The coordinate system used by the device is different from the
> + * coordinate system of the framebuffer in that the x and y axes are
> + * swapped, and that the y axis is inverted; so what the device reports
> + * as the height is actually the width of the framebuffer and vice
> + * versa
> + */
> + drm->mode_config.min_width = 0;
> + drm->mode_config.min_height = 0;
No need to clear this to zero.
> + drm->mode_config.max_width = max(adev->height, DRM_SHADOW_PLANE_MAX_WIDTH);
> + drm->mode_config.max_height = max(adev->width, DRM_SHADOW_PLANE_MAX_HEIGHT);
> + drm->mode_config.preferred_depth = APPLETBDRM_BITS_PER_PIXEL;
> + drm->mode_config.funcs = &appletbdrm_mode_config_funcs;
> +
> + adev->mode = (struct drm_display_mode) {
> + DRM_MODE_INIT(60, adev->height, adev->width,
> + DRM_MODE_RES_MM(adev->height, 218),
> + DRM_MODE_RES_MM(adev->width, 218))
> + };
> +
> + ret = drm_connector_init(drm, connector,
> + &appletbdrm_connector_funcs, DRM_MODE_CONNECTOR_USB);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to initialize connector\n");
> +
> + drm_connector_helper_add(connector, &appletbdrm_connector_helper_funcs);
> +
> + ret = drm_connector_set_panel_orientation(connector,
> + DRM_MODE_PANEL_ORIENTATION_RIGHT_UP);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to set panel orientation\n");
> +
> + connector->display_info.non_desktop = true;
> + ret = drm_object_property_set_value(&connector->base,
> + drm->mode_config.non_desktop_property, true);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to set non-desktop property\n");
> +
> + ret = drm_connector_attach_encoder(connector, encoder);
> +
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to initialize simple display pipe\n");
> +
> + drm_mode_config_reset(drm);
> +
> + return 0;
> +}
> +
> +static int appletbdrm_probe(struct usb_interface *intf,
> + const struct usb_device_id *id)
> +{
> + struct usb_endpoint_descriptor *bulk_in, *bulk_out;
> + struct device *dev = &intf->dev;
> + struct appletbdrm_device *adev;
> + struct drm_device *drm;
> + int ret;
> +
> + ret = usb_find_common_endpoints(intf->cur_altsetting, &bulk_in, &bulk_out, NULL, NULL);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to find bulk endpoints\n");
> +
> + adev = devm_drm_dev_alloc(dev, &appletbdrm_drm_driver, struct appletbdrm_device, drm);
> + if (IS_ERR(adev))
> + return PTR_ERR(adev);
> +
> + adev->dev = dev;
> + adev->in_ep = bulk_in->bEndpointAddress;
> + adev->out_ep = bulk_out->bEndpointAddress;
> +
> + drm = &adev->drm;
> +
> + usb_set_intfdata(intf, adev);
> +
> + ret = appletbdrm_get_information(adev);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to get display information\n");
> +
> + ret = appletbdrm_signal_readiness(adev);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to signal readiness\n");
> +
> + ret = appletbdrm_setup_mode_config(adev);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to setup mode config\n");
> +
> + ret = drm_dev_register(drm, 0);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to register DRM device\n");
> +
> + ret = appletbdrm_clear_display(adev);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to clear display\n");
> +
> + return 0;
> +}
> +
> +static void appletbdrm_disconnect(struct usb_interface *intf)
> +{
> + struct appletbdrm_device *adev = usb_get_intfdata(intf);
> + struct drm_device *drm = &adev->drm;
> +
You have to put_device(dmadev) to release the DMA device.
Best regards
Thomas
> + drm_dev_unplug(drm);
> + drm_atomic_helper_shutdown(drm);
> +}
> +
> +static void appletbdrm_shutdown(struct usb_interface *intf)
> +{
> + struct appletbdrm_device *adev = usb_get_intfdata(intf);
> +
> + /*
> + * The framebuffer needs to be cleared on shutdown since its content
> + * persists across boots
> + */
> + drm_atomic_helper_shutdown(&adev->drm);
> +}
> +
> +static const struct usb_device_id appletbdrm_usb_id_table[] = {
> + { USB_DEVICE_INTERFACE_CLASS(0x05ac, 0x8302, USB_CLASS_AUDIO_VIDEO) },
> + {}
> +};
> +MODULE_DEVICE_TABLE(usb, appletbdrm_usb_id_table);
> +
> +static struct usb_driver appletbdrm_usb_driver = {
> + .name = "appletbdrm",
> + .probe = appletbdrm_probe,
> + .disconnect = appletbdrm_disconnect,
> + .shutdown = appletbdrm_shutdown,
> + .id_table = appletbdrm_usb_id_table,
> +};
> +module_usb_driver(appletbdrm_usb_driver);
> +
> +MODULE_AUTHOR("Kerem Karabay <kekrby(a)gmail.com>");
> +MODULE_DESCRIPTION("Apple Touch Bar DRM Driver");
> +MODULE_LICENSE("GPL");
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
11 months, 3 weeks
- 1
- 0
Re: [PATCH v3 3/3] drm/tiny: add driver for Apple Touch Bars in x86 Macs
by Thomas Zimmermann
Hi
Am 22.02.25 um 10:07 schrieb Aditya Garg:
>> What padding, please? Why TCP UAPI headers do not have these attributes?
>> Think about it, and think about what actually __packed does and how it affects
>> (badly) the code generation. Otherwise it looks like a cargo cult.
>>
>>> I tried removing __packed btw and driver no longer works.
>> So, you need to find a justification why. But definitely not due to padding in
>> many of them. They can go without __packed as they are naturally aligned.
> Alright, I did some debugging, basically printk sizeof(struct). Did it for both packed and unpacked with the following results:
>
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_msg_request_header is 16
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_msg_request_header_unpacked is 16
>
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_msg_response_header is 20
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_msg_response_header_unpacked is 20
>
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_msg_simple_request is 32
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_msg_simple_request_unpacked is 32
>
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_msg_information is 65
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_msg_information_unpacked is 68
In the unpacked version, there is a 3-byte gap after the
'bits_per_pixel' to align the next field. Using __packed removes those
gaps at the expense of runtime overhead.
>
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_frame is 12
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_frame_unpacked is 12
>
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_fb_request_footer is 80
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_fb_request_footer_unpacked is 80
>
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_fb_request is 48
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_fb_request_unpacked is 48
>
> Feb 22 13:02:03 MacBook kernel: size of struct appletbdrm_fb_request_response is 40
> Feb 22 13:02:04 MacBook kernel: size of struct appletbdrm_fb_request_response_unpacked is 40
>
> So, the difference in sizeof in unpacked and packed is only in appletbdrm_msg_information. So, I kept this packed, and removed it from others. The Touch Bar still works.
>
> So maybe keep just this packed?
The fields in the TCP header are aligned by design. Unfortunately, this
hardware's protocol is not. And there's no way of fixing this now. Just
keep all of them packed if you want. At least it's clear then what
happens. And if your hardware requires this, you can't do much anyway.
Best regards
Thomas
>>
>>
>> ...
>>
>>>>> + if (response->msg == APPLETBDRM_MSG_SIGNAL_READINESS) {
>>>>> + if (!readiness_signal_received) {
>>>>> + readiness_signal_received = true;
>>>>> + goto retry;
>>>>> + }
>>>>> +
>>>>> + drm_err(drm, "Encountered unexpected readiness signal\n");
>>>>> + return -EIO;
>>>>> + }
>>>>> +
>>>>> + if (actual_size != size) {
>>>>> + drm_err(drm, "Actual size (%d) doesn't match expected size (%lu)\n",
>>>>> + actual_size, size);
>>>>> + return -EIO;
>>>>> + }
>>>>> +
>>>>> + if (response->msg != expected_response) {
>>>>> + drm_err(drm, "Unexpected response from device (expected %p4ch found %p4ch)\n",
>>>>> + &expected_response, &response->msg);
>>>>> + return -EIO;
>>>> For three different cases the same error code, can it be adjusted more to the
>>>> situation?
>>> All these are I/O errors, you got any suggestion?
>> Your email client mangled the code so badly that it's hard to read. But I would
>> suggest to use -EINTR in the first case, and -EBADMSG. But also you may consider
>> -EPROTO.
> Thanks
>>>>> + }
>> ...
>>
>>>>> + if (ret)
>>>>> + return ret;
>>>>> + else if (!new_plane_state->visible)
>>>> Why 'else'? It's redundant.
>>> I’ve just followed what other drm drivers are doing here:
>>>
>>> https://elixir.bootlin.com/linux/v6.13.3/source/drivers/gpu/drm/tiny/bochs.…
>>> https://elixir.bootlin.com/linux/v6.13.3/source/drivers/gpu/drm/tiny/cirrus…
>>>
>>> And plenty more
>> A bad example is still a bad example. 'else' is simply redundant in this
>> case and add a noisy to the code.
>>
>>> I won’t mind removing else. You want that?
>> Sure.
>>
>> ...
>>
>>>>> + request_size = ALIGN(sizeof(struct appletbdrm_fb_request) +
>>>>> + frames_size +
>>>>> + sizeof(struct appletbdrm_fb_request_footer), 16);
>>>> Missing header for ALIGN().
>>>>
>>>> But have you checked overflow.h for the possibility of using some helper macros
>>>> from there? This is what should be usually done for k*alloc() in the kernel.
>>> I don’t really think we need a macro here.
>> Hmm... is frames_size known to be in a guaranteed range to make sure no
>> potential overflow happens?
> I don’t really find any cause of potential overflow.
>
>
>>>>> + appletbdrm_state->request = kzalloc(request_size, GFP_KERNEL);
>>>>> +
>>>>> + if (!appletbdrm_state->request)
>>>>> + return -ENOMEM;
>> ...
>>
>>>>> + request->msg_id = timestamp & 0xff;
>>>> Why ' & 0xff'?
>>> https://github.com/imbushuo/DFRDisplayKm/blob/master/src/DFRDisplayKm/DfrDi…
>> This is not an answer.
>> Why do you need this here? Isn't the type of msg_id enough?
> Hmm, I double checked this. msg_id is u8 in the Linux port so would anyways never exceed 0xff. I’ll remove this.
> Its different in the Windows driver.
>> ...
>>
>>>>> + adev->mode = (struct drm_display_mode) {
>>>> Why do you need a compound literal here? Perhaps you want to have that to be
>>>> done directly in DRM_MODE_INIT()?
>>> I really don’t find this as an issue. You want me to declare another structure, basically this?:
>> Nope, I'm asking if the DRM_MODE_INIT() is done in a way that it only can be
>> used for the static data. Seems like the case. Have you tried to convert
>> DRM_MODE_INIT() to be always a compound literal? Does it break things?
> Seems to be breaking things.
>>> struct drm_display_mode mode = {
>>> DRM_MODE_INIT(60, adev->height, adev->width,
>>> DRM_MODE_RES_MM(adev->height, 218),
>>> DRM_MODE_RES_MM(adev->width, 218))
>>> };
>>> adev->mode = mode;
>>>
>>>>> + DRM_MODE_INIT(60, adev->height, adev->width,
>>>>> + DRM_MODE_RES_MM(adev->height, 218),
>>>>> + DRM_MODE_RES_MM(adev->width, 218))
>>>>> + };
>> --
>> With Best Regards,
>> Andy Shevchenko
>>
>>
--
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)
11 months, 3 weeks
- 1
- 0
Re: [RFC PATCH 0/5] drm/panthor: Protected mode support for Mali CSF GPUs
by Maxime Ripard
On Tue, Feb 11, 2025 at 03:32:23PM +0100, Boris Brezillon wrote:
> On Tue, 11 Feb 2025 14:46:56 +0100
> Maxime Ripard <mripard(a)kernel.org> wrote:
>
> > Hi Boris,
> >
> > On Fri, Feb 07, 2025 at 04:02:53PM +0100, Boris Brezillon wrote:
> > > Sorry for joining the party late, a couple of comments to back Akash
> > > and Nicolas' concerns.
> > >
> > > On Wed, 05 Feb 2025 13:14:14 -0500
> > > Nicolas Dufresne <nicolas(a)ndufresne.ca> wrote:
> > >
> > > > Le mercredi 05 février 2025 à 15:52 +0100, Maxime Ripard a écrit :
> > > > > On Mon, Feb 03, 2025 at 04:43:23PM +0000, Florent Tomasin wrote:
> > > > > > Hi Maxime, Nicolas
> > > > > >
> > > > > > On 30/01/2025 17:47, Nicolas Dufresne wrote:
> > > > > > > Le jeudi 30 janvier 2025 à 17:38 +0100, Maxime Ripard a écrit :
> > > > > > > > Hi Nicolas,
> > > > > > > >
> > > > > > > > On Thu, Jan 30, 2025 at 10:59:56AM -0500, Nicolas Dufresne wrote:
> > > > > > > > > Le jeudi 30 janvier 2025 à 14:46 +0100, Maxime Ripard a écrit :
> > > > > > > > > > Hi,
> > > > > > > > > >
> > > > > > > > > > I started to review it, but it's probably best to discuss it here.
> > > > > > > > > >
> > > > > > > > > > On Thu, Jan 30, 2025 at 01:08:56PM +0000, Florent Tomasin wrote:
> > > > > > > > > > > Hi,
> > > > > > > > > > >
> > > > > > > > > > > This is a patch series covering the support for protected mode execution in
> > > > > > > > > > > Mali Panthor CSF kernel driver.
> > > > > > > > > > >
> > > > > > > > > > > The Mali CSF GPUs come with the support for protected mode execution at the
> > > > > > > > > > > HW level. This feature requires two main changes in the kernel driver:
> > > > > > > > > > >
> > > > > > > > > > > 1) Configure the GPU with a protected buffer. The system must provide a DMA
> > > > > > > > > > > heap from which the driver can allocate a protected buffer.
> > > > > > > > > > > It can be a carved-out memory or dynamically allocated protected memory region.
> > > > > > > > > > > Some system includes a trusted FW which is in charge of the protected memory.
> > > > > > > > > > > Since this problem is integration specific, the Mali Panthor CSF kernel
> > > > > > > > > > > driver must import the protected memory from a device specific exporter.
> > > > > > > > > >
> > > > > > > > > > Why do you need a heap for it in the first place? My understanding of
> > > > > > > > > > your series is that you have a carved out memory region somewhere, and
> > > > > > > > > > you want to allocate from that carved out memory region your buffers.
> > > > > > > > > >
> > > > > > > > > > How is that any different from using a reserved-memory region, adding
> > > > > > > > > > the reserved-memory property to the GPU device and doing all your
> > > > > > > > > > allocation through the usual dma_alloc_* API?
> > > > > > > > >
> > > > > > > > > How do you then multiplex this region so it can be shared between
> > > > > > > > > GPU/Camera/Display/Codec drivers and also userspace ?
> > > > > > > >
> > > > > > > > You could point all the devices to the same reserved memory region, and
> > > > > > > > they would all allocate from there, including for their userspace-facing
> > > > > > > > allocations.
> > > > > > >
> > > > > > > I get that using memory region is somewhat more of an HW description, and
> > > > > > > aligned with what a DT is supposed to describe. One of the challenge is that
> > > > > > > Mediatek heap proposal endup calling into their TEE, meaning knowing the region
> > > > > > > is not that useful. You actually need the TEE APP guid and its IPC protocol. If
> > > > > > > we can dell drivers to use a head instead, we can abstract that SoC specific
> > > > > > > complexity. I believe each allocated addressed has to be mapped to a zone, and
> > > > > > > that can only be done in the secure application. I can imagine similar needs
> > > > > > > when the protection is done using some sort of a VM / hypervisor.
> > > > > > >
> > > > > > > Nicolas
> > > > > > >
> > > > > >
> > > > > > The idea in this design is to abstract the heap management from the
> > > > > > Panthor kernel driver (which consumes a DMA buffer from it).
> > > > > >
> > > > > > In a system, an integrator would have implemented a secure heap driver,
> > > > > > and could be based on TEE or a carved-out memory with restricted access,
> > > > > > or else. This heap driver would be responsible of implementing the
> > > > > > logic to: allocate, free, refcount, etc.
> > > > > >
> > > > > > The heap would be retrieved by the Panthor kernel driver in order to
> > > > > > allocate protected memory to load the FW and allow the GPU to enter/exit
> > > > > > protected mode. This memory would not belong to a user space process.
> > > > > > The driver allocates it at the time of loading the FW and initialization
> > > > > > of the GPU HW. This is a device globally owned protected memory.
> > > > >
> > > > > The thing is, it's really not clear why you absolutely need to have the
> > > > > Panthor driver involved there. It won't be transparent to userspace,
> > > > > since you'd need an extra flag at allocation time, and the buffers
> > > > > behave differently. If userspace has to be aware of it, what's the
> > > > > advantage to your approach compared to just exposing a heap for those
> > > > > secure buffers, and letting userspace allocate its buffers from there?
> > > >
> > > > Unless I'm mistaken, the Panthor driver loads its own firmware. Since loading
> > > > the firmware requires placing the data in a protected memory region, and that
> > > > this aspect has no exposure to userspace, how can Panthor not be implicated ?
> > >
> > > Right, the very reason we need protected memory early is because some
> > > FW sections need to be allocated from the protected pool, otherwise the
> > > TEE will fault as soon at the FW enters the so-called 'protected mode'.
> >
> > How does that work if you don't have some way to allocate the protected
> > memory? You can still submit jobs to the GPU, but you can't submit /
> > execute "protected jobs"?
>
> Exactly.
>
> >
> > > Now, it's not impossible to work around this limitation. For instance,
> > > we could load the FW without this protected section by default (what we
> > > do right now), and then provide a DRM_PANTHOR_ENABLE_FW_PROT_MODE
> > > ioctl that would take a GEM object imported from a dmabuf allocated
> > > from the protected dma-heap by userspace. We can then reset the FW and
> > > allow it to operate in protected mode after that point.
> >
> > Urgh, I'd rather avoid that dance if possible :)
>
> Me too.
>
> >
> > > This approach has two downsides though:
> > >
> > > 1. We have no way of checking that the memory we're passed is actually
> > > suitable for FW execution in a protected context. If we're passed
> > > random memory, this will likely hang the platform as soon as we enter
> > > protected mode.
> >
> > It's a current limitation of dma-buf in general, and you'd have the same
> > issue right now if someone imports a buffer, or misconfigure the heap
> > for a !protected heap.
> >
> > I'd really like to have some way to store some metadata in dma_buf, if
> > only to tell that the buffer is protected.
>
> The dma_buf has a pointer to its ops, so it should be relatively easy
> to add an is_dma_buf_coming_from_this_heap() helper. Of course this
> implies linking the consumer driver to the heap it's supposed to take
> protected buffers from, which is basically the thing being discussed
> here :-).
I'm not sure looking at the ops would be enough. Like, you can compare
that the buffer you allocated come from the heap you got from the DT,
but if that heap doesn't allocate protected buffers, you're screwed and
you have no way to tell.
It also falls apart if we have a heap driver with multiple instances,
which is pretty likely if we ever merge the carveout heap driver.
> >
> > I suspect you'd also need that if you do things like do protected video
> > playback through a codec, get a protected frame, and want to import that
> > into the GPU. Depending on how you allocate it, either the codec or the
> > GPU or both will want to make sure it's protected.
>
> If it's all allocated from a central "protected" heap (even if that
> goes through the driver calling the dma_heap_alloc_buffer()), it
> shouldn't be an issue.
Right, assuming we have a way to identify the heap the buffer was
allocated from somehow. This kind of assumes that you only ever get one
source of protected memory, and you'd never allocate a protected buffer
from a different one in the codec driver for example.
> > > 2. If the driver already boot the FW and exposed a DRI node, we might
> > > have GPU workloads running, and doing a FW reset might incur a slight
> > > delay in GPU jobs execution.
> > >
> > > I think #1 is a more general issue that applies to suspend buffers
> > > allocated for GPU contexts too. If we expose ioctls where we take
> > > protected memory buffers that can possibly lead to crashes if they are
> > > not real protected memory regions, and we have no way to ensure the
> > > memory is protected, we probably want to restrict these ioctls/modes to
> > > some high-privilege CAP_SYS_.
> > >
> > > For #2, that's probably something we can live with, since it's a
> > > one-shot thing. If it becomes an issue, we can even make sure we enable
> > > the FW protected-mode before the GPU starts being used for real.
> > >
> > > This being said, I think the problem applies outside Panthor, and it
> > > might be that the video codec can't reset the FW/HW block to switch to
> > > protected mode as easily as Panthor.
> > >
> > > Note that there's also downsides to the reserved-memory node approach,
> > > where some bootloader stage would ask the secure FW to reserve a
> > > portion of mem and pass this through the DT. This sort of things tend to
> > > be an integration mess, where you need all the pieces of the stack (TEE,
> > > u-boot, MTK dma-heap driver, gbm, ...) to be at a certain version to
> > > work properly. If we go the ioctl() way, we restrict the scope to the
> > > TEE, gbm/mesa and the protected-dma-heap driver, which is still a lot,
> > > but we've ripped the bootloader out of the equation at least.
> >
> > Yeah. I also think there's two discussions in parallel here:
> >
> > 1) Being able to allocate protected buffers from the driver
> > 2) Exposing an interface to allocate those to userspace
> >
> > I'm not really convinced we need 2, but 1 is obviously needed from what
> > you're saying.
>
> I suspect we need #2 for GBM, still. But that's what dma-heaps are for,
> so I don't think that's a problem.
Yeah, that was my point too, we have the heaps for that already.
Maxime
11 months, 4 weeks
- 1
- 0
[PATCH v5 0/7] TEE subsystem for restricted dma-buf allocations
by Jens Wiklander
Hi,
[Now with a Gstreamer demo, see below.]
This patch set allocates the restricted DMA-bufs via the TEE subsystem.
The TEE subsystem handles the DMA-buf allocations since it is the TEE
(OP-TEE, AMD-TEE, TS-TEE, or perhaps a future QCOMTEE) which sets up the
restrictions for the memory used for the DMA-bufs.
I've added a new IOCTL, TEE_IOC_RSTMEM_ALLOC, to allocate the restricted
DMA-bufs. This IOCTL reaches the backend TEE driver, allowing it to choose
how to allocate the restricted physical memory.
TEE_IOC_RSTMEM_ALLOC takes in addition to a size and flags parameters also
a use-case parameter. This is used by the backend TEE driver to decide on
allocation policy and which devices should be able to access the memory.
Three use-cases (Secure Video Playback, Trusted UI, and Secure Video
Recording) has been identified so far to serve as examples of what can be
expected. More use-cases can be added in userspace ABI, but it's up to the
backend TEE drivers to provide the implementation.
Each use-case has it's own restricted memory pool since different use-cases
requires isolation from different parts of the system. A restricted memory
pool can be based on a static carveout instantiated while probing the TEE
backend driver, or dynamically allocated from CMA and made restricted as
needed by the TEE.
This can be tested on a RockPi 4B+ with the following steps:
repo init -u https://github.com/jenswi-linaro/manifest.git -m rockpi4.xml \
-b prototype/sdp-v5
repo sync -j8
cd build
make toolchains -j$(nproc)
make all -j$(nproc)
# Copy ../out/rockpi4.img to an SD card and boot the RockPi from that
# Connect a monitor to the RockPi
# login and at the prompt:
gst-launch-1.0 videotestsrc ! \
aesenc key=1f9423681beb9a79215820f6bda73d0f \
iv=e9aa8e834d8d70b7e0d254ff670dd718 serialize-iv=true ! \
aesdec key=1f9423681beb9a79215820f6bda73d0f ! \
kmssink
The aesdec module has been hacked to use an OP-TEE TA to decrypt the stream
into restricted DMA-bufs which are consumed by the kmssink.
The primitive QEMU tests from previous patch set can be tested on RockPi
in the same way with:
xtest --sdp-basic
The primitive test are tested on QEMU with the following steps:
repo init -u https://github.com/jenswi-linaro/manifest.git -m qemu_v8.xml \
-b prototype/sdp-v5
repo sync -j8
cd build
make toolchains -j$(nproc)
make SPMC_AT_EL=1 all -j$(nproc)
make SPMC_AT_EL=1 run-only
# login and at the prompt:
xtest --sdp-basic
The SPMC_AT_EL=1 parameter configures the build with FF-A and an SPMC at
S-EL1 inside OP-TEE. The parameter can be changed into SPMC_AT_EL=n to test
without FF-A using the original SMC ABI instead. Please remember to do
%rm -rf ../trusted-firmware-a/build/qemu
for TF-A to be rebuilt properly using the new configuration.
https://optee.readthedocs.io/en/latest/building/prerequisites.html
list dependencies needed to build the above.
The tests are pretty basic, mostly checking that a Trusted Application in
the secure world can access and manipulate the memory. There are also some
negative tests for out of bounds buffers etc.
Thanks,
Jens
Changes since V4:
* Adding the patch "tee: add TEE_IOC_RSTMEM_FD_INFO" needed by the
GStreamer demo
* Removing the dummy CPU access and mmap functions from the dma_buf_ops
* Fixing a compile error in "optee: FF-A: dynamic restricted memory allocation"
reported by kernel test robot <lkp(a)intel.com>
Changes since V3:
* Make the use_case and flags field in struct tee_shm u32's instead of
u16's
* Add more description for TEE_IOC_RSTMEM_ALLOC in the header file
* Import namespace DMA_BUF in module tee, reported by lkp(a)intel.com
* Added a note in the commit message for "optee: account for direction
while converting parameters" why it's needed
* Factor out dynamic restricted memory allocation from
"optee: support restricted memory allocation" into two new commits
"optee: FF-A: dynamic restricted memory allocation" and
"optee: smc abi: dynamic restricted memory allocation"
* Guard CMA usage with #ifdef CONFIG_CMA, effectively disabling dynamic
restricted memory allocate if CMA isn't configured
Changes since the V2 RFC:
* Based on v6.12
* Replaced the flags for SVP and Trusted UID memory with a u32 field with
unique id for each use case
* Added dynamic allocation of restricted memory pools
* Added OP-TEE ABI both with and without FF-A for dynamic restricted memory
* Added support for FF-A with FFA_LEND
Changes since the V1 RFC:
* Based on v6.11
* Complete rewrite, replacing the restricted heap with TEE_IOC_RSTMEM_ALLOC
Changes since Olivier's post [2]:
* Based on Yong Wu's post [1] where much of dma-buf handling is done in
the generic restricted heap
* Simplifications and cleanup
* New commit message for "dma-buf: heaps: add Linaro restricted dmabuf heap
support"
* Replaced the word "secure" with "restricted" where applicable
Jens Wiklander (7):
tee: add restricted memory allocation
tee: add TEE_IOC_RSTMEM_FD_INFO
optee: account for direction while converting parameters
optee: sync secure world ABI headers
optee: support restricted memory allocation
optee: FF-A: dynamic restricted memory allocation
optee: smc abi: dynamic restricted memory allocation
drivers/tee/Makefile | 1 +
drivers/tee/optee/Makefile | 1 +
drivers/tee/optee/call.c | 10 +-
drivers/tee/optee/core.c | 1 +
drivers/tee/optee/ffa_abi.c | 179 +++++++++++++-
drivers/tee/optee/optee_ffa.h | 27 ++-
drivers/tee/optee/optee_msg.h | 65 ++++-
drivers/tee/optee/optee_private.h | 75 ++++--
drivers/tee/optee/optee_smc.h | 71 +++++-
drivers/tee/optee/rpc.c | 31 ++-
drivers/tee/optee/rstmem.c | 389 ++++++++++++++++++++++++++++++
drivers/tee/optee/smc_abi.c | 215 +++++++++++++++--
drivers/tee/tee_core.c | 69 +++++-
drivers/tee/tee_private.h | 4 +
drivers/tee/tee_rstmem.c | 188 +++++++++++++++
drivers/tee/tee_shm.c | 2 +
drivers/tee/tee_shm_pool.c | 69 +++++-
include/linux/tee_core.h | 15 ++
include/linux/tee_drv.h | 2 +
include/uapi/linux/tee.h | 71 +++++-
20 files changed, 1409 insertions(+), 76 deletions(-)
create mode 100644 drivers/tee/optee/rstmem.c
create mode 100644 drivers/tee/tee_rstmem.c
base-commit: a64dcfb451e254085a7daee5fe51bf22959d52d3
--
2.43.0
12 months
- 2
- 8
Re: [PATCH 4/4] dma-buf: drop caching of sg_tables
by Christian König
Am 17.02.25 um 17:28 schrieb Simona Vetter:
> On Tue, Feb 11, 2025 at 05:31:09PM +0100, Christian König wrote:
>> That was purely for the transition from static to dynamic dma-buf
>> handling and can be removed again now.
>>
>> Signed-off-by: Christian König <christian.koenig(a)amd.com>
> Yay!
>
> Might uncover some fun if people have meanwhile started to rely on this
> for perf or something. But we'll figure that out when it happens.
Yeah that was exactly the reason why I made this a separate patch and didn't mixed it into patch #3.
On the other hand I'm fine to keep it a bit longer if anybody complains.
Christian.
>
> Reviewed-by: Simona Vetter <simona.vetter(a)ffwll.ch>
>
>
>> ---
>> drivers/dma-buf/dma-buf.c | 34 --------------------------
>> drivers/dma-buf/udmabuf.c | 1 -
>> drivers/gpu/drm/drm_prime.c | 1 -
>> drivers/gpu/drm/virtio/virtgpu_prime.c | 1 -
>> include/linux/dma-buf.h | 13 ----------
>> 5 files changed, 50 deletions(-)
>>
>> diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c
>> index 357b94a3dbaa..35221c4ddbf5 100644
>> --- a/drivers/dma-buf/dma-buf.c
>> +++ b/drivers/dma-buf/dma-buf.c
>> @@ -636,10 +636,6 @@ struct dma_buf *dma_buf_export(const struct dma_buf_export_info *exp_info)
>> || !exp_info->ops->release))
>> return ERR_PTR(-EINVAL);
>>
>> - if (WARN_ON(exp_info->ops->cache_sgt_mapping &&
>> - (exp_info->ops->pin || exp_info->ops->unpin)))
>> - return ERR_PTR(-EINVAL);
>> -
>> if (WARN_ON(!exp_info->ops->pin != !exp_info->ops->unpin))
>> return ERR_PTR(-EINVAL);
>>
>> @@ -964,17 +960,7 @@ void dma_buf_detach(struct dma_buf *dmabuf, struct dma_buf_attachment *attach)
>> return;
>>
>> dma_resv_lock(dmabuf->resv, NULL);
>> -
>> - if (attach->sgt) {
>> - mangle_sg_table(attach->sgt);
>> - attach->dmabuf->ops->unmap_dma_buf(attach, attach->sgt,
>> - attach->dir);
>> -
>> - if (dma_buf_pin_on_map(attach))
>> - dma_buf_unpin(attach);
>> - }
>> list_del(&attach->node);
>> -
>> dma_resv_unlock(dmabuf->resv);
>>
>> if (dmabuf->ops->detach)
>> @@ -1069,18 +1055,6 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach,
>>
>> dma_resv_assert_held(attach->dmabuf->resv);
>>
>> - if (attach->sgt) {
>> - /*
>> - * Two mappings with different directions for the same
>> - * attachment are not allowed.
>> - */
>> - if (attach->dir != direction &&
>> - attach->dir != DMA_BIDIRECTIONAL)
>> - return ERR_PTR(-EBUSY);
>> -
>> - return attach->sgt;
>> - }
>> -
>> if (dma_buf_pin_on_map(attach)) {
>> ret = attach->dmabuf->ops->pin(attach);
>> if (ret)
>> @@ -1105,11 +1079,6 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach,
>> }
>> mangle_sg_table(sg_table);
>>
>> - if (attach->dmabuf->ops->cache_sgt_mapping) {
>> - attach->sgt = sg_table;
>> - attach->dir = direction;
>> - }
>> -
>> #ifdef CONFIG_DMA_API_DEBUG
>> {
>> struct scatterlist *sg;
>> @@ -1190,9 +1159,6 @@ void dma_buf_unmap_attachment(struct dma_buf_attachment *attach,
>>
>> dma_resv_assert_held(attach->dmabuf->resv);
>>
>> - if (attach->sgt == sg_table)
>> - return;
>> -
>> mangle_sg_table(sg_table);
>> attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction);
>>
>> diff --git a/drivers/dma-buf/udmabuf.c b/drivers/dma-buf/udmabuf.c
>> index cc7398cc17d6..2fa2c9135eac 100644
>> --- a/drivers/dma-buf/udmabuf.c
>> +++ b/drivers/dma-buf/udmabuf.c
>> @@ -285,7 +285,6 @@ static int end_cpu_udmabuf(struct dma_buf *buf,
>> }
>>
>> static const struct dma_buf_ops udmabuf_ops = {
>> - .cache_sgt_mapping = true,
>> .map_dma_buf = map_udmabuf,
>> .unmap_dma_buf = unmap_udmabuf,
>> .release = release_udmabuf,
>> diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
>> index 32a8781cfd67..c284f306d597 100644
>> --- a/drivers/gpu/drm/drm_prime.c
>> +++ b/drivers/gpu/drm/drm_prime.c
>> @@ -810,7 +810,6 @@ int drm_gem_dmabuf_mmap(struct dma_buf *dma_buf, struct vm_area_struct *vma)
>> EXPORT_SYMBOL(drm_gem_dmabuf_mmap);
>>
>> static const struct dma_buf_ops drm_gem_prime_dmabuf_ops = {
>> - .cache_sgt_mapping = true,
>> .attach = drm_gem_map_attach,
>> .detach = drm_gem_map_detach,
>> .map_dma_buf = drm_gem_map_dma_buf,
>> diff --git a/drivers/gpu/drm/virtio/virtgpu_prime.c b/drivers/gpu/drm/virtio/virtgpu_prime.c
>> index fe6a0b018571..c6f3be3cb914 100644
>> --- a/drivers/gpu/drm/virtio/virtgpu_prime.c
>> +++ b/drivers/gpu/drm/virtio/virtgpu_prime.c
>> @@ -75,7 +75,6 @@ static void virtgpu_gem_unmap_dma_buf(struct dma_buf_attachment *attach,
>>
>> static const struct virtio_dma_buf_ops virtgpu_dmabuf_ops = {
>> .ops = {
>> - .cache_sgt_mapping = true,
>> .attach = virtio_dma_buf_attach,
>> .detach = drm_gem_map_detach,
>> .map_dma_buf = virtgpu_gem_map_dma_buf,
>> diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h
>> index c54ff2dda8cb..544f8f8c3f44 100644
>> --- a/include/linux/dma-buf.h
>> +++ b/include/linux/dma-buf.h
>> @@ -34,15 +34,6 @@ struct dma_buf_attachment;
>> * @vunmap: [optional] unmaps a vmap from the buffer
>> */
>> struct dma_buf_ops {
>> - /**
>> - * @cache_sgt_mapping:
>> - *
>> - * If true the framework will cache the first mapping made for each
>> - * attachment. This avoids creating mappings for attachments multiple
>> - * times.
>> - */
>> - bool cache_sgt_mapping;
>> -
>> /**
>> * @attach:
>> *
>> @@ -493,8 +484,6 @@ struct dma_buf_attach_ops {
>> * @dmabuf: buffer for this attachment.
>> * @dev: device attached to the buffer.
>> * @node: list of dma_buf_attachment, protected by dma_resv lock of the dmabuf.
>> - * @sgt: cached mapping.
>> - * @dir: direction of cached mapping.
>> * @peer2peer: true if the importer can handle peer resources without pages.
>> * @priv: exporter specific attachment data.
>> * @importer_ops: importer operations for this attachment, if provided
>> @@ -514,8 +503,6 @@ struct dma_buf_attachment {
>> struct dma_buf *dmabuf;
>> struct device *dev;
>> struct list_head node;
>> - struct sg_table *sgt;
>> - enum dma_data_direction dir;
>> bool peer2peer;
>> const struct dma_buf_attach_ops *importer_ops;
>> void *importer_priv;
>> --
>> 2.34.1
>>
12 months
- 1
- 0
Bunch of DMA-buf cleanup patches
by Christian König
Hello everyone,
just a few DMA-buf cleanup patches. The first one is fixing an incorrect
documentation which has annoyed me for quite a while.
The rest basically just removes stuff we no longer need or which was
just added as abstraction which was never used.
Please review and/or voice objection if some of that is till needed for
something.
Regards,
Christian.
12 months
- 2
- 9
Re: [PATCH v4 0/6] TEE subsystem for restricted dma-buf allocations
by Daniel Stone
Hi,
On Thu, 13 Feb 2025 at 12:40, Boris Brezillon
<boris.brezillon(a)collabora.com> wrote:
> On Thu, 13 Feb 2025 14:46:01 +0530 Sumit Garg <sumit.garg(a)linaro.org> wrote:
> > Yeah but all the prior vendor specific secure/restricted DMA heaps
> > relied on DT information.
>
> Right, but there's nothing in the DMA heap provider API forcing that.
Yeah. DMA heaps are just a way to allocate memory from a specific
place. It allows people to settle on having a single way to do
allocations from weird platform-specific places; the only weird
platform-specific part userspace needs to deal with is figuring out
the name to use. The rest is at least a unified API: the point of
dma-heaps was exactly to have a single coherent API for userspace, not
to create one API for ZONE_CMA and DT ranges and everyone else doing
their own thing.
> > Rather than that it's better
> > for the user to directly ask the TEE device to allocate restricted
> > memory without worrying about how the memory restriction gets
> > enforced.
>
> If the consensus is that restricted/protected memory allocation should
> always be routed to the TEE, sure, but I had the feeling this wasn't as
> clear as that. OTOH, using a dma-heap to expose the TEE-SDP
> implementation provides the same benefits, without making potential
> future non-TEE based implementations a pain for users. The dma-heap
> ioctl being common to all implementations, it just becomes a
> configuration matter if we want to change the heap we rely on for
> protected/restricted buffer allocation. And because heaps have
> unique/well-known names, users can still default to (or rely solely on)
> the TEE-SPD implementation if they want.
>
> > There have been several attempts with DMA heaps in the past which all
> > resulted in a very vendor specific vertically integrated solution. But
> > the solution with TEE subsystem aims to make it generic and vendor
> > agnostic.
>
> Just because all previous protected/restricted dma-heap effort
> failed to make it upstream, doesn't mean dma-heap is the wrong way of
> exposing this feature IMHO.
To be fair, having a TEE implementation does give us a much better
chance of having a sensible cross-vendor plan. And the fact it's
already (sort of accidentally and only on one platform AFAICT) ready
for a 'test' interface, where we can still exercise protected
allocation paths but without having to go through all the
platform-specific setup that is inaccessible to most people, is also
really great! That's probably been the biggest barrier to having this
tested outside of IHVs and OEMs.
But just because TEE is one good backend implementation, doesn't mean
it should be the userspace ABI. Why should userspace care that TEE has
mediated the allocation instead of it being a predefined range within
DT? How does userspace pick which TEE device to use? What advantage
does userspace get from having to have a different codepath to get a
different handle to memory? What about x86?
I think this proposal is looking at it from the wrong direction.
Instead of working upwards from the implementation to userspace, start
with userspace and work downwards. The interesting property to focus
on is allocating memory, not that EL1 is involved behind the scenes.
Cheers,
Daniel
1 year
- 3
- 4
Re: [PATCH v4 0/6] TEE subsystem for restricted dma-buf allocations
by Sumit Garg
On Thu, 13 Feb 2025 at 14:06, Boris Brezillon
<boris.brezillon(a)collabora.com> wrote:
>
> On Thu, 13 Feb 2025 12:11:52 +0530
> Sumit Garg <sumit.garg(a)linaro.org> wrote:
>
> > Hi Boris,
> >
> > On Thu, 13 Feb 2025 at 01:26, Boris Brezillon
> > <boris.brezillon(a)collabora.com> wrote:
> > >
> > > +Florent, who's working on protected-mode support in Panthor.
> > >
> > > Hi Jens,
> > >
> > > On Tue, 17 Dec 2024 11:07:36 +0100
> > > Jens Wiklander <jens.wiklander(a)linaro.org> wrote:
> > >
> > > > Hi,
> > > >
> > > > This patch set allocates the restricted DMA-bufs via the TEE subsystem.
> > >
> > > We're currently working on protected-mode support for Panthor [1] and it
> > > looks like your series (and the OP-TEE implementation that goes with
> > > it) would allow us to have a fully upstream/open solution for the
> > > protected content use case we're trying to support. I need a bit more
> > > time to play with the implementation but this looks very promising
> > > (especially the lend rstmem feature, which might help us allocate our
> > > FW sections that are supposed to execute code accessing protected
> > > content).
> >
> > Glad to hear that, if you can demonstrate an open source use case
> > based on this series then it will help to land it. We really would
> > love to see support for restricted DMA-buf consumers be it GPU, crypto
> > accelerator, media pipeline etc.
> >
> > >
> > > >
> > > > The TEE subsystem handles the DMA-buf allocations since it is the TEE
> > > > (OP-TEE, AMD-TEE, TS-TEE, or perhaps a future QCOMTEE) which sets up the
> > > > restrictions for the memory used for the DMA-bufs.
> > > >
> > > > I've added a new IOCTL, TEE_IOC_RSTMEM_ALLOC, to allocate the restricted
> > > > DMA-bufs. This IOCTL reaches the backend TEE driver, allowing it to choose
> > > > how to allocate the restricted physical memory.
> > >
> > > I'll probably have more questions soon, but here's one to start: any
> > > particular reason you didn't go for a dma-heap to expose restricted
> > > buffer allocation to userspace? I see you already have a cdev you can
> > > take ioctl()s from, but my understanding was that dma-heap was the
> > > standard solution for these device-agnostic/central allocators.
> >
> > This series started with the DMA heap approach only here [1] but later
> > discussions [2] lead us here. To point out specifically:
> >
> > - DMA heaps require reliance on DT to discover static restricted
> > regions carve-outs whereas via the TEE implementation driver (eg.
> > OP-TEE) those can be discovered dynamically.
>
> Hm, the system heap [1] doesn't rely on any DT information AFAICT.
Yeah but all the prior vendor specific secure/restricted DMA heaps
relied on DT information.
> The dynamic allocation scheme, where the TEE implementation allocates a
> chunk of protected memory for us would have a similar behavior, I guess.
In a dynamic scheme, the allocation will still be from CMA or system
heap depending on TEE implementation capabilities but the restriction
will be enforced via interaction with TEE.
>
> > - Dynamic allocation of buffers and making them restricted requires
> > vendor specific driver hooks with DMA heaps whereas the TEE subsystem
> > abstracts that out with underlying TEE implementation (eg. OP-TEE)
> > managing the dynamic buffer restriction.
>
> Yeah, the lend rstmem feature is clearly something tee specific, and I
> think that's okay to assume the user knows the protection request
> should go through the tee subsystem in that case.
Yeah but how will the user discover that? Rather than that it's better
for the user to directly ask the TEE device to allocate restricted
memory without worrying about how the memory restriction gets
enforced.
>
> > - TEE subsystem already has a well defined user-space interface for
> > managing shared memory buffers with TEE and restricted DMA buffers
> > will be yet another interface managed along similar lines.
>
> Okay, so the very reason I'm asking about the dma-buf heap interface is
> because there might be cases where the protected/restricted allocation
> doesn't go through the TEE (Mediatek has a TEE-free implementation
> for instance, but I realize vendor implementations are probably not the
> best selling point :-/).
You can always have a system with memory and peripheral access
permissions setup during boot (or even have a pre-configured hardware
as a special case) prior to booting up the kernel too. But that even
gets somehow configured by a TEE implementation during boot, so
calling it a TEE-free implementation seems over-simplified and not a
scalable solution. However, this patchset [1] from Mediatek requires
runtime TEE interaction too.
[1] https://lore.kernel.org/linux-arm-kernel/20240515112308.10171-1-yong.wu@med…
> If we expose things as a dma-heap, we have
> a solution where integrators can pick the dma-heap they think is
> relevant for protected buffer allocations without the various drivers
> (GPU, video codec, ...) having to implement a dispatch function for all
> possible implementations. The same goes for userspace allocations,
> where passing a dma-heap name, is simpler than supporting different
> ioctl()s based on the allocation backend.
There have been several attempts with DMA heaps in the past which all
resulted in a very vendor specific vertically integrated solution. But
the solution with TEE subsystem aims to make it generic and vendor
agnostic.
>
> [1]https://elixir.bootlin.com/linux/v6.13.2/source/drivers/dma-buf/heaps/sys…
-Sumit
1 year
- 1
- 0
Re: [PATCH v4 0/6] TEE subsystem for restricted dma-buf allocations
by Sumit Garg
Hi Boris,
On Thu, 13 Feb 2025 at 01:26, Boris Brezillon
<boris.brezillon(a)collabora.com> wrote:
>
> +Florent, who's working on protected-mode support in Panthor.
>
> Hi Jens,
>
> On Tue, 17 Dec 2024 11:07:36 +0100
> Jens Wiklander <jens.wiklander(a)linaro.org> wrote:
>
> > Hi,
> >
> > This patch set allocates the restricted DMA-bufs via the TEE subsystem.
>
> We're currently working on protected-mode support for Panthor [1] and it
> looks like your series (and the OP-TEE implementation that goes with
> it) would allow us to have a fully upstream/open solution for the
> protected content use case we're trying to support. I need a bit more
> time to play with the implementation but this looks very promising
> (especially the lend rstmem feature, which might help us allocate our
> FW sections that are supposed to execute code accessing protected
> content).
Glad to hear that, if you can demonstrate an open source use case
based on this series then it will help to land it. We really would
love to see support for restricted DMA-buf consumers be it GPU, crypto
accelerator, media pipeline etc.
>
> >
> > The TEE subsystem handles the DMA-buf allocations since it is the TEE
> > (OP-TEE, AMD-TEE, TS-TEE, or perhaps a future QCOMTEE) which sets up the
> > restrictions for the memory used for the DMA-bufs.
> >
> > I've added a new IOCTL, TEE_IOC_RSTMEM_ALLOC, to allocate the restricted
> > DMA-bufs. This IOCTL reaches the backend TEE driver, allowing it to choose
> > how to allocate the restricted physical memory.
>
> I'll probably have more questions soon, but here's one to start: any
> particular reason you didn't go for a dma-heap to expose restricted
> buffer allocation to userspace? I see you already have a cdev you can
> take ioctl()s from, but my understanding was that dma-heap was the
> standard solution for these device-agnostic/central allocators.
This series started with the DMA heap approach only here [1] but later
discussions [2] lead us here. To point out specifically:
- DMA heaps require reliance on DT to discover static restricted
regions carve-outs whereas via the TEE implementation driver (eg.
OP-TEE) those can be discovered dynamically.
- Dynamic allocation of buffers and making them restricted requires
vendor specific driver hooks with DMA heaps whereas the TEE subsystem
abstracts that out with underlying TEE implementation (eg. OP-TEE)
managing the dynamic buffer restriction.
- TEE subsystem already has a well defined user-space interface for
managing shared memory buffers with TEE and restricted DMA buffers
will be yet another interface managed along similar lines.
[1] https://lore.kernel.org/lkml/mzur3odofwwrdqnystozjgf3qtvb73wqjm6g2vf5dfsqie…
[2] https://lore.kernel.org/lkml/CAFA6WYPtp3H5JhxzgH9=z2EvNL7Kdku3EmG1aDkTS-gjF…
-Sumit
>
> Regards,
>
> Boris
>
> [1]https://lwn.net/ml/all/cover.1738228114.git.florent.tomasin@arm.com/#t
1 year
- 2
- 1
Re: [RFC PATCH 1/5] dt-bindings: dma: Add CMA Heap bindings
by Maxime Ripard
On Wed, Feb 12, 2025 at 10:29:32AM +0000, Florent Tomasin wrote:
>
>
> On 12/02/2025 10:01, Maxime Ripard wrote:
> > On Wed, Feb 12, 2025 at 09:49:56AM +0000, Florent Tomasin wrote:
> >> Note that the CMA patches were initially shared to help reproduce my
> >> environment of development, I can isolate them in a separate patch
> >> series and include a reference or "base-commit:" tag to it in the
> >> Panthor protected mode RFC, to help progress this review in another
> >> thread. It will avoid overlapping these two topics:
> >>
> >> - Multiple standalone CMA heaps support
> >> - Panthor protected mode handling
> >
> > You keep insisting on using CMA here, but it's really not clear to me
> > why you would need CMA in the first place.
> >
> > By CMA, do you mean the CMA allocator, and thus would provide buffers
> > through the usual dma_alloc_* API, or would any allocator providing
> > physically contiguous memory work?
>
> You are correct only the CMA allocator is relevant. I needed a way to
> sub-allocate from a carved-out memory.
I'm still confused, sorry. You're saying that you require CMA but...
> > In the latter case, would something like this work:
> > https://lore.kernel.org/all/20240515-dma-buf-ecc-heap-v1-1-54cbbd049511@ker…
>
> Thanks for sharing this link, I was not aware previous work was done
> on this aspect. The new carveout heap introduced in the series could
> probably be a good alternative. I will play-around with it and share
> some updates.
... you seem to be ok with a driver that doesn't use it?
Maxime
1 year
- 1
- 0
Re: [RFC PATCH 1/5] dt-bindings: dma: Add CMA Heap bindings
by Maxime Ripard
On Wed, Feb 12, 2025 at 09:49:56AM +0000, Florent Tomasin wrote:
> Note that the CMA patches were initially shared to help reproduce my
> environment of development, I can isolate them in a separate patch
> series and include a reference or "base-commit:" tag to it in the
> Panthor protected mode RFC, to help progress this review in another
> thread. It will avoid overlapping these two topics:
>
> - Multiple standalone CMA heaps support
> - Panthor protected mode handling
You keep insisting on using CMA here, but it's really not clear to me
why you would need CMA in the first place.
By CMA, do you mean the CMA allocator, and thus would provide buffers
through the usual dma_alloc_* API, or would any allocator providing
physically contiguous memory work?
In the latter case, would something like this work:
https://lore.kernel.org/all/20240515-dma-buf-ecc-heap-v1-1-54cbbd049511@ker…
Maxime
1 year
- 1
- 0
Re: [RFC PATCH 0/5] drm/panthor: Protected mode support for Mali CSF GPUs
by Maxime Ripard
Hi Boris,
On Fri, Feb 07, 2025 at 04:02:53PM +0100, Boris Brezillon wrote:
> Sorry for joining the party late, a couple of comments to back Akash
> and Nicolas' concerns.
>
> On Wed, 05 Feb 2025 13:14:14 -0500
> Nicolas Dufresne <nicolas(a)ndufresne.ca> wrote:
>
> > Le mercredi 05 février 2025 à 15:52 +0100, Maxime Ripard a écrit :
> > > On Mon, Feb 03, 2025 at 04:43:23PM +0000, Florent Tomasin wrote:
> > > > Hi Maxime, Nicolas
> > > >
> > > > On 30/01/2025 17:47, Nicolas Dufresne wrote:
> > > > > Le jeudi 30 janvier 2025 à 17:38 +0100, Maxime Ripard a écrit :
> > > > > > Hi Nicolas,
> > > > > >
> > > > > > On Thu, Jan 30, 2025 at 10:59:56AM -0500, Nicolas Dufresne wrote:
> > > > > > > Le jeudi 30 janvier 2025 à 14:46 +0100, Maxime Ripard a écrit :
> > > > > > > > Hi,
> > > > > > > >
> > > > > > > > I started to review it, but it's probably best to discuss it here.
> > > > > > > >
> > > > > > > > On Thu, Jan 30, 2025 at 01:08:56PM +0000, Florent Tomasin wrote:
> > > > > > > > > Hi,
> > > > > > > > >
> > > > > > > > > This is a patch series covering the support for protected mode execution in
> > > > > > > > > Mali Panthor CSF kernel driver.
> > > > > > > > >
> > > > > > > > > The Mali CSF GPUs come with the support for protected mode execution at the
> > > > > > > > > HW level. This feature requires two main changes in the kernel driver:
> > > > > > > > >
> > > > > > > > > 1) Configure the GPU with a protected buffer. The system must provide a DMA
> > > > > > > > > heap from which the driver can allocate a protected buffer.
> > > > > > > > > It can be a carved-out memory or dynamically allocated protected memory region.
> > > > > > > > > Some system includes a trusted FW which is in charge of the protected memory.
> > > > > > > > > Since this problem is integration specific, the Mali Panthor CSF kernel
> > > > > > > > > driver must import the protected memory from a device specific exporter.
> > > > > > > >
> > > > > > > > Why do you need a heap for it in the first place? My understanding of
> > > > > > > > your series is that you have a carved out memory region somewhere, and
> > > > > > > > you want to allocate from that carved out memory region your buffers.
> > > > > > > >
> > > > > > > > How is that any different from using a reserved-memory region, adding
> > > > > > > > the reserved-memory property to the GPU device and doing all your
> > > > > > > > allocation through the usual dma_alloc_* API?
> > > > > > >
> > > > > > > How do you then multiplex this region so it can be shared between
> > > > > > > GPU/Camera/Display/Codec drivers and also userspace ?
> > > > > >
> > > > > > You could point all the devices to the same reserved memory region, and
> > > > > > they would all allocate from there, including for their userspace-facing
> > > > > > allocations.
> > > > >
> > > > > I get that using memory region is somewhat more of an HW description, and
> > > > > aligned with what a DT is supposed to describe. One of the challenge is that
> > > > > Mediatek heap proposal endup calling into their TEE, meaning knowing the region
> > > > > is not that useful. You actually need the TEE APP guid and its IPC protocol. If
> > > > > we can dell drivers to use a head instead, we can abstract that SoC specific
> > > > > complexity. I believe each allocated addressed has to be mapped to a zone, and
> > > > > that can only be done in the secure application. I can imagine similar needs
> > > > > when the protection is done using some sort of a VM / hypervisor.
> > > > >
> > > > > Nicolas
> > > > >
> > > >
> > > > The idea in this design is to abstract the heap management from the
> > > > Panthor kernel driver (which consumes a DMA buffer from it).
> > > >
> > > > In a system, an integrator would have implemented a secure heap driver,
> > > > and could be based on TEE or a carved-out memory with restricted access,
> > > > or else. This heap driver would be responsible of implementing the
> > > > logic to: allocate, free, refcount, etc.
> > > >
> > > > The heap would be retrieved by the Panthor kernel driver in order to
> > > > allocate protected memory to load the FW and allow the GPU to enter/exit
> > > > protected mode. This memory would not belong to a user space process.
> > > > The driver allocates it at the time of loading the FW and initialization
> > > > of the GPU HW. This is a device globally owned protected memory.
> > >
> > > The thing is, it's really not clear why you absolutely need to have the
> > > Panthor driver involved there. It won't be transparent to userspace,
> > > since you'd need an extra flag at allocation time, and the buffers
> > > behave differently. If userspace has to be aware of it, what's the
> > > advantage to your approach compared to just exposing a heap for those
> > > secure buffers, and letting userspace allocate its buffers from there?
> >
> > Unless I'm mistaken, the Panthor driver loads its own firmware. Since loading
> > the firmware requires placing the data in a protected memory region, and that
> > this aspect has no exposure to userspace, how can Panthor not be implicated ?
>
> Right, the very reason we need protected memory early is because some
> FW sections need to be allocated from the protected pool, otherwise the
> TEE will fault as soon at the FW enters the so-called 'protected mode'.
How does that work if you don't have some way to allocate the protected
memory? You can still submit jobs to the GPU, but you can't submit /
execute "protected jobs"?
> Now, it's not impossible to work around this limitation. For instance,
> we could load the FW without this protected section by default (what we
> do right now), and then provide a DRM_PANTHOR_ENABLE_FW_PROT_MODE
> ioctl that would take a GEM object imported from a dmabuf allocated
> from the protected dma-heap by userspace. We can then reset the FW and
> allow it to operate in protected mode after that point.
Urgh, I'd rather avoid that dance if possible :)
> This approach has two downsides though:
>
> 1. We have no way of checking that the memory we're passed is actually
> suitable for FW execution in a protected context. If we're passed
> random memory, this will likely hang the platform as soon as we enter
> protected mode.
It's a current limitation of dma-buf in general, and you'd have the same
issue right now if someone imports a buffer, or misconfigure the heap
for a !protected heap.
I'd really like to have some way to store some metadata in dma_buf, if
only to tell that the buffer is protected.
I suspect you'd also need that if you do things like do protected video
playback through a codec, get a protected frame, and want to import that
into the GPU. Depending on how you allocate it, either the codec or the
GPU or both will want to make sure it's protected.
> 2. If the driver already boot the FW and exposed a DRI node, we might
> have GPU workloads running, and doing a FW reset might incur a slight
> delay in GPU jobs execution.
>
> I think #1 is a more general issue that applies to suspend buffers
> allocated for GPU contexts too. If we expose ioctls where we take
> protected memory buffers that can possibly lead to crashes if they are
> not real protected memory regions, and we have no way to ensure the
> memory is protected, we probably want to restrict these ioctls/modes to
> some high-privilege CAP_SYS_.
>
> For #2, that's probably something we can live with, since it's a
> one-shot thing. If it becomes an issue, we can even make sure we enable
> the FW protected-mode before the GPU starts being used for real.
>
> This being said, I think the problem applies outside Panthor, and it
> might be that the video codec can't reset the FW/HW block to switch to
> protected mode as easily as Panthor.
>
> Note that there's also downsides to the reserved-memory node approach,
> where some bootloader stage would ask the secure FW to reserve a
> portion of mem and pass this through the DT. This sort of things tend to
> be an integration mess, where you need all the pieces of the stack (TEE,
> u-boot, MTK dma-heap driver, gbm, ...) to be at a certain version to
> work properly. If we go the ioctl() way, we restrict the scope to the
> TEE, gbm/mesa and the protected-dma-heap driver, which is still a lot,
> but we've ripped the bootloader out of the equation at least.
Yeah. I also think there's two discussions in parallel here:
1) Being able to allocate protected buffers from the driver
2) Exposing an interface to allocate those to userspace
I'm not really convinced we need 2, but 1 is obviously needed from what
you're saying.
Maxime
1 year
- 1
- 0
Re: [RFC PATCH 3/5] dt-bindings: gpu: Add protected heap name to Mali Valhall CSF binding
by Krzysztof Kozlowski
On 03/02/2025 16:31, Florent Tomasin wrote:
> Hi Krzysztof
>
> On 30/01/2025 13:25, Krzysztof Kozlowski wrote:
>> On 30/01/2025 14:08, Florent Tomasin wrote:
>>> Allow mali-valhall-csf driver to retrieve a protected
>>> heap at probe time by passing the name of the heap
>>> as attribute to the device tree GPU node.
>>
>> Please wrap commit message according to Linux coding style / submission
>> process (neither too early nor over the limit):
>> https://elixir.bootlin.com/linux/v6.4-rc1/source/Documentation/process/subm…
> Apologies, I think I made quite few other mistakes in the style of the
> patches I sent. I will work on improving this aspect, appreciated
>
>> Why this cannot be passed by phandle, just like all reserved regions?
>>
>> From where do you take these protected heaps? Firmware? This would
>> explain why no relation is here (no probe ordering, no device links,
>> nothing connecting separate devices).
>
> The protected heap is generaly obtained from a firmware (TEE) and could
> sometimes be a carved-out memory with restricted access.
Which is a reserved memory, isn't it?
>
> The Panthor CSF kernel driver does not own or manage the protected heap
> and is instead a consumer of it (assuming the heap is made available by
> the system integrator).
>
> I initially used a phandle, but then I realised it would introduce a new
> API to share the heap across kernel driver. In addition I found this
> patch series:
> -
> https://lore.kernel.org/lkml/20230911023038.30649-1-yong.wu@mediatek.com/#t
>
> which introduces a DMA Heap API to the rest of the kernel to find a
> heap by name:
> - dma_heap_find()
>
> I then decided to follow that approach to help isolate the heap
> management from the GPU driver code. In the Panthor driver, if the
> heap is not found at probe time, the driver will defer the probe until
> the exporter made it available.
I don't talk here really about the driver but even above mediatek
patchset uses reserved memory bindings.
You explained some things about driver yet you did not answer the
question. This looks like reserved memory. If it does not, bring
arguments why this binding cannot be a reserved memory, why hardware is
not a carve out memory.
Best regards,
Krzysztof
1 year
- 2
- 2
Re: [RFC PATCH 0/5] drm/panthor: Protected mode support for Mali CSF GPUs
by Nicolas Dufresne
Le vendredi 07 février 2025 à 16:02 +0100, Boris Brezillon a écrit :
> Sorry for joining the party late, a couple of comments to back Akash
> and Nicolas' concerns.
>
> On Wed, 05 Feb 2025 13:14:14 -0500
> Nicolas Dufresne <nicolas(a)ndufresne.ca> wrote:
>
> > Le mercredi 05 février 2025 à 15:52 +0100, Maxime Ripard a écrit :
> > > On Mon, Feb 03, 2025 at 04:43:23PM +0000, Florent Tomasin wrote:
> > > > Hi Maxime, Nicolas
> > > >
> > > > On 30/01/2025 17:47, Nicolas Dufresne wrote:
> > > > > Le jeudi 30 janvier 2025 à 17:38 +0100, Maxime Ripard a écrit :
> > > > > > Hi Nicolas,
> > > > > >
> > > > > > On Thu, Jan 30, 2025 at 10:59:56AM -0500, Nicolas Dufresne wrote:
> > > > > > > Le jeudi 30 janvier 2025 à 14:46 +0100, Maxime Ripard a écrit :
> > > > > > > > Hi,
> > > > > > > >
> > > > > > > > I started to review it, but it's probably best to discuss it here.
> > > > > > > >
> > > > > > > > On Thu, Jan 30, 2025 at 01:08:56PM +0000, Florent Tomasin wrote:
> > > > > > > > > Hi,
> > > > > > > > >
> > > > > > > > > This is a patch series covering the support for protected mode execution in
> > > > > > > > > Mali Panthor CSF kernel driver.
> > > > > > > > >
> > > > > > > > > The Mali CSF GPUs come with the support for protected mode execution at the
> > > > > > > > > HW level. This feature requires two main changes in the kernel driver:
> > > > > > > > >
> > > > > > > > > 1) Configure the GPU with a protected buffer. The system must provide a DMA
> > > > > > > > > heap from which the driver can allocate a protected buffer.
> > > > > > > > > It can be a carved-out memory or dynamically allocated protected memory region.
> > > > > > > > > Some system includes a trusted FW which is in charge of the protected memory.
> > > > > > > > > Since this problem is integration specific, the Mali Panthor CSF kernel
> > > > > > > > > driver must import the protected memory from a device specific exporter.
> > > > > > > >
> > > > > > > > Why do you need a heap for it in the first place? My understanding of
> > > > > > > > your series is that you have a carved out memory region somewhere, and
> > > > > > > > you want to allocate from that carved out memory region your buffers.
> > > > > > > >
> > > > > > > > How is that any different from using a reserved-memory region, adding
> > > > > > > > the reserved-memory property to the GPU device and doing all your
> > > > > > > > allocation through the usual dma_alloc_* API?
> > > > > > >
> > > > > > > How do you then multiplex this region so it can be shared between
> > > > > > > GPU/Camera/Display/Codec drivers and also userspace ?
> > > > > >
> > > > > > You could point all the devices to the same reserved memory region, and
> > > > > > they would all allocate from there, including for their userspace-facing
> > > > > > allocations.
> > > > >
> > > > > I get that using memory region is somewhat more of an HW description, and
> > > > > aligned with what a DT is supposed to describe. One of the challenge is that
> > > > > Mediatek heap proposal endup calling into their TEE, meaning knowing the region
> > > > > is not that useful. You actually need the TEE APP guid and its IPC protocol. If
> > > > > we can dell drivers to use a head instead, we can abstract that SoC specific
> > > > > complexity. I believe each allocated addressed has to be mapped to a zone, and
> > > > > that can only be done in the secure application. I can imagine similar needs
> > > > > when the protection is done using some sort of a VM / hypervisor.
> > > > >
> > > > > Nicolas
> > > > >
> > > >
> > > > The idea in this design is to abstract the heap management from the
> > > > Panthor kernel driver (which consumes a DMA buffer from it).
> > > >
> > > > In a system, an integrator would have implemented a secure heap driver,
> > > > and could be based on TEE or a carved-out memory with restricted access,
> > > > or else. This heap driver would be responsible of implementing the
> > > > logic to: allocate, free, refcount, etc.
> > > >
> > > > The heap would be retrieved by the Panthor kernel driver in order to
> > > > allocate protected memory to load the FW and allow the GPU to enter/exit
> > > > protected mode. This memory would not belong to a user space process.
> > > > The driver allocates it at the time of loading the FW and initialization
> > > > of the GPU HW. This is a device globally owned protected memory.
> > >
> > > The thing is, it's really not clear why you absolutely need to have the
> > > Panthor driver involved there. It won't be transparent to userspace,
> > > since you'd need an extra flag at allocation time, and the buffers
> > > behave differently. If userspace has to be aware of it, what's the
> > > advantage to your approach compared to just exposing a heap for those
> > > secure buffers, and letting userspace allocate its buffers from there?
> >
> > Unless I'm mistaken, the Panthor driver loads its own firmware. Since loading
> > the firmware requires placing the data in a protected memory region, and that
> > this aspect has no exposure to userspace, how can Panthor not be implicated ?
>
> Right, the very reason we need protected memory early is because some
> FW sections need to be allocated from the protected pool, otherwise the
> TEE will fault as soon at the FW enters the so-called 'protected mode'.
>
> Now, it's not impossible to work around this limitation. For instance,
> we could load the FW without this protected section by default (what we
> do right now), and then provide a DRM_PANTHOR_ENABLE_FW_PROT_MODE
> ioctl that would take a GEM object imported from a dmabuf allocated
> from the protected dma-heap by userspace. We can then reset the FW and
> allow it to operate in protected mode after that point. This approach
> has two downsides though:
>
> 1. We have no way of checking that the memory we're passed is actually
> suitable for FW execution in a protected context. If we're passed
> random memory, this will likely hang the platform as soon as we enter
> protected mode.
>
> 2. If the driver already boot the FW and exposed a DRI node, we might
> have GPU workloads running, and doing a FW reset might incur a slight
> delay in GPU jobs execution.
>
> I think #1 is a more general issue that applies to suspend buffers
> allocated for GPU contexts too. If we expose ioctls where we take
> protected memory buffers that can possibly lead to crashes if they are
> not real protected memory regions, and we have no way to ensure the
> memory is protected, we probably want to restrict these ioctls/modes to
> some high-privilege CAP_SYS_.
>
> For #2, that's probably something we can live with, since it's a
> one-shot thing. If it becomes an issue, we can even make sure we enable
> the FW protected-mode before the GPU starts being used for real.
>
> This being said, I think the problem applies outside Panthor, and it
> might be that the video codec can't reset the FW/HW block to switch to
> protected mode as easily as Panthor.
Overall the reset and reboot method is pretty ugly in my opinion. But to stick
with the pure rationale, rebooting the SCP on MTK is much harder, since its not
specific to a single HW/driver.
Other codecs like Samsung MFC, Venus/Iris, Chips&Media, etc. that approach seams
plausible, but we still can't trust the buffer, which to me is not acceptable.
>
> Note that there's also downsides to the reserved-memory node approach,
> where some bootloader stage would ask the secure FW to reserve a
> portion of mem and pass this through the DT. This sort of things tend to
> be an integration mess, where you need all the pieces of the stack (TEE,
> u-boot, MTK dma-heap driver, gbm, ...) to be at a certain version to
> work properly. If we go the ioctl() way, we restrict the scope to the
> TEE, gbm/mesa and the protected-dma-heap driver, which is still a lot,
> but we've ripped the bootloader out of the equation at least.
>
> Regards,
>
> Boris
1 year
- 1
- 0
Re: [RFC PATCH 0/5] drm/panthor: Protected mode support for Mali CSF GPUs
by Maxime Ripard
On Mon, Feb 03, 2025 at 04:43:23PM +0000, Florent Tomasin wrote:
> Hi Maxime, Nicolas
>
> On 30/01/2025 17:47, Nicolas Dufresne wrote:
> > Le jeudi 30 janvier 2025 à 17:38 +0100, Maxime Ripard a écrit :
> >> Hi Nicolas,
> >>
> >> On Thu, Jan 30, 2025 at 10:59:56AM -0500, Nicolas Dufresne wrote:
> >>> Le jeudi 30 janvier 2025 à 14:46 +0100, Maxime Ripard a écrit :
> >>>> Hi,
> >>>>
> >>>> I started to review it, but it's probably best to discuss it here.
> >>>>
> >>>> On Thu, Jan 30, 2025 at 01:08:56PM +0000, Florent Tomasin wrote:
> >>>>> Hi,
> >>>>>
> >>>>> This is a patch series covering the support for protected mode execution in
> >>>>> Mali Panthor CSF kernel driver.
> >>>>>
> >>>>> The Mali CSF GPUs come with the support for protected mode execution at the
> >>>>> HW level. This feature requires two main changes in the kernel driver:
> >>>>>
> >>>>> 1) Configure the GPU with a protected buffer. The system must provide a DMA
> >>>>> heap from which the driver can allocate a protected buffer.
> >>>>> It can be a carved-out memory or dynamically allocated protected memory region.
> >>>>> Some system includes a trusted FW which is in charge of the protected memory.
> >>>>> Since this problem is integration specific, the Mali Panthor CSF kernel
> >>>>> driver must import the protected memory from a device specific exporter.
> >>>>
> >>>> Why do you need a heap for it in the first place? My understanding of
> >>>> your series is that you have a carved out memory region somewhere, and
> >>>> you want to allocate from that carved out memory region your buffers.
> >>>>
> >>>> How is that any different from using a reserved-memory region, adding
> >>>> the reserved-memory property to the GPU device and doing all your
> >>>> allocation through the usual dma_alloc_* API?
> >>>
> >>> How do you then multiplex this region so it can be shared between
> >>> GPU/Camera/Display/Codec drivers and also userspace ?
> >>
> >> You could point all the devices to the same reserved memory region, and
> >> they would all allocate from there, including for their userspace-facing
> >> allocations.
> >
> > I get that using memory region is somewhat more of an HW description, and
> > aligned with what a DT is supposed to describe. One of the challenge is that
> > Mediatek heap proposal endup calling into their TEE, meaning knowing the region
> > is not that useful. You actually need the TEE APP guid and its IPC protocol. If
> > we can dell drivers to use a head instead, we can abstract that SoC specific
> > complexity. I believe each allocated addressed has to be mapped to a zone, and
> > that can only be done in the secure application. I can imagine similar needs
> > when the protection is done using some sort of a VM / hypervisor.
> >
> > Nicolas
> >
>
> The idea in this design is to abstract the heap management from the
> Panthor kernel driver (which consumes a DMA buffer from it).
>
> In a system, an integrator would have implemented a secure heap driver,
> and could be based on TEE or a carved-out memory with restricted access,
> or else. This heap driver would be responsible of implementing the
> logic to: allocate, free, refcount, etc.
>
> The heap would be retrieved by the Panthor kernel driver in order to
> allocate protected memory to load the FW and allow the GPU to enter/exit
> protected mode. This memory would not belong to a user space process.
> The driver allocates it at the time of loading the FW and initialization
> of the GPU HW. This is a device globally owned protected memory.
The thing is, it's really not clear why you absolutely need to have the
Panthor driver involved there. It won't be transparent to userspace,
since you'd need an extra flag at allocation time, and the buffers
behave differently. If userspace has to be aware of it, what's the
advantage to your approach compared to just exposing a heap for those
secure buffers, and letting userspace allocate its buffers from there?
> When I came across this patch series:
> -
> https://lore.kernel.org/lkml/20230911023038.30649-1-yong.wu@mediatek.com/#t
> I found it could help abstract the interface between the secure heap and
> the integration of protected memory in Panthor.
>
> A kernel driver would have to find the heap: `dma_heap_find()`, then
> request allocation of a DMA buffer from it. The heap driver would deal
> with the specifities of the protected memory on the system.
Sure, but we still have to address *why* it would be a good idea for the
driver to do it in the first place. The mediatek series had the same
feedback.
Maxime
1 year
- 2
- 1
Re: [RFC PATCH 0/5] drm/panthor: Protected mode support for Mali CSF GPUs
by Nicolas Dufresne
Le lundi 03 février 2025 à 16:43 +0000, Florent Tomasin a écrit :
> Hi Maxime, Nicolas
>
> On 30/01/2025 17:47, Nicolas Dufresne wrote:
> > Le jeudi 30 janvier 2025 à 17:38 +0100, Maxime Ripard a écrit :
> > > Hi Nicolas,
> > >
> > > On Thu, Jan 30, 2025 at 10:59:56AM -0500, Nicolas Dufresne wrote:
> > > > Le jeudi 30 janvier 2025 à 14:46 +0100, Maxime Ripard a écrit :
> > > > > Hi,
> > > > >
> > > > > I started to review it, but it's probably best to discuss it here.
> > > > >
> > > > > On Thu, Jan 30, 2025 at 01:08:56PM +0000, Florent Tomasin wrote:
> > > > > > Hi,
> > > > > >
> > > > > > This is a patch series covering the support for protected mode execution in
> > > > > > Mali Panthor CSF kernel driver.
> > > > > >
> > > > > > The Mali CSF GPUs come with the support for protected mode execution at the
> > > > > > HW level. This feature requires two main changes in the kernel driver:
> > > > > >
> > > > > > 1) Configure the GPU with a protected buffer. The system must provide a DMA
> > > > > > heap from which the driver can allocate a protected buffer.
> > > > > > It can be a carved-out memory or dynamically allocated protected memory region.
> > > > > > Some system includes a trusted FW which is in charge of the protected memory.
> > > > > > Since this problem is integration specific, the Mali Panthor CSF kernel
> > > > > > driver must import the protected memory from a device specific exporter.
> > > > >
> > > > > Why do you need a heap for it in the first place? My understanding of
> > > > > your series is that you have a carved out memory region somewhere, and
> > > > > you want to allocate from that carved out memory region your buffers.
> > > > >
> > > > > How is that any different from using a reserved-memory region, adding
> > > > > the reserved-memory property to the GPU device and doing all your
> > > > > allocation through the usual dma_alloc_* API?
> > > >
> > > > How do you then multiplex this region so it can be shared between
> > > > GPU/Camera/Display/Codec drivers and also userspace ?
> > >
> > > You could point all the devices to the same reserved memory region, and
> > > they would all allocate from there, including for their userspace-facing
> > > allocations.
> >
> > I get that using memory region is somewhat more of an HW description, and
> > aligned with what a DT is supposed to describe. One of the challenge is that
> > Mediatek heap proposal endup calling into their TEE, meaning knowing the region
> > is not that useful. You actually need the TEE APP guid and its IPC protocol. If
> > we can dell drivers to use a head instead, we can abstract that SoC specific
> > complexity. I believe each allocated addressed has to be mapped to a zone, and
> > that can only be done in the secure application. I can imagine similar needs
> > when the protection is done using some sort of a VM / hypervisor.
> >
> > Nicolas
> >
>
> The idea in this design is to abstract the heap management from the
> Panthor kernel driver (which consumes a DMA buffer from it).
>
> In a system, an integrator would have implemented a secure heap driver,
> and could be based on TEE or a carved-out memory with restricted access,
> or else. This heap driver would be responsible of implementing the
> logic to: allocate, free, refcount, etc.
>
> The heap would be retrieved by the Panthor kernel driver in order to
> allocate protected memory to load the FW and allow the GPU to enter/exit
> protected mode. This memory would not belong to a user space process.
> The driver allocates it at the time of loading the FW and initialization
> of the GPU HW. This is a device globally owned protected memory.
This use case also applies well for codec. The Mediatek SCP firmware needs to be
loaded with a restricted memory too, its a very similar scenario, plus Mediatek
chips often include a Mali. On top of that, V4L2 codecs (in general) do need to
allocate internal scratch buffer for the IP to write to for things like motion
vectors, reconstruction frames, entropy statistics, etc. The IP will only be
able to write if the memory is restricted.
Nicolas
>
> When I came across this patch series:
> -
> https://lore.kernel.org/lkml/20230911023038.30649-1-yong.wu@mediatek.com/#t
> I found it could help abstract the interface between the secure heap and
> the integration of protected memory in Panthor.
>
> A kernel driver would have to find the heap: `dma_heap_find()`, then
> request allocation of a DMA buffer from it. The heap driver would deal
> with the specifities of the protected memory on the system.
>
> > >
> > > > Also, how the secure memory is allocted / obtained is a process that
> > > > can vary a lot between SoC, so implementation details assumption
> > > > should not be coded in the driver.
> > >
> > > But yeah, we agree there, it's also the point I was trying to make :)
> > >
> > > Maxime
> >
>
> Agree with your point, the Panthor kernel driver may not be aware of the
> heap management logic. As an alternative to the DMA heap API used here,
> I also tried to expose the heap by passing the phandle of a "heap"
> device to Panthor. The reference to the DMA heap was stored as a private
> data of the heap device as a new type: `struct dma_heap_import_info`,
> similar to the existing type: `struct dma_heap_export_info`.
> This made me think it could be problematic, as the private data type
> would have to be cast before accessing it from the importer driver. I
> worried about a mis-use of the types with this approach.
>
> Regards,
> Florent
1 year
- 2
- 2
Re: [RFC PATCH 1/5] dt-bindings: dma: Add CMA Heap bindings
by Nicolas Dufresne
Hi Florent,
Le lundi 03 février 2025 à 13:36 +0000, Florent Tomasin a écrit :
>
> On 30/01/2025 13:28, Maxime Ripard wrote:
> > Hi,
> >
> > On Thu, Jan 30, 2025 at 01:08:57PM +0000, Florent Tomasin wrote:
> > > Introduce a CMA Heap dt-binding allowing custom
> > > CMA heap registrations.
> > >
> > > * Note to the reviewers:
> > > The patch was used for the development of the protected mode
Just to avoid divergence in nomenclature, and because this is not a new subject,
perhaps you should also adhere to the name "restricted". Both Linaro and
Mediatek have moved from "secure" to that name in their proposal. As you are the
third proposing this (at least for the proposal that are CCed on linux-media), I
would have expected in your cover letter a summary of how the other requirement
have been blended in your proposal.
regards,
Nicolas
> > > feature in Panthor CSF kernel driver and is not initially thought
> > > to land in the Linux kernel. It is mostly relevant if someone
> > > wants to reproduce the environment of testing. Please, raise
> > > interest if you think the patch has value in the Linux kernel.
> > >
> > > Signed-off-by: Florent Tomasin <florent.tomasin(a)arm.com>
> > > ---
> > > .../devicetree/bindings/dma/linux,cma.yml | 43 +++++++++++++++++++
> > > 1 file changed, 43 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/dma/linux,cma.yml
> > >
> > > diff --git a/Documentation/devicetree/bindings/dma/linux,cma.yml b/Documentation/devicetree/bindings/dma/linux,cma.yml
> > > new file mode 100644
> > > index 000000000000..c532e016bbe5
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/dma/linux,cma.yml
> > > @@ -0,0 +1,43 @@
> > > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/dma/linux-cma.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Custom Linux CMA heap
> > > +
> > > +description:
> > > + The custom Linux CMA heap device tree node allows registering
> > > + of multiple CMA heaps.
> > > +
> > > + The CMA heap name will match the node name of the "memory-region".
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - linux,cma
> > > +
> > > + memory-region:
> > > + maxItems: 1
> > > + description: |
> > > + Phandle to the reserved memory node associated with the CMA Heap.
> > > + The reserved memory node must follow this binding convention:
> > > + - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
> > > +
> > > +examples:
> > > + - |
> > > + reserved-memory {
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > +
> > > + custom_cma_heap: custom-cma-heap {
> > > + compatible = "shared-dma-pool";
> > > + reg = <0x0 0x90600000 0x0 0x1000000>;
> > > + reusable;
> > > + };
> > > + };
> > > +
> > > + device_cma_heap: device-cma-heap {
> > > + compatible = "linux,cma";
> > > + memory-region = <&custom_cma_heap>;
> > > + };
> >
> > Isn't it redundant with the linux,cma-default shared-dma-pool property
> > already?
> >
> > Maxime
>
> Hi Maxime,
>
> Please correct me if my understanding is wrong,
>
> The existing properties: linux,cma-default and shared-dma-pool, do not
> allow the creations of multiple standalone CMA heaps, those will create
> a single CMA heap: `dma_contiguous_default_area`? Other CMA heaps will
> be bound to a driver.
>
> I introduced the "linux,cma" to allow creating multiple standalone CMA
> heaps, with the intention of validating the protected mode support on
> Mali CSG GPUs. It was included in the RFC in there are interests in
> this approach.
>
> Since the Panthor CSF kernel driver does not own or manage a heap,
> I needed a way to create a standalone heap. The idea here is for the
> kernel driver to be an importer. I relied on a patch series to retrieve
> the heap and allocate a DMA buffer from it:
> - dma_heap_find()
> - dma_heap_buffer_alloc()
> - dma_heap_put()
>
> Ref:
> https://lore.kernel.org/lkml/20230911023038.30649-1-yong.wu@mediatek.com/#t
>
>
> Since the protected/secure memory management is integration specific,
> I needed a generic way for Panthor to allocate from such heap.
>
> In some scenarios it might be a carved-out memory, in others a FW will
> reside in the system (TEE) and require a secure heap driver to allocate
> memory (e.g: a similar approach is followd by MTK). Such driver would
> implement the allocation and free logic.
>
> Florent
>
>
>
1 year
- 1
- 0
Re: [PATCH v7 0/7] Improve gpu_scheduler trace events + uAPI
by Christian König
I can't see patch #1 in my inbox for some reason, but I already know
what it does from your repository.
Feel free to add Reviewed-by: Christian König <christian.koenig(a)amd.com>
to the entire series.
Regards,
Christian.
Am 31.01.25 um 12:02 schrieb Pierre-Eric Pelloux-Prayer:
> Hi,
>
> The initial goal of this series was to improve the drm and amdgpu
> trace events to be able to expose more of the inner workings of
> the scheduler and drivers to developers via tools.
>
> Then, the series evolved to become focused only on gpu_scheduler.
> The changes around vblank events will be part of a different
> series, as well as the amdgpu ones.
>
> Moreover Sima suggested to make some trace events stable uAPI,
> so tools can rely on them long term.
>
> The first patches extend and cleanup the gpu scheduler events.
>
> The last one adds a documentation entry in drm-uapi.rst.
>
> Changes since v6:
> * Addressed comments from Philipp, Tvrtko, Steven
> * The commit storing drm_client_id in sched_fence adds an extra
> field which looks like a duplicate of the owner field. Currently
> amdgpu uses the owner field with some magic values, so we have to
> have 2 separate fields for now, but ultimately one could be removed.
> Similarly storing the drm_client_id in the sched_entity is not
> really possible as there's nothing preventing a driver to use a
> sched_entity with multiple drm_file instances.
>
>
> Useful links:
> - userspace tool using the updated events:
> https://gitlab.freedesktop.org/tomstdenis/umr/-/merge_requests/37
> - v6:
> https://lists.freedesktop.org/archives/dri-devel/2024-November/477644.html
>
> Pierre-Eric Pelloux-Prayer (7):
> drm/debugfs: output client_id in in drm_clients_info
> drm/sched: store the drm client_id in drm_sched_fence
> drm/sched: add device name to the drm_sched_process_job event
> drm/sched: cleanup gpu_scheduler trace events
> drm/sched: trace dependencies for gpu jobs
> drm/sched: add the drm_client_id to the drm_sched_run/exec_job events
> drm/doc: document some tracepoints as uAPI
>
> Documentation/gpu/drm-uapi.rst | 19 +++
> drivers/accel/amdxdna/aie2_ctx.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 8 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 +-
> drivers/gpu/drm/drm_debugfs.c | 10 +-
> drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 2 +-
> drivers/gpu/drm/imagination/pvr_job.c | 2 +-
> drivers/gpu/drm/imagination/pvr_queue.c | 5 +-
> drivers/gpu/drm/imagination/pvr_queue.h | 2 +-
> drivers/gpu/drm/lima/lima_gem.c | 2 +-
> drivers/gpu/drm/lima/lima_sched.c | 6 +-
> drivers/gpu/drm/lima/lima_sched.h | 3 +-
> drivers/gpu/drm/msm/msm_gem_submit.c | 8 +-
> drivers/gpu/drm/nouveau/nouveau_sched.c | 3 +-
> drivers/gpu/drm/panfrost/panfrost_drv.c | 2 +-
> drivers/gpu/drm/panthor/panthor_drv.c | 3 +-
> drivers/gpu/drm/panthor/panthor_mmu.c | 2 +-
> drivers/gpu/drm/panthor/panthor_sched.c | 5 +-
> drivers/gpu/drm/panthor/panthor_sched.h | 3 +-
> .../gpu/drm/scheduler/gpu_scheduler_trace.h | 123 ++++++++++++++----
> drivers/gpu/drm/scheduler/sched_entity.c | 8 +-
> drivers/gpu/drm/scheduler/sched_fence.c | 4 +-
> drivers/gpu/drm/scheduler/sched_main.c | 8 +-
> drivers/gpu/drm/v3d/v3d_submit.c | 2 +-
> drivers/gpu/drm/xe/xe_sched_job.c | 3 +-
> include/drm/gpu_scheduler.h | 12 +-
> 28 files changed, 192 insertions(+), 64 deletions(-)
>
1 year
- 1
- 0