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Re: [PATCH v1 05/10] media: platform: mediatek: add isp_7x camsys unit

by Krzysztof Kozlowski

On 09/10/2024 13:15, Shu-hsiang Yang wrote: > Introduces the top media device driver for the MediaTek ISP7X CAMSYS. > The driver maintains the camera system, including sub-device management, > DMA operations, and integration with the V4L2 framework. It handles > request stream data, buffer management, and MediaTek-specific features, > and pipeline management, streaming control, error handling mechanism. > Additionally, it aggregates sub-drivers for the camera interface, raw > and yuv pipelines. > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang(a)mediatek.com> ... > + > +static int mtk_cam_probe(struct platform_device *pdev) > +{ > + struct mtk_cam_device *cam_dev; > + struct device *dev = &pdev->dev; > + struct resource *res; > + int ret; > + unsigned int i; > + > + dev_dbg(dev, "camsys | start %s\n", __func__); NAK. Same issues. > + > + /* initialize structure */ > + cam_dev = devm_kzalloc(dev, sizeof(*cam_dev), GFP_KERNEL); > + if (!cam_dev) > + return -ENOMEM; > + > + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34))) { > + dev_err(dev, "%s: No suitable DMA available\n", __func__); > + return -EIO; > + } > + > + if (!dev->dma_parms) { > + dev->dma_parms = > + devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL); > + if (!dev->dma_parms) > + return -ENOMEM; > + } > + > + dma_set_max_seg_size(dev, UINT_MAX); > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) { > + dev_err(dev, "failed to get mem\n"); > + return -ENODEV; > + } > + > + cam_dev->base = devm_ioremap_resource(dev, res); > + if (IS_ERR(cam_dev->base)) { > + dev_err(dev, "failed to map register base\n"); > + return PTR_ERR(cam_dev->base); > + } > + > + cam_dev->dev = dev; > + dev_set_drvdata(dev, cam_dev); > + > + cam_dev->composer_cnt = 0; > + cam_dev->num_seninf_devices = 0; > + > + cam_dev->max_stream_num = MTKCAM_SUBDEV_MAX; > + cam_dev->ctxs = devm_kcalloc(dev, cam_dev->max_stream_num, > + sizeof(*cam_dev->ctxs), GFP_KERNEL); > + if (!cam_dev->ctxs) > + return -ENOMEM; > + > + cam_dev->streaming_ctx = 0; > + for (i = 0; i < cam_dev->max_stream_num; i++) > + mtk_cam_ctx_init(cam_dev->ctxs + i, cam_dev, i); > + > + cam_dev->running_job_count = 0; > + spin_lock_init(&cam_dev->pending_job_lock); > + spin_lock_init(&cam_dev->running_job_lock); > + INIT_LIST_HEAD(&cam_dev->pending_job_list); > + INIT_LIST_HEAD(&cam_dev->running_job_list); > + > + cam_dev->dma_processing_count = 0; > + spin_lock_init(&cam_dev->dma_pending_lock); > + spin_lock_init(&cam_dev->dma_processing_lock); > + INIT_LIST_HEAD(&cam_dev->dma_pending); > + INIT_LIST_HEAD(&cam_dev->dma_processing); > + > + mutex_init(&cam_dev->queue_lock); > + > + pm_runtime_enable(dev); > + > + ret = mtk_cam_of_rproc(cam_dev, pdev); > + if (ret) > + goto fail_destroy_mutex; > + > + ret = register_sub_drivers(dev); > + if (ret) { > + dev_err(dev, "fail to register_sub_drivers\n"); > + goto fail_destroy_mutex; > + } > + > + /* register mtk_cam as all isp subdev async parent */ > + cam_dev->notifier.ops = &mtk_cam_async_nf_ops; > + v4l2_async_nf_init(&cam_dev->notifier, &cam_dev->v4l2_dev); > + ret = mtk_cam_async_subdev_add(dev); /* wait all isp sub drivers */ > + if (ret) { > + dev_err(dev, "%s failed mtk_cam_async_subdev_add\n", __func__); > + goto fail_unregister_sub_drivers; > + } > + > + ret = v4l2_async_nf_register(&cam_dev->notifier); > + if (ret) { > + dev_err(dev, "%s async_nf_register ret:%d\n", __func__, ret); > + v4l2_async_nf_cleanup(&cam_dev->notifier); > + goto fail_unregister_sub_drivers; > + } > + > + ret = mtk_cam_debug_fs_init(cam_dev); > + if (ret < 0) > + goto fail_unregister_async_nf; > + > + dev_info(dev, "camsys | [%s] success\n", __func__); NAK. Same issues. > + > + return 0; > + > +fail_unregister_async_nf: > + v4l2_async_nf_unregister(&cam_dev->notifier); > + > +fail_unregister_sub_drivers: > + unregister_sub_drivers(dev); > + > +fail_destroy_mutex: > + mutex_destroy(&cam_dev->queue_lock); > + > + return ret; > +} > + > +static void mtk_cam_remove(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_cam_device *cam_dev = dev_get_drvdata(dev); > + > + pm_runtime_disable(dev); > + > + mtk_cam_debug_fs_deinit(cam_dev); > + > + v4l2_async_nf_unregister(&cam_dev->notifier); > + > + unregister_sub_drivers(dev); > + > + mutex_destroy(&cam_dev->queue_lock); > +} > + > +static const struct dev_pm_ops mtk_cam_pm_ops = { > + SET_RUNTIME_PM_OPS(mtk_cam_runtime_suspend, mtk_cam_runtime_resume, > + NULL) > +}; > + > +static struct platform_driver mtk_cam_driver = { > + .probe = mtk_cam_probe, > + .remove = mtk_cam_remove, > + .driver = { > + .name = "mtk-cam", > + .of_match_table = of_match_ptr(mtk_cam_of_ids), Same issues as in previous patch. All my comments apply to all your patches in this thread. > + .pm = &mtk_cam_pm_ops, > + } > +}; Best regards, Krzysztof

7 months, 2 weeks

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Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit

by Krzysztof Kozlowski

On 09/10/2024 13:15, Shu-hsiang Yang wrote: > Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv > modules. Key functionalities include data processing, V4L2 integration, > resource management, debug support, and various control operations. > Additionally, IRQ handling, platform device management, and MediaTek > ISP DMA format support are also included. > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang(a)mediatek.com> ... > + > +static int mtk_yuv_of_probe(struct platform_device *pdev, > + struct mtk_yuv_device *drvdata) > +{ > + struct device *dev = &pdev->dev; > + struct resource *res; > + int irq, ret; > + int n_clks; > + > + ret = of_property_read_u32(dev->of_node, "mediatek,cam-id", > + &drvdata->id); > + if (ret) { > + dev_dbg(dev, "missing camid property\n"); Debug? Or error? > + return ret; > + } > + > + if (dma_set_mask_and_coherent(dev, DMA_BIT_MASK(34))) { > + dev_err(dev, "%s: No suitable DMA available\n", __func__); > + return -EIO; > + } > + > + if (!dev->dma_parms) { > + dev->dma_parms = > + devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL); > + if (!dev->dma_parms) > + return -ENOMEM; > + } > + > + dma_set_max_seg_size(dev, UINT_MAX); > + > + /* base outer register */ > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base"); > + if (!res) { > + dev_err(dev, "failed to get mem\n"); > + return -ENODEV; > + } > + > + drvdata->base = devm_ioremap_resource(dev, res); > + if (IS_ERR(drvdata->base)) { > + dev_dbg(dev, "failed to map register base\n"); Dbg? What? > + return PTR_ERR(drvdata->base); > + } > + > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) { > + dev_err(dev, "failed to get irq\n"); > + return -ENODEV; > + } > + > + ret = devm_request_irq(dev, irq, mtk_irq_yuv, 0, > + dev_name(dev), drvdata); > + if (ret) { > + dev_err(dev, "failed to request irq=%d\n", irq); > + return ret; > + } > + dev_dbg(dev, "registered irq=%d\n", irq); Drop > + > + n_clks = devm_clk_bulk_get_all(dev, &drvdata->clk_b); > + if (n_clks < 0) { > + dev_err(dev, "failed to devm_clk_bulk_get_all=%d\n", n_clks); Syntax is: return dev_err_probe() > + return n_clks; > + } > + > + drvdata->num_clks = n_clks; > + dev_info(dev, "clk_num:%d\n", drvdata->num_clks); Drop > + > +#ifdef CONFIG_PM_SLEEP > + drvdata->pm_notifier.notifier_call = yuv_pm_notifier; > + ret = register_pm_notifier(&drvdata->pm_notifier); > + if (ret) { > + dev_err(dev, "failed to register notifier block.\n"); > + return ret; > + } > +#endif > + > + return 0; > +} > + > +static int mtk_yuv_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_yuv_device *drvdata; > + struct v4l2_subdev *sd; > + int ret; > + > + dev_dbg(dev, "camsys | start %s\n", __func__); NAK > + > + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); > + if (!drvdata) > + return -ENOMEM; > + > + drvdata->dev = dev; > + dev_set_drvdata(dev, drvdata); > + > + ret = mtk_yuv_of_probe(pdev, drvdata); > + if (ret) { > + dev_info(dev, "mtk_yuv_of_probe failed\n"); NAK. Neither info nor proper for memory allocation errors. Drop. > + return ret; > + } > + > + /* register yuv as mtk_cam async child */ > + sd = &drvdata->subdev; > + v4l2_subdev_init(sd, &mtk_raw_subdev_ops); > + sd->internal_ops = &mtk_raw_subdev_internal_ops; > + snprintf(sd->name, sizeof(sd->name), "%s", > + of_node_full_name(dev->of_node)); > + sd->dev = dev; > + sd->owner = THIS_MODULE; > + > + ret = v4l2_async_register_subdev(sd); > + if (ret) { > + dev_err(dev, "%s failed on async_register_subdev\n", __func__); > + return ret; > + } > + > + pm_runtime_enable(dev); > + > + dev_info(dev, "camsys | [%s] success\n", __func__); NAK > + > + return 0; > +} > + > +static void mtk_yuv_remove(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct mtk_yuv_device *yuv_dev = dev_get_drvdata(dev); > + struct v4l2_subdev *sd = &yuv_dev->subdev; > + > + dev_dbg(dev, "camsys | start %s\n", __func__); NAK > + > + unregister_pm_notifier(&yuv_dev->pm_notifier); > + > + pm_runtime_disable(dev); > + > + v4l2_async_unregister_subdev(sd); > +} > + > +/* driver for yuv part */ > +static int mtk_yuv_runtime_suspend(struct device *dev) > +{ > + struct mtk_yuv_device *drvdata = dev_get_drvdata(dev); > + > + dev_info(dev, "%s:disable clock\n", __func__); NAK > + > + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clk_b); > + > + return 0; > +} > + > +static int mtk_yuv_runtime_resume(struct device *dev) > +{ > + struct mtk_yuv_device *drvdata = dev_get_drvdata(dev); > + int ret; > + > + dev_info(dev, "%s:enable clock\n", __func__); NAK. Not even dev_dbg. Please don't ever post such code. > + > + ret = clk_bulk_prepare_enable(drvdata->num_clks, drvdata->clk_b); > + if (ret) { > + dev_info(dev, "failed at clk_bulk_prepare_enable, ret = %d\n", ret); > + clk_bulk_disable_unprepare(drvdata->num_clks, drvdata->clk_b); > + return ret; > + } > + > + return 0; > +} > + > +static const struct dev_pm_ops mtk_yuv_pm_ops = { > + SET_RUNTIME_PM_OPS(mtk_yuv_runtime_suspend, mtk_yuv_runtime_resume, > + NULL) > +}; > + > +static const struct of_device_id mtk_yuv_of_ids[] = { > + {.compatible = "mediatek,cam-yuv",}, > + {} > +}; > +MODULE_DEVICE_TABLE(of, mtk_yuv_of_ids); > + > +struct platform_driver mtk_cam_yuv_driver = { > + .probe = mtk_yuv_probe, > + .remove = mtk_yuv_remove, > + .driver = { > + .name = "mtk-cam yuv", > + .of_match_table = of_match_ptr(mtk_yuv_of_ids), Drop of_match_ptr(), you will have here warnings. > + .pm = &mtk_yuv_pm_ops, > + } > +}; ... > diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h > new file mode 100644 > index 000000000000..b775e6c30aa1 > --- /dev/null > +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h > @@ -0,0 +1,65 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2022 MediaTek Inc. > + */ > + > +#ifndef __MTK_CAMERA_V4l2_CONTROLS_H > +#define __MTK_CAMERA_V4l2_CONTROLS_H > + > +#include <linux/videodev2.h> > +#include <linux/v4l2-controls.h> > +#include <linux/mtkisp_camsys.h> How these headers are used here? I don't see. Don't include unrelated stuff in your files. > + > +/* Allowed value of V4L2_CID_MTK_CAM_RAW_PATH_SELECT */ > +#define V4L2_MTK_CAM_RAW_PATH_SELECT_BPC 1 > +#define V4L2_MTK_CAM_RAW_PATH_SELECT_FUS 3 > +#define V4L2_MTK_CAM_RAW_PATH_SELECT_DGN 4 > +#define V4L2_MTK_CAM_RAW_PATH_SELECT_LSC 5 > +#define V4L2_MTK_CAM_RAW_PATH_SELECT_LTM 7 > + > +#define V4L2_MBUS_FRAMEFMT_PAD_ENABLE BIT(1) Best regards, Krzysztof

7 months, 2 weeks

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Re: [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device

by Krzysztof Kozlowski

On 09/10/2024 13:15, Shu-hsiang Yang wrote: > 1. Add camera isp7x module device document > 2. Add camera interface device document > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang(a)mediatek.com> > --- > .../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++ > .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++ > .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++ > .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++ > .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++ > 5 files changed, 582 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml > new file mode 100644 > index 000000000000..c709e4bf0a18 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml > @@ -0,0 +1,169 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2024 MediaTek Inc. > + Drop blank line > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: The cam-raw unit of MediaTek ISP system > + > +maintainers: > + - Shu-hsiang Yang <shu-hsiang.yang(a)mediatek.com> > + - Shun-yi Wang <shun-yi.wang(a)mediatek.com> > + - Teddy Chen <teddy.chen(a)mediatek.com> > + > +description: > + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC. > + > +properties: > + compatible: > + const: mediatek,cam-raw SoC specific compatible instead. I see Rob gave you review, so few more points. ... > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-parents: > + maxItems: 1 Drop assigned-clock* > + > + iommus: > + description: > + Points to the respective IOMMU block with master port as argument, see > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. > + Ports are according to the HW. > + minItems: 1 > + maxItems: 32 > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - power-domains > + - clocks > + - clock-names > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/mediatek,mt8188-power.h> > + #include <dt-bindings/clock/mediatek,mt8188-clk.h> > + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cam_raw_a@16030000 { Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetr… e.g. isp Also, underscores are not allowed in node names. Please do not send to us your downstream code. Read DTS coding style and write code maching upstream style. > + compatible = "mediatek,cam-raw"; > + reg = <0 0x16030000 0 0x8000>, > + <0 0x16038000 0 0x8000>; > + reg-names = "base", "inner_base"; > + mediatek,cam-id = <0>; > + mediatek,larbs = <&larb16a>; > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; > + #address-cells = <2>; > + #size-cells = <2>; > + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; > + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>; > + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, > + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, > + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>, > + <&camsys CLK_CAM_MAIN_CAM>, > + <&camsys CLK_CAM_MAIN_CAMTG>, > + <&camsys_rawa CLK_CAM_RAWA_LARBX>, > + <&camsys_rawa CLK_CAM_RAWA_CAM>, > + <&camsys_rawa CLK_CAM_RAWA_CAMTG>, > + <&topckgen CLK_TOP_CAM>, > + <&topckgen CLK_TOP_CAMTG>, > + <&topckgen CLK_TOP_CAMTM>; Messed alignment. > + clock-names = "camsys_cam2mm0_cgpdn", > + "camsys_cam2mm1_cgpdn", > + "camsys_cam2sys_cgpdn", > + "camsys_cam_cgpdn", > + "camsys_camtg_cgpdn", > + "camsys_rawa_larbx_cgpdn", > + "camsys_rawa_cam_cgpdn", > + "camsys_rawa_camtg_cgpdn", > + "topckgen_top_cam", > + "topckgen_top_camtg", > + "topckgen_top_camtm"; Also misaligned. > + assigned-clocks = <&topckgen CLK_TOP_CAM>; > + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>; > + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>, > + <&vpp_iommu M4U_PORT_L16A_CQI_R1>, Also misaligned. All comments apply to other files as well. Best regards, Krzysztof

7 months, 2 weeks

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Re: [PATCH v1 5/5] i2c: i2c-qcom-geni: Add Block event interrupt support

by kernel test robot

Hi Jyothi, kernel test robot noticed the following build errors: [auto build test ERROR on 55bcd2e0d04c1171d382badef1def1fd04ef66c5] url: https://github.com/intel-lab-lkp/linux/commits/Jyothi-Kumar-Seerapu/dt-bind… base: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 patch link: https://lore.kernel.org/r/20241015120750.21217-6-quic_jseerapu%40quicinc.com patch subject: [PATCH v1 5/5] i2c: i2c-qcom-geni: Add Block event interrupt support config: i386-allmodconfig (https://download.01.org/0day-ci/archive/20241019/202410191055.bi1pWTAY-lkp@…) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241019/202410191055.bi1pWTAY-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410191055.bi1pWTAY-lkp@intel.com/ All errors (new ones prefixed by >>, old ones prefixed by <<): >> ERROR: modpost: "gpi_multi_desc_process" [drivers/i2c/busses/i2c-qcom-geni.ko] undefined! Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for GET_FREE_REGION Depends on [n]: SPARSEMEM [=n] Selected by [m]: - RESOURCE_KUNIT_TEST [=m] && RUNTIME_TESTING_MENU [=y] && KUNIT [=m] WARNING: unmet direct dependencies detected for OMAP2PLUS_MBOX Depends on [n]: MAILBOX [=y] && (ARCH_OMAP2PLUS || ARCH_K3) Selected by [m]: - TI_K3_M4_REMOTEPROC [=m] && REMOTEPROC [=y] && (ARCH_K3 || COMPILE_TEST [=y]) -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

7 months, 3 weeks

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Re: [PATCH v1 5/5] i2c: i2c-qcom-geni: Add Block event interrupt support

by kernel test robot

Hi Jyothi, kernel test robot noticed the following build errors: [auto build test ERROR on 55bcd2e0d04c1171d382badef1def1fd04ef66c5] url: https://github.com/intel-lab-lkp/linux/commits/Jyothi-Kumar-Seerapu/dt-bind… base: 55bcd2e0d04c1171d382badef1def1fd04ef66c5 patch link: https://lore.kernel.org/r/20241015120750.21217-6-quic_jseerapu%40quicinc.com patch subject: [PATCH v1 5/5] i2c: i2c-qcom-geni: Add Block event interrupt support config: x86_64-allyesconfig (https://download.01.org/0day-ci/archive/20241019/202410190549.hGAfByqg-lkp@…) compiler: clang version 18.1.8 (https://github.com/llvm/llvm-project 3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20241019/202410190549.hGAfByqg-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202410190549.hGAfByqg-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/i2c/busses/i2c-qcom-geni.c:562:8: error: incompatible pointer to integer conversion passing 'dma_addr_t *' (aka 'unsigned long long *') to parameter of type 'dma_addr_t' (aka 'unsigned long long'); dereference with * [-Wint-conversion] 562 | tx_multi_xfer->dma_addr[wr_idx], NULL, NULL); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | * drivers/i2c/busses/i2c-qcom-geni.c:519:36: note: passing argument to parameter 'tx_addr' here 519 | void *tx_buf, dma_addr_t tx_addr, | ^ >> drivers/i2c/busses/i2c-qcom-geni.c:562:47: error: incompatible pointer to integer conversion passing 'void *' to parameter of type 'dma_addr_t' (aka 'unsigned long long') [-Wint-conversion] 562 | tx_multi_xfer->dma_addr[wr_idx], NULL, NULL); | ^~~~ include/linux/stddef.h:8:14: note: expanded from macro 'NULL' 8 | #define NULL ((void *)0) | ^~~~~~~~~~~ drivers/i2c/busses/i2c-qcom-geni.c:520:36: note: passing argument to parameter 'rx_addr' here 520 | void *rx_buf, dma_addr_t rx_addr) | ^ >> drivers/i2c/busses/i2c-qcom-geni.c:586:7: error: incompatible pointer to integer conversion assigning to 'dma_addr_t' (aka 'unsigned long long') from 'dma_addr_t *' (aka 'unsigned long long *'); dereference with * [-Wint-conversion] 586 | addr = gi2c_gpi_xfer->dma_addr[gi2c_gpi_xfer->buf_idx]; | ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | * 3 errors generated. Kconfig warnings: (for reference only) WARNING: unmet direct dependencies detected for OMAP2PLUS_MBOX Depends on [n]: MAILBOX [=y] && (ARCH_OMAP2PLUS || ARCH_K3) Selected by [y]: - TI_K3_M4_REMOTEPROC [=y] && REMOTEPROC [=y] && (ARCH_K3 || COMPILE_TEST [=y]) vim +562 drivers/i2c/busses/i2c-qcom-geni.c 532 533 /** 534 * gpi_i2c_multi_desc_unmap() - unmaps the buffers post multi message TX transfers 535 * @dev: pointer to the corresponding dev node 536 * @gi2c: i2c dev handle 537 * @msgs: i2c messages array 538 * @peripheral: pointer to the gpi_i2c_config 539 */ 540 static void gpi_i2c_multi_desc_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], 541 struct gpi_i2c_config *peripheral) 542 { 543 u32 msg_xfer_cnt, wr_idx = 0; 544 struct gpi_multi_xfer *tx_multi_xfer = &peripheral->multi_xfer; 545 546 /* 547 * In error case, need to unmap all messages based on the msg_idx_cnt. 548 * Non-error case unmap all the processed messages. 549 */ 550 if (gi2c->err) 551 msg_xfer_cnt = tx_multi_xfer->msg_idx_cnt; 552 else 553 msg_xfer_cnt = tx_multi_xfer->irq_cnt * NUM_MSGS_PER_IRQ; 554 555 /* Unmap the processed DMA buffers based on the received interrupt count */ 556 for (; tx_multi_xfer->unmap_msg_cnt < msg_xfer_cnt; tx_multi_xfer->unmap_msg_cnt++) { 557 if (tx_multi_xfer->unmap_msg_cnt == gi2c->num_msgs) 558 break; 559 wr_idx = tx_multi_xfer->unmap_msg_cnt % QCOM_GPI_MAX_NUM_MSGS; 560 geni_i2c_gpi_unmap(gi2c, &msgs[tx_multi_xfer->unmap_msg_cnt], 561 tx_multi_xfer->dma_buf[wr_idx], > 562 tx_multi_xfer->dma_addr[wr_idx], NULL, NULL); 563 tx_multi_xfer->freed_msg_cnt++; 564 } 565 } 566 567 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int cur_msg_idx, 568 struct dma_slave_config *config, dma_addr_t *dma_addr_p, 569 void **buf, unsigned int op, struct dma_chan *dma_chan) 570 { 571 struct gpi_i2c_config *peripheral; 572 unsigned int flags; 573 void *dma_buf; 574 dma_addr_t addr; 575 enum dma_data_direction map_dirn; 576 enum dma_transfer_direction dma_dirn; 577 struct dma_async_tx_descriptor *desc; 578 int ret; 579 struct gpi_multi_xfer *gi2c_gpi_xfer; 580 dma_cookie_t cookie; 581 582 peripheral = config->peripheral_config; 583 gi2c_gpi_xfer = &peripheral->multi_xfer; 584 gi2c_gpi_xfer->msg_idx_cnt = cur_msg_idx; 585 dma_buf = gi2c_gpi_xfer->dma_buf[gi2c_gpi_xfer->buf_idx]; > 586 addr = gi2c_gpi_xfer->dma_addr[gi2c_gpi_xfer->buf_idx]; 587 588 dma_buf = i2c_get_dma_safe_msg_buf(&msgs[gi2c_gpi_xfer->msg_idx_cnt], 1); 589 if (!dma_buf) { 590 gi2c->err = -ENOMEM; 591 return -ENOMEM; 592 } 593 594 if (op == I2C_WRITE) 595 map_dirn = DMA_TO_DEVICE; 596 else 597 map_dirn = DMA_FROM_DEVICE; 598 599 addr = dma_map_single(gi2c->se.dev->parent, 600 dma_buf, msgs[gi2c_gpi_xfer->msg_idx_cnt].len, 601 map_dirn); 602 if (dma_mapping_error(gi2c->se.dev->parent, addr)) { 603 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[gi2c_gpi_xfer->msg_idx_cnt], 604 false); 605 gi2c->err = -ENOMEM; 606 return -ENOMEM; 607 } 608 609 if (gi2c->is_tx_multi_xfer) { 610 if (((gi2c_gpi_xfer->msg_idx_cnt + 1) % NUM_MSGS_PER_IRQ)) 611 peripheral->flags |= QCOM_GPI_BLOCK_EVENT_IRQ; 612 else 613 peripheral->flags &= ~QCOM_GPI_BLOCK_EVENT_IRQ; 614 615 /* BEI bit to be cleared for last TRE */ 616 if (gi2c_gpi_xfer->msg_idx_cnt == gi2c->num_msgs - 1) 617 peripheral->flags &= ~QCOM_GPI_BLOCK_EVENT_IRQ; 618 } 619 620 /* set the length as message for rx txn */ 621 peripheral->rx_len = msgs[gi2c_gpi_xfer->msg_idx_cnt].len; 622 peripheral->op = op; 623 624 ret = dmaengine_slave_config(dma_chan, config); 625 if (ret) { 626 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op); 627 goto err_config; 628 } 629 630 peripheral->set_config = 0; 631 peripheral->multi_msg = true; 632 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK; 633 634 if (op == I2C_WRITE) 635 dma_dirn = DMA_MEM_TO_DEV; 636 else 637 dma_dirn = DMA_DEV_TO_MEM; 638 639 desc = dmaengine_prep_slave_single(dma_chan, addr, 640 msgs[gi2c_gpi_xfer->msg_idx_cnt].len, 641 dma_dirn, flags); 642 if (!desc) { 643 dev_err(gi2c->se.dev, "prep_slave_sg failed\n"); 644 gi2c->err = -EIO; 645 goto err_config; 646 } 647 648 desc->callback_result = i2c_gpi_cb_result; 649 desc->callback_param = gi2c; 650 651 if (!((msgs[cur_msg_idx].flags & I2C_M_RD) && op == I2C_WRITE)) { 652 gi2c_gpi_xfer->msg_idx_cnt++; 653 gi2c_gpi_xfer->buf_idx = (cur_msg_idx + 1) % QCOM_GPI_MAX_NUM_MSGS; 654 } 655 cookie = dmaengine_submit(desc); 656 if (dma_submit_error(cookie)) { 657 dev_err(gi2c->se.dev, 658 "%s: dmaengine_submit failed (%d)\n", __func__, cookie); 659 return -EINVAL; 660 } 661 662 if (gi2c->is_tx_multi_xfer) { 663 dma_async_issue_pending(gi2c->tx_c); 664 if ((cur_msg_idx == (gi2c->num_msgs - 1)) || 665 (gi2c_gpi_xfer->msg_idx_cnt >= 666 QCOM_GPI_MAX_NUM_MSGS + gi2c_gpi_xfer->freed_msg_cnt)) { 667 ret = gpi_multi_desc_process(gi2c->se.dev, gi2c_gpi_xfer, 668 gi2c->num_msgs, XFER_TIMEOUT, 669 &gi2c->done); 670 if (ret) { 671 dev_dbg(gi2c->se.dev, 672 "I2C multi write msg transfer timeout: %d\n", 673 ret); 674 gi2c->err = -ETIMEDOUT; 675 goto err_config; 676 } 677 } 678 } else { 679 /* Non multi descriptor message transfer */ 680 *buf = dma_buf; 681 *dma_addr_p = addr; 682 } 683 return 0; 684 685 err_config: 686 dma_unmap_single(gi2c->se.dev->parent, addr, 687 msgs[cur_msg_idx].len, map_dirn); 688 i2c_put_dma_safe_msg_buf(dma_buf, &msgs[cur_msg_idx], false); 689 return ret; 690 } 691 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

7 months, 3 weeks

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[RFC PATCH v2 0/2] TEE subsystem for restricted dma-buf allocations

by Jens Wiklander

Hi, This patch set allocates the restricted DMA-bufs via the TEE subsystem. This a complete rewrite compared to the previous patch set [1], and other earlier proposals [2] and [3] with a separate restricted heap. The TEE subsystem handles the DMA-buf allocations since it is the TEE (OP-TEE, AMD-TEE, TS-TEE, or a future QTEE) which sets up the restrictions for the memory used for the DMA-bufs. I've added a new IOCTL, TEE_IOC_RSTMEM_ALLOC, to allocate the restricted DMA-bufs. This new IOCTL reaches the backend TEE driver, allowing it to choose how to allocate the restricted physical memory. TEE_IOC_RSTMEM_ALLOC is quite similar to TEE_IOC_SHM_ALLOC so it's tempting to extend TEE_IOC_SHM_ALLOC with two new flags TEE_IOC_SHM_FLAG_SECURE_VIDEO and TEE_IOC_SHM_FLAG_SECURE_TRUSTED_UI for the same feature. However, it might be a bit confusing since TEE_IOC_SHM_ALLOC only returns an anonymous file descriptor, but TEE_IOC_SHM_FLAG_SECURE_VIDEO and TEE_IOC_SHM_FLAG_SECURE_TRUSTED_UI would return a DMA-buf file descriptor instead. What do others think? This can be tested on QEMU with the following steps: repo init -u https://github.com/jenswi-linaro/manifest.git -m qemu_v8.xml \ -b prototype/sdp-v2 repo sync -j8 cd build make toolchains -j4 make all -j$(nproc) make run-only # login and at the prompt: xtest --sdp-basic https://optee.readthedocs.io/en/latest/building/prerequisites.html list dependencies needed to build the above. The tests are pretty basic, mostly checking that a Trusted Application in the secure world can access and manipulate the memory. There are also some negative tests for out of bounds buffers etc. Thanks, Jens [1] https://lore.kernel.org/lkml/20240830070351.2855919-1-jens.wiklander@linaro… [2] https://lore.kernel.org/dri-devel/20240515112308.10171-1-yong.wu@mediatek.c… [3] https://lore.kernel.org/lkml/20220805135330.970-1-olivier.masse@nxp.com/ Changes since the V1 RFC: * Based on v6.11 * Complete rewrite, replacing the restricted heap with TEE_IOC_RSTMEM_ALLOC Changes since Olivier's post [2]: * Based on Yong Wu's post [1] where much of dma-buf handling is done in the generic restricted heap * Simplifications and cleanup * New commit message for "dma-buf: heaps: add Linaro restricted dmabuf heap support" * Replaced the word "secure" with "restricted" where applicable Jens Wiklander (2): tee: add restricted memory allocation optee: support restricted memory allocation drivers/tee/Makefile | 1 + drivers/tee/optee/core.c | 21 ++++ drivers/tee/optee/optee_private.h | 6 + drivers/tee/optee/optee_smc.h | 35 ++++++ drivers/tee/optee/smc_abi.c | 45 ++++++- drivers/tee/tee_core.c | 33 ++++- drivers/tee/tee_private.h | 2 + drivers/tee/tee_rstmem.c | 200 ++++++++++++++++++++++++++++++ drivers/tee/tee_shm.c | 2 + drivers/tee/tee_shm_pool.c | 69 ++++++++++- include/linux/tee_core.h | 6 + include/linux/tee_drv.h | 9 ++ include/uapi/linux/tee.h | 33 ++++- 13 files changed, 455 insertions(+), 7 deletions(-) create mode 100644 drivers/tee/tee_rstmem.c -- 2.43.0

7 months, 3 weeks

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[PATCH] dma-buf/dma-fence_array: use kvzalloc

by Christian König

Reports indicates that some userspace applications try to merge more than 80k of fences into a single dma_fence_array leading to a warning from kzalloc() that the requested size becomes to big. While that is clearly an userspace bug we should probably handle that case gracefully in the kernel. So we can either reject requests to merge more than a reasonable amount of fences (64k maybe?) or we can start to use kvzalloc() instead of kzalloc(). This patch here does the later. Signed-off-by: Christian König <christian.koenig(a)amd.com> CC: stable(a)vger.kernel.org --- drivers/dma-buf/dma-fence-array.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma-buf/dma-fence-array.c b/drivers/dma-buf/dma-fence-array.c index 8a08ffde31e7..46ac42bcfac0 100644 --- a/drivers/dma-buf/dma-fence-array.c +++ b/drivers/dma-buf/dma-fence-array.c @@ -119,8 +119,8 @@ static void dma_fence_array_release(struct dma_fence *fence) for (i = 0; i < array->num_fences; ++i) dma_fence_put(array->fences[i]); - kfree(array->fences); - dma_fence_free(fence); + kvfree(array->fences); + kvfree_rcu(fence, rcu); } static void dma_fence_array_set_deadline(struct dma_fence *fence, @@ -153,7 +153,7 @@ struct dma_fence_array *dma_fence_array_alloc(int num_fences) { struct dma_fence_array *array; - return kzalloc(struct_size(array, callbacks, num_fences), GFP_KERNEL); + return kvzalloc(struct_size(array, callbacks, num_fences), GFP_KERNEL); } EXPORT_SYMBOL(dma_fence_array_alloc); -- 2.34.1

7 months, 3 weeks

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Re: [PATCH 9/9] drm/panfrost: Explicitly clean up panfrost fence

by Christian König

Am 16.10.24 um 18:43 schrieb Adrián Larumbe: > On 16.10.2024 15:12, Christian König wrote: >> Am 15.10.24 um 01:31 schrieb Adrián Larumbe: >>> Doesn't make any functional difference because generic dma_fence is the >>> first panfrost_fence structure member, but I guess it doesn't hurt either. >> As discussed with Sima we want to push into the exactly opposite direction >> because that requires that the panfrost module stays loaded as long as fences >> are around. > Does that mean in future commits the struct dma_fence_ops' .release pointer will be > done with altogether? Yes, exactly that's the idea. As a first step I'm preparing patches right now to enforce using kmalloc instead of driver brewed approaches for dma_fence handling. Regards, Christian. > >> So clearly a NAK to this one here. Rather document on the structure that the >> dma_fence structure must be the first member. >> >> Regards, >> Christian. >> >>> Signed-off-by: Adrián Larumbe <adrian.larumbe(a)collabora.com> >>> --- >>> drivers/gpu/drm/panfrost/panfrost_job.c | 6 ++++++ >>> 1 file changed, 6 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c >>> index 5d83c6a148ec..fa219f719bdc 100644 >>> --- a/drivers/gpu/drm/panfrost/panfrost_job.c >>> +++ b/drivers/gpu/drm/panfrost/panfrost_job.c >>> @@ -85,9 +85,15 @@ static const char *panfrost_fence_get_timeline_name(struct dma_fence *fence) >>> } >>> } >>> +static void panfrost_fence_release(struct dma_fence *fence) >>> +{ >>> + kfree(to_panfrost_fence(fence)); >>> +} >>> + >>> static const struct dma_fence_ops panfrost_fence_ops = { >>> .get_driver_name = panfrost_fence_get_driver_name, >>> .get_timeline_name = panfrost_fence_get_timeline_name, >>> + .release = panfrost_fence_release, >>> }; >>> static struct dma_fence *panfrost_fence_create(struct panfrost_device *pfdev, int js_num)

7 months, 3 weeks

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Re: [PATCH v1 2/5] arm64: dts: qcom: Add support for configuring channel TRE size

by Krzysztof Kozlowski

On 15/10/2024 14:07, Jyothi Kumar Seerapu wrote: > When high performance with multiple i2c messages in a single transfer > is required, employ Block Event Interrupt (BEI) to trigger interrupts > after specific messages transfer and the last message transfer, > thereby reducing interrupts. > For each i2c message transfer, a series of Transfer Request Elements(TREs) > must be programmed, including config tre for frequency configuration, > go tre for holding i2c address and dma tre for holding dma buffer address, > length as per the hardware programming guide. For transfer using BEI, > multiple I2C messages may necessitate the preparation of config, go, > and tx DMA TREs. However, a channel TRE size of 64 is often insufficient, > potentially leading to failures due to inadequate memory space. > > Adjust the channel TRE size through the device tree. > The default size is 64, but clients can modify this value based on > their heigher channel TRE size requirements. > > Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu(a)quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 132 +++++++++++++-------------- > 1 file changed, 66 insertions(+), 66 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 3d8410683402..c7c0e15ff9d3 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1064,7 +1064,7 @@ > }; > > gpi_dma0: dma-controller@900000 { > - #dma-cells = <3>; > + #dma-cells = <4>; > compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; > reg = <0 0x00900000 0 0x60000>; > interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, > @@ -1114,8 +1114,8 @@ > "qup-memory"; > power-domains = <&rpmhpd SC7280_CX>; > required-opps = <&rpmhpd_opp_low_svs>; > - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, > - <&gpi_dma0 1 0 QCOM_GPI_I2C>; > + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C 64>, > + <&gpi_dma0 1 0 QCOM_GPI_I2C 64>; So everywhere is 64, thus this is fixed. Deduce it from the compatible Best regards, Krzysztof

7 months, 3 weeks

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Re: [PATCH 9/9] drm/panfrost: Explicitly clean up panfrost fence

by Christian König

Am 15.10.24 um 01:31 schrieb Adrián Larumbe: > Doesn't make any functional difference because generic dma_fence is the > first panfrost_fence structure member, but I guess it doesn't hurt either. As discussed with Sima we want to push into the exactly opposite direction because that requires that the panfrost module stays loaded as long as fences are around. So clearly a NAK to this one here. Rather document on the structure that the dma_fence structure must be the first member. Regards, Christian. > Signed-off-by: Adrián Larumbe <adrian.larumbe(a)collabora.com> > --- > drivers/gpu/drm/panfrost/panfrost_job.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/gpu/drm/panfrost/panfrost_job.c b/drivers/gpu/drm/panfrost/panfrost_job.c > index 5d83c6a148ec..fa219f719bdc 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_job.c > +++ b/drivers/gpu/drm/panfrost/panfrost_job.c > @@ -85,9 +85,15 @@ static const char *panfrost_fence_get_timeline_name(struct dma_fence *fence) > } > } > > +static void panfrost_fence_release(struct dma_fence *fence) > +{ > + kfree(to_panfrost_fence(fence)); > +} > + > static const struct dma_fence_ops panfrost_fence_ops = { > .get_driver_name = panfrost_fence_get_driver_name, > .get_timeline_name = panfrost_fence_get_timeline_name, > + .release = panfrost_fence_release, > }; > > static struct dma_fence *panfrost_fence_create(struct panfrost_device *pfdev, int js_num)

7 months, 3 weeks

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Re: [PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property

by Vinod Koul

On 15-10-24, 17:37, Jyothi Kumar Seerapu wrote: > When high performance with multiple i2c messages in a single transfer > is required, employ Block Event Interrupt (BEI) to trigger interrupts > after specific messages transfer and the last message transfer, > thereby reducing interrupts. > > For each i2c message transfer, a series of Transfer Request Elements(TREs) > must be programmed, including config tre for frequency configuration, > go tre for holding i2c address and dma tre for holding dma buffer address, > length as per the hardware programming guide. For transfer using BEI, > multiple I2C messages may necessitate the preparation of config, go, > and tx DMA TREs. However, a channel TRE size of 64 is often insufficient, > potentially leading to failures due to inadequate memory space. > > Add additional argument to dma-cell property for channel TRE size. > With this, adjust the channel TRE size via the device tree. > The default size is 64, but clients can modify this value based on > their specific requirements. > > Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu(a)quicinc.com> > --- > Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml > index 4df4e61895d2..002495921643 100644 > --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml > +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml > @@ -54,14 +54,16 @@ properties: > maxItems: 13 > > "#dma-cells": > - const: 3 > + minItems: 3 > + maxItems: 4 > description: > > DMA clients must use the format described in dma.txt, giving a phandle > - to the DMA controller plus the following 3 integer cells: > + to the DMA controller plus the following 4 integer cells: > - channel: if set to 0xffffffff, any available channel will be allocated > for the client. Otherwise, the exact channel specified will be used. > - seid: serial id of the client as defined in the SoC documentation. > - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h > + - channel-tre-size: size of the channel TRE (transfer ring element) This is a firmware /software property, why should this be in hardware description? -- ~Vinod

7 months, 3 weeks

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Re: [PATCH v1 00/10] Add MediaTek ISP7 camera system driver

by Nicolas Dufresne

Hi, Le mercredi 09 octobre 2024 à 19:15 +0800, Shu-hsiang Yang a écrit : > Based on linux-next/master, tag: next-20241008 > > The patch set adds the MediaTek ISP7.x camera system hardware driver. > > This driver sets up ISP hardware, handles interrupts, and initializes > V4L2 device nodes and functions. Moreover, implement V4L2 standard > video driver that utilizes media framework APIs. It also connects > the sensors and ISP, bridging with the seninf interface. Communicate > with SCP co-processor to compose ISP registers in the firmware. Thanks for this work. If I read you correctly, this will depends on an scp firmware update. Its probably early at rev1, but we appreciate if you can cross- reference your associated linux-firmware submission (or document which MT flavour of SCP firmware) contains this support already. For ISP drivers reviewers, we have the experience with SCP that the IPC is not versioned, making it difficult to maintain backward compatibility. Won't matter until this is merged, but be aware that unless this SCP IPC design issue has been fixed, any change to the -if headers means a modification to the SCP has been made, and often we have had to ask MTK to revisit the firmware code to unbreak backward compatibility. If this specific part of the SCP IPC is versioned, please let us know. I don't want this to be alarming message, just something we need to collectively be aware of not to break userspace, which may not update their firmwares in lock step with the kernel. regards, Nicolas p.s. for those new to MTK architecture, the SCP firmware provides services to everything multimedia in the platform, including CODECs, color converter and scalers, etc. > > These patches include CSI received data from sensors, sensor interface > bridge, raw/YUV image pre-processing, ISP utility and ISP control parts. > > Thank you for reviewing these patches. > > Shu-hsiang Yang (10): > dt-bindings: media: mediatek: add camsys device > media: platform: mediatek: add seninf controller > media: platform: mediatek: add isp_7x seninf unit > media: platform: mediatek: add isp_7x cam-raw unit > media: platform: mediatek: add isp_7x camsys unit > media: platform: mediatek: add isp_7x utility > media: platform: mediatek: add isp_7x video ops > media: platform: mediatek: add isp_7x state ctrl > media: platform: mediatek: add isp_7x build config > uapi: linux: add mediatek isp_7x camsys user api > > .../media/mediatek/mediatek,cam-raw.yaml | 169 + > .../media/mediatek/mediatek,cam-yuv.yaml | 148 + > .../media/mediatek/mediatek,camisp.yaml | 71 + > .../media/mediatek/mediatek,seninf-core.yaml | 106 + > .../media/mediatek/mediatek,seninf.yaml | 88 + > drivers/media/platform/mediatek/Kconfig | 1 + > drivers/media/platform/mediatek/Makefile | 2 + > drivers/media/platform/mediatek/isp/Kconfig | 21 + > .../platform/mediatek/isp/isp_7x/Makefile | 7 + > .../mediatek/isp/isp_7x/camsys/Makefile | 16 + > .../isp_7x/camsys/kd_imgsensor_define_v4l2.h | 87 + > .../mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.c | 1797 ++++++ > .../mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.h | 140 + > .../isp/isp_7x/camsys/mtk_cam-debug.c | 1271 ++++ > .../isp/isp_7x/camsys/mtk_cam-debug.h | 273 + > .../mediatek/isp/isp_7x/camsys/mtk_cam-defs.h | 168 + > .../isp/isp_7x/camsys/mtk_cam-dmadbg.h | 721 +++ > .../isp/isp_7x/camsys/mtk_cam-feature.c | 40 + > .../isp/isp_7x/camsys/mtk_cam-feature.h | 26 + > .../mediatek/isp/isp_7x/camsys/mtk_cam-fmt.h | 87 + > .../mediatek/isp/isp_7x/camsys/mtk_cam-ipi.h | 233 + > .../isp/isp_7x/camsys/mtk_cam-meta-mt8188.h | 2436 ++++++++ > .../isp/isp_7x/camsys/mtk_cam-plat-util.c | 207 + > .../isp/isp_7x/camsys/mtk_cam-plat-util.h | 16 + > .../mediatek/isp/isp_7x/camsys/mtk_cam-pool.c | 393 ++ > .../mediatek/isp/isp_7x/camsys/mtk_cam-pool.h | 28 + > .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.c | 5359 +++++++++++++++++ > .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.h | 325 + > .../isp/isp_7x/camsys/mtk_cam-raw_debug.c | 403 ++ > .../isp/isp_7x/camsys/mtk_cam-raw_debug.h | 39 + > .../isp/isp_7x/camsys/mtk_cam-regs-mt8188.h | 382 ++ > .../isp/isp_7x/camsys/mtk_cam-seninf-def.h | 193 + > .../isp/isp_7x/camsys/mtk_cam-seninf-drv.c | 1741 ++++++ > .../isp/isp_7x/camsys/mtk_cam-seninf-drv.h | 16 + > .../isp/isp_7x/camsys/mtk_cam-seninf-hw.h | 120 + > .../isp/isp_7x/camsys/mtk_cam-seninf-if.h | 28 + > .../isp/isp_7x/camsys/mtk_cam-seninf-regs.h | 40 + > .../isp/isp_7x/camsys/mtk_cam-seninf-route.c | 356 ++ > .../isp/isp_7x/camsys/mtk_cam-seninf-route.h | 23 + > .../isp/isp_7x/camsys/mtk_cam-seninf.h | 170 + > .../isp/isp_7x/camsys/mtk_cam-timesync.c | 125 + > .../isp/isp_7x/camsys/mtk_cam-timesync.h | 12 + > .../isp/isp_7x/camsys/mtk_cam-ufbc-def.h | 59 + > .../isp/isp_7x/camsys/mtk_cam-video.c | 1817 ++++++ > .../isp/isp_7x/camsys/mtk_cam-video.h | 224 + > .../mediatek/isp/isp_7x/camsys/mtk_cam.c | 4168 +++++++++++++ > .../mediatek/isp/isp_7x/camsys/mtk_cam.h | 733 +++ > .../isp_7x/camsys/mtk_camera-v4l2-controls.h | 65 + > .../isp_7x/camsys/mtk_csi_phy_2_0/Makefile | 5 + > .../mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h | 911 +++ > .../mtk_cam-seninf-csi0-cphy.h | 69 + > .../mtk_cam-seninf-csi0-dphy.h | 139 + > .../mtk_cam-seninf-hw_phy_2_0.c | 2879 +++++++++ > .../mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h | 257 + > .../mtk_cam-seninf-seninf1-csi2.h | 415 ++ > .../mtk_cam-seninf-seninf1-mux.h | 147 + > .../mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h | 47 + > .../mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h | 49 + > .../mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h | 99 + > include/uapi/linux/mtkisp_camsys.h | 227 + > 60 files changed, 30194 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml > create mode 100644 drivers/media/platform/mediatek/isp/Kconfig > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/Makefile > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/Makefile > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/kd_imgsensor_define_v4l2.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ctrl.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-debug.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-debug.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-defs.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-dmadbg.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-feature.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-fmt.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ipi.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-meta-mt8188.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-plat-util.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-plat-util.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-pool.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-pool.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-regs-mt8188.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-def.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-drv.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-hw.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-if.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-regs.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf-route.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-seninf.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-timesync.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-timesync.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-ufbc-def.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-video.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-cphy.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-dphy.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-csi2.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-mux.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h > create mode 100644 include/uapi/linux/mtkisp_camsys.h >

7 months, 3 weeks

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Re: [PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property

by Rob Herring

On Tue, Oct 15, 2024 at 05:37:46PM +0530, Jyothi Kumar Seerapu wrote: > When high performance with multiple i2c messages in a single transfer > is required, employ Block Event Interrupt (BEI) to trigger interrupts > after specific messages transfer and the last message transfer, > thereby reducing interrupts. > > For each i2c message transfer, a series of Transfer Request Elements(TREs) > must be programmed, including config tre for frequency configuration, > go tre for holding i2c address and dma tre for holding dma buffer address, > length as per the hardware programming guide. For transfer using BEI, > multiple I2C messages may necessitate the preparation of config, go, > and tx DMA TREs. However, a channel TRE size of 64 is often insufficient, > potentially leading to failures due to inadequate memory space. > > Add additional argument to dma-cell property for channel TRE size. No such property 'dma-cell' > With this, adjust the channel TRE size via the device tree. > The default size is 64, but clients can modify this value based on > their specific requirements. > > Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu(a)quicinc.com> > --- > Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml > index 4df4e61895d2..002495921643 100644 > --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml > +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml > @@ -54,14 +54,16 @@ properties: > maxItems: 13 > > "#dma-cells": > - const: 3 > + minItems: 3 > + maxItems: 4 > description: > > DMA clients must use the format described in dma.txt, giving a phandle > - to the DMA controller plus the following 3 integer cells: > + to the DMA controller plus the following 4 integer cells: > - channel: if set to 0xffffffff, any available channel will be allocated > for the client. Otherwise, the exact channel specified will be used. > - seid: serial id of the client as defined in the SoC documentation. > - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h > + - channel-tre-size: size of the channel TRE (transfer ring element) > > iommus: > maxItems: 1 > -- > 2.17.1 >

7 months, 3 weeks

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Re: [PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property

by Krzysztof Kozlowski

On 15/10/2024 14:07, Jyothi Kumar Seerapu wrote: > When high performance with multiple i2c messages in a single transfer > is required, employ Block Event Interrupt (BEI) to trigger interrupts > after specific messages transfer and the last message transfer, > thereby reducing interrupts. > > For each i2c message transfer, a series of Transfer Request Elements(TREs) > must be programmed, including config tre for frequency configuration, > go tre for holding i2c address and dma tre for holding dma buffer address, > length as per the hardware programming guide. For transfer using BEI, > multiple I2C messages may necessitate the preparation of config, go, > and tx DMA TREs. However, a channel TRE size of 64 is often insufficient, > potentially leading to failures due to inadequate memory space. Please kindly test the patches before you sent them. Upstream is not a testing service. Best regards, Krzysztof

7 months, 3 weeks

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Re: [PATCH v1 1/5] dt-bindings: dmaengine: qcom: gpi: Add additional arg to dma-cell property

by Rob Herring (Arm)

On Tue, 15 Oct 2024 17:37:46 +0530, Jyothi Kumar Seerapu wrote: > When high performance with multiple i2c messages in a single transfer > is required, employ Block Event Interrupt (BEI) to trigger interrupts > after specific messages transfer and the last message transfer, > thereby reducing interrupts. > > For each i2c message transfer, a series of Transfer Request Elements(TREs) > must be programmed, including config tre for frequency configuration, > go tre for holding i2c address and dma tre for holding dma buffer address, > length as per the hardware programming guide. For transfer using BEI, > multiple I2C messages may necessitate the preparation of config, go, > and tx DMA TREs. However, a channel TRE size of 64 is often insufficient, > potentially leading to failures due to inadequate memory space. > > Add additional argument to dma-cell property for channel TRE size. > With this, adjust the channel TRE size via the device tree. > The default size is 64, but clients can modify this value based on > their specific requirements. > > Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu(a)quicinc.com> > --- > Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/dma/qcom,gpi.yaml: properties:#dma-cells: 'minItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf'] from schema $id: http://devicetree.org/meta-schemas/core.yaml# /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/dma/qcom,gpi.yaml: properties:#dma-cells: 'maxItems' is not one of ['description', 'deprecated', 'const', 'enum', 'minimum', 'maximum', 'multipleOf', 'default', '$ref', 'oneOf'] from schema $id: http://devicetree.org/meta-schemas/core.yaml# doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/202410151207… The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema.

7 months, 3 weeks

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Re: [PATCH v2] dma-buf: fix S_IRUGO to 0444, block comments, func declaration

by John Stultz

On Sat, Oct 5, 2024 at 11:10 AM Pintu Kumar <quic_pintu(a)quicinc.com> wrote: > > These warnings/errors are reported by checkpatch. > Fix them with minor changes to make it clean. > No other functional changes. > > WARNING: Block comments use * on subsequent lines > + /* only support discovering the end of the buffer, > + but also allow SEEK_SET to maintain the idiomatic > > WARNING: Block comments use a trailing */ on a separate line > + SEEK_END(0), SEEK_CUR(0) pattern */ > > WARNING: Block comments use a trailing */ on a separate line > + * before passing the sgt back to the exporter. */ > > ERROR: "foo * bar" should be "foo *bar" > +static struct sg_table * __map_dma_buf(struct dma_buf_attachment *attach, > > WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. > + d = debugfs_create_file("bufinfo", S_IRUGO, dma_buf_debugfs_dir, > > total: 1 errors, 4 warnings, 1746 lines checked > > Signed-off-by: Pintu Kumar <quic_pintu(a)quicinc.com> Looks ok to me. Thanks for sending these cleanups! Acked-by: John Stultz <jstultz(a)google.com>

7 months, 4 weeks

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Notes from the XDC 2024 "universal buffer allocator" workshop

by Laurent Pinchart

Hello, We held a workshop at XDC 2024 titled "Towards a universal buffer allocator for Linux", whose abstract was as follows: Buffer allocation for media contents, despite being required for any framework or application dealing with image capture, processing, decoding, encoding, rendering and display, remains an area plagued by many unsolved problems. Over time improvements have been made to APIs for buffer allocation, both on the kernel side (standardization of the DRM dumb buffer API, or DMA heaps, to name a few) and in userspace (most notably with GBM, and the buffer management API in Vulkan), or for specific use cases (e.g. gralloc in Android). Unfortunately, no universal solution exists to allocate buffers shared by multiple devices. This is hindering interoperability and forces userspace to pile hacks and workarounds. (https://indico.freedesktop.org/event/6/contributions/395/). Here are the raw notes from the workshop. XDC 2024 - Buffer allocation workshop ===================================== Attendees: - Erico Nunes <ernunes(a)redhat.com> - James Jones <jajones(a)nvidia.com> - Laurent Pinchart <laurent.pinchart(a)ideasonboard.com> - Nicolas Dufresne <nicolas(a)collabora.com> - Yunxiang (Teddy) Li <yunxiang.li(a)amd.com> Relevant content: - XDC 2016: https://www.x.org/wiki/Events/XDC2016/Program/Unix_Device_Memory_Allocation… - XDC 2020: https://lpc.events/event/9/contributions/615/attachments/704/1301/XDC_2020_… Discussions ----------- NICs are relevant to the discussion, but likely only on large servers. The proposal needs to accomodate that. Nicolas asked about support for the CPU as a device. A lot of pipelines are hybrid, with CPU processing and dedicated hardware processing. James said previous proposals were able to support the CPU as a device. The last proposal was focussed on usages, so could support CPUs. Demi things this could be viewed as in a similar way as type checking in compilers, which have to resolve constraints. Nicolas is annoyed that we force applications to make a decision, requiring them to go the hard route of reallocation if they get it wrong. Some of the parameters are the MMU configuration, which can't be changed afterwards in Linux. Demi said that there could be cases where the fastest thing to do is to use shadow memory and copy. Nicolas said the first question that would come back is if this is something userspace should decide. Yunxiang asked if we're looking at designing a kernel interface to convey constraints. Nicolas said some kernel APIs expose some constraints. For instance, V4L2 allows discovering some stride constraints. Yunxiang thinks constraints won't be able to scale. Capabilities would be better. The difference is that the hardware device can have lots of constraints, but could more easily say some of the things it can do. Adding a new capability later wouldn't break anything, but adding a new constraint would require all components to understand it. James said the latest proposal handled constraints in a forward-compatible way with versioned constraints. Demi prefers the capabilities approach. Yunxiang said devices could expose which memory they can access. Nicolas said that in GStreamer, the current approach is trial and error. Capabilities would reduce trial and error. Everybody has hacks on top. James is instead bringing a formula that solves this. As soon as each of the nodes involved can be identified (which GStreamer can do now), we can calculate and combine but can't sustain adding capabilities. Liviu said GStreamer could tell which capabilities it supports, and push hardware vendors to comply with that. If the hardware is not compatible, GStreamer would provide converters. Nicolas said buffer sharing is a trade-off. We will find things that won't break it but will make it slower. Demi said that cache-incoherent DMA will usually have higher bandwidth than cache-coherent DMA, unless all the components share the same cache. Discussion followed on capabilities vs. constraints. It's partly a vocabulary matter. The first proposal from James was using the word capability. Constraints in the last proposal describe what a device can do. Nicolas has only stride and number of planes as constraints in GStreamer. James' mechanism has support for much more. Yunxiang asked if we can include the pixel format as constraints. James said we first have to resolve formats and modifiers, and then handle allocation constraints. Yunxiang thinks the allocator should also take care of the format. Nicolas said that when using a tiling modifier, we already reduce the scope of incompatibilities. When using e.g. an Intel tiling modifier, there's a bigger guarantee that the devices that support it will be able to inter-operate as they're designed for that purpose. Demi said it should be possible to validate parameters for buffers without being Mesa. The format modifiers are way too opaque. James said that for each format we need to query possible modifiers, and for each format+modifier we need to query constraints. Modifiers are mostly considered opaque to applications, constraints are semi-opaque, and formats are not opaque. The problem that remains hard to James is when it comes to locality, how do we say "local to a device" ? There's no serializable representation of a device. Nicolas says that as soon as it stays in the graphics stack, the stack will hide the problem from applications. A sysfs path could be used on Linux to identify a device. James asked how an application would be allowed to allocate buffers from e.g. a DRI device, if the allocator library told it that the allocation needs to be done there. This starts becoming a permission issue or a logind issue. Passing fds could help, but when sitting on top of GL, we have no way to get an fd. Nicolas said Vulkan should be OK, but GL is dead. Nicolas asked why it would be useful to get access to fds. James said that at the bottom of the problem we have the question of which fd we send an ioctl to to allocate memory. We could start small to have something and break the chicken and egg problem. James thought about using GBM to start with, but this isn't good for GStreamer. James and Nicolas thought that kernel drivers would register dmabuf heaps. One issue with dmabuf heaps today is that allocation isn't tracked, so we bypass cgroups. DRM and V4L2 have the same issue, offering an infinite amount of memory. logind has a responsibility of not making it worse, so didn't allow access to dmabuf heaps. The problem needs to be fixed in the kernel first, adding accounting. This would then be an incentive to abandon device-specific allocation APIs, as memory accounting would come for free when using dmabuf heaps. Nicolas wonders why the obvious path forward of implementing heaps for devices that have specific constraints didn't happen. James thinks people may just have been too busy. Demi brought up the VFIO case. The hardware device may not be managed by the kernel, it may be managed by userspace, or passed to a guest. Capabilities for those devices can't come from a kernel device. James said the key is communicating the constraints in a serializable way. Allocation would involve passing dmabufs between guests and hosts. Allocation from DMA heaps and from subsystem-specific APIs will coexist for a long time. This needs to be abstracted in a userspace library, so that the underlying allocators can evolve. Demi asked if GBM is needed when using Vulkan. Internally in mesa, everything uses GBM for allocation. James said it's a good argument to ask why not using Vulkan only. If we decide to use GBM to bootstrap this evolution, and GBM allocates for a specific device, then it doesn't seem to be a good fit. We don't want to add support for system memory allocation to GBM. Erico said that there's a use case for GBM even when using Vulkan when there's a separate display device that has no Vulkan implementation. We need an iterative approach. For instance a simple useful improvement would be to expose stride constraints on DRM devices. Conclusions ----------- - We need some library (existing or new one) - We need some API - We need someone to bootstrap this - We need a more iterative approach Action points ------------- - Add memory accounting to DMA heaps - Push drivers to implement their own heaps to replace subsystem allocation APIs -- Regards, Laurent Pinchart

7 months, 4 weeks

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Re: [PATCH v1 04/10] media: platform: mediatek: add isp_7x cam-raw unit

by AngeloGioacchino Del Regno

Il 09/10/24 13:15, Shu-hsiang Yang ha scritto: > Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv > modules. Key functionalities include data processing, V4L2 integration, > resource management, debug support, and various control operations. > Additionally, IRQ handling, platform device management, and MediaTek > ISP DMA format support are also included. > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang(a)mediatek.com> > --- > .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.c | 5359 +++++++++++++++++ > .../mediatek/isp/isp_7x/camsys/mtk_cam-raw.h | 325 + > .../isp/isp_7x/camsys/mtk_cam-raw_debug.c | 403 ++ > .../isp/isp_7x/camsys/mtk_cam-raw_debug.h | 39 + > .../isp_7x/camsys/mtk_camera-v4l2-controls.h | 65 + > 5 files changed, 6191 insertions(+) > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw_debug.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_camera-v4l2-controls.h > > diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c > new file mode 100644 > index 000000000000..c025f53c952d > --- /dev/null > +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_cam-raw.c > @@ -0,0 +1,5359 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// > +// Copyright (c) 2022 MediaTek Inc. > + > +#include <linux/clk.h> > +#include <linux/interrupt.h> > +#include <linux/iopoll.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/of_platform.h> > +#include <linux/platform_device.h> > +#include <linux/pm_runtime.h> > +#include <linux/vmalloc.h> > +#include <linux/videodev2.h> > +#include <linux/suspend.h> > +#include <linux/rtc.h> > + > +#include <media/v4l2-device.h> > +#include <media/v4l2-event.h> > +#include <media/v4l2-ioctl.h> > +#include <media/v4l2-subdev.h> > + > +#include <soc/mediatek/smi.h> > + > +#include "mtk_cam.h" > +#include "mtk_cam-feature.h" > +#include "mtk_cam-raw.h" > + > +#include "mtk_cam-regs-mt8188.h" > + > +#include "mtk_cam-video.h" > +#include "mtk_cam-seninf-if.h" > +#include "mtk_camera-v4l2-controls.h" > + > +#include "mtk_cam-dmadbg.h" > +#include "mtk_cam-raw_debug.h" > + > +static unsigned int debug_raw; > +module_param(debug_raw, uint, 0644); > +MODULE_PARM_DESC(debug_raw, "activates debug info"); > + > +static int debug_raw_num = -1; > +module_param(debug_raw_num, int, 0644); > +MODULE_PARM_DESC(debug_raw_num, "debug: num of used raw devices"); > + > +static int debug_pixel_mode = -1; > +module_param(debug_pixel_mode, int, 0644); > +MODULE_PARM_DESC(debug_pixel_mode, "debug: pixel mode"); > + > +static int debug_clk_idx = -1; > +module_param(debug_clk_idx, int, 0644); > +MODULE_PARM_DESC(debug_clk_idx, "debug: clk idx"); > + > +static int debug_dump_fbc; > +module_param(debug_dump_fbc, int, 0644); > +MODULE_PARM_DESC(debug_dump_fbc, "debug: dump fbc"); > + In addition to the first review that I gave you on patch [02/10]: please drop all those module parameters. If you want debug switches, use debugfs instead. Regards, Angelo

8 months

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Re: [PATCH v2] dma-buf: fix S_IRUGO to 0444, block comments, func declaration

by Pintu Agarwal

Hi, On Sat, 5 Oct 2024 at 23:40, Pintu Kumar <quic_pintu(a)quicinc.com> wrote: > > These warnings/errors are reported by checkpatch. > Fix them with minor changes to make it clean. > No other functional changes. > > WARNING: Block comments use * on subsequent lines > + /* only support discovering the end of the buffer, > + but also allow SEEK_SET to maintain the idiomatic > > WARNING: Block comments use a trailing */ on a separate line > + SEEK_END(0), SEEK_CUR(0) pattern */ > > WARNING: Block comments use a trailing */ on a separate line > + * before passing the sgt back to the exporter. */ > > ERROR: "foo * bar" should be "foo *bar" > +static struct sg_table * __map_dma_buf(struct dma_buf_attachment *attach, > > WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. > + d = debugfs_create_file("bufinfo", S_IRUGO, dma_buf_debugfs_dir, > > total: 1 errors, 4 warnings, 1746 lines checked > > Signed-off-by: Pintu Kumar <quic_pintu(a)quicinc.com> > > --- > Changes in V1 suggested by Sumit Semwal: > Change commit title, and mention exact reason of fix in commit log. > V1: https://lore.kernel.org/all/CAOuPNLg1=YCUFXW-76A_gZm_PE1MFSugNvg3dEdkfujXV_… > --- > drivers/dma-buf/dma-buf.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c > index 8892bc701a66..2e63d50e46d3 100644 > --- a/drivers/dma-buf/dma-buf.c > +++ b/drivers/dma-buf/dma-buf.c > @@ -176,8 +176,9 @@ static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence) > dmabuf = file->private_data; > > /* only support discovering the end of the buffer, > - but also allow SEEK_SET to maintain the idiomatic > - SEEK_END(0), SEEK_CUR(0) pattern */ > + * but also allow SEEK_SET to maintain the idiomatic > + * SEEK_END(0), SEEK_CUR(0) pattern. > + */ > if (whence == SEEK_END) > base = dmabuf->size; > else if (whence == SEEK_SET) > @@ -782,13 +783,14 @@ static void mangle_sg_table(struct sg_table *sg_table) > /* To catch abuse of the underlying struct page by importers mix > * up the bits, but take care to preserve the low SG_ bits to > * not corrupt the sgt. The mixing is undone in __unmap_dma_buf > - * before passing the sgt back to the exporter. */ > + * before passing the sgt back to the exporter. > + */ > for_each_sgtable_sg(sg_table, sg, i) > sg->page_link ^= ~0xffUL; > #endif > > } > -static struct sg_table * __map_dma_buf(struct dma_buf_attachment *attach, > +static struct sg_table *__map_dma_buf(struct dma_buf_attachment *attach, > enum dma_data_direction direction) > { > struct sg_table *sg_table; > @@ -1694,7 +1696,7 @@ static int dma_buf_init_debugfs(void) > > dma_buf_debugfs_dir = d; > > - d = debugfs_create_file("bufinfo", S_IRUGO, dma_buf_debugfs_dir, > + d = debugfs_create_file("bufinfo", 0444, dma_buf_debugfs_dir, > NULL, &dma_buf_debug_fops); > if (IS_ERR(d)) { > pr_debug("dma_buf: debugfs: failed to create node bufinfo\n"); > -- Pushed V2 here. Any further comment on this ? Thanks, Pintu

8 months

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Re: [PATCH 2/3] dma-buf/heaps: replace kmap_atomic with kmap_local_page

by T.J. Mercier

On Tue, Oct 1, 2024 at 7:51 PM Pintu Kumar <quic_pintu(a)quicinc.com> wrote: > > Use of kmap_atomic/kunmap_atomic is deprecated, use > kmap_local_page/kunmap_local instead. > > This is reported by checkpatch. > Also fix repeated word issue. > > WARNING: Deprecated use of 'kmap_atomic', prefer 'kmap_local_page' instead > + void *vaddr = kmap_atomic(page); > > WARNING: Deprecated use of 'kunmap_atomic', prefer 'kunmap_local' instead > + kunmap_atomic(vaddr); > > WARNING: Possible repeated word: 'by' > + * has been killed by by SIGKILL > > total: 0 errors, 3 warnings, 405 lines checked > > Signed-off-by: Pintu Kumar <quic_pintu(a)quicinc.com> Reviewed-by: T.J. Mercier <tjmercier(a)google.com> The Android kernels have been doing this for over a year, so should be pretty well tested at this point: https://r.android.com/c/kernel/common/+/2500840 > --- > drivers/dma-buf/heaps/cma_heap.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/dma-buf/heaps/cma_heap.c b/drivers/dma-buf/heaps/cma_heap.c > index 93be88b805fe..8c55431cc16c 100644 > --- a/drivers/dma-buf/heaps/cma_heap.c > +++ b/drivers/dma-buf/heaps/cma_heap.c > @@ -309,13 +309,13 @@ static struct dma_buf *cma_heap_allocate(struct dma_heap *heap, > struct page *page = cma_pages; > > while (nr_clear_pages > 0) { > - void *vaddr = kmap_atomic(page); > + void *vaddr = kmap_local_page(page); > > memset(vaddr, 0, PAGE_SIZE); > - kunmap_atomic(vaddr); > + kunmap_local(vaddr); > /* > * Avoid wasting time zeroing memory if the process > - * has been killed by by SIGKILL > + * has been killed by SIGKILL. > */ > if (fatal_signal_pending(current)) > goto free_cma; > -- > 2.17.1 >

8 months

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Re: [PATCH v1 01/10] dt-bindings: media: mediatek: add camsys device

by Rob Herring

On Wed, Oct 09, 2024 at 07:15:42PM +0800, Shu-hsiang Yang wrote: > 1. Add camera isp7x module device document > 2. Add camera interface device document > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang(a)mediatek.com> > --- > .../media/mediatek/mediatek,cam-raw.yaml | 169 ++++++++++++++++++ > .../media/mediatek/mediatek,cam-yuv.yaml | 148 +++++++++++++++ > .../media/mediatek/mediatek,camisp.yaml | 71 ++++++++ > .../media/mediatek/mediatek,seninf-core.yaml | 106 +++++++++++ > .../media/mediatek/mediatek,seninf.yaml | 88 +++++++++ > 5 files changed, 582 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,camisp.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf-core.yaml > create mode 100644 Documentation/devicetree/bindings/media/mediatek/mediatek,seninf.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml > new file mode 100644 > index 000000000000..c709e4bf0a18 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-raw.yaml > @@ -0,0 +1,169 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (c) 2024 MediaTek Inc. > + > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek/mediatek,cam-raw.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: The cam-raw unit of MediaTek ISP system > + > +maintainers: > + - Shu-hsiang Yang <shu-hsiang.yang(a)mediatek.com> > + - Shun-yi Wang <shun-yi.wang(a)mediatek.com> > + - Teddy Chen <teddy.chen(a)mediatek.com> > + > +description: > + MediaTek cam-raw is the camera RAW processing unit in MediaTek SoC. > + > +properties: > + compatible: > + const: mediatek,cam-raw Compatibles should be SoC specific. > + > + "#address-cells": > + const: 2 > + > + "#size-cells": > + const: 2 Don't need these. You don't have any child nodes with addresses. > + > + reg: > + items: > + minItems: 2 > + maxItems: 4 Drop items. > + minItems: 1 > + maxItems: 2 You have to specify what each region is. Why does it vary? A h/w block either has register region or it doesn't. > + > + reg-names: > + minItems: 1 > + maxItems: 2 You must define the names. > + > + mediatek,cam-id: > + description: > + Describes the index of MediaTek cam-raw unit for ISP > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [0, 1, 2] No, we don't put module indices in DT. > + > + mediatek,larbs: > + description: > + Describes MediaTek bus infrastructure unit for ISP system. > + List of phandle to the local arbiters in the current SoCs. > + Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + minItems: 1 > + maxItems: 32 > + > + interrupts: > + minItems: 1 > + > + dma-ranges: > + description: > + Describes the address information of IOMMU mapping to memory. > + Defines six fields for the MediaTek IOMMU extended iova, pa, and size. > + minItems: 1 > + > + power-domains: > + minItems: 1 > + > + clocks: > + minItems: 4 > + maxItems: 16 You have to define what the clocks are. > + > + clock-names: > + minItems: 4 > + maxItems: 16 > + > + assigned-clocks: > + maxItems: 1 > + > + assigned-clock-parents: > + maxItems: 1 Drop. You don't need to document assigned-clocks. > + > + iommus: > + description: > + Points to the respective IOMMU block with master port as argument, see > + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. > + Ports are according to the HW. > + minItems: 1 > + maxItems: 32 > + > +required: > + - compatible > + - reg > + - reg-names > + - interrupts > + - power-domains > + - clocks > + - clock-names > + - iommus > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/power/mediatek,mt8188-power.h> > + #include <dt-bindings/clock/mediatek,mt8188-clk.h> > + #include <dt-bindings/memory/mediatek,mt8188-memory-port.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + cam_raw_a@16030000 { > + compatible = "mediatek,cam-raw"; > + reg = <0 0x16030000 0 0x8000>, > + <0 0x16038000 0 0x8000>; > + reg-names = "base", "inner_base"; > + mediatek,cam-id = <0>; > + mediatek,larbs = <&larb16a>; > + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH 0>; > + #address-cells = <2>; > + #size-cells = <2>; > + dma-ranges = <0x2 0x0 0x0 0x40000000 0x1 0x0>; > + power-domains = <&spm MT8188_POWER_DOMAIN_CAM_SUBA>; > + clocks = <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, > + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, > + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>, > + <&camsys CLK_CAM_MAIN_CAM>, > + <&camsys CLK_CAM_MAIN_CAMTG>, > + <&camsys_rawa CLK_CAM_RAWA_LARBX>, > + <&camsys_rawa CLK_CAM_RAWA_CAM>, > + <&camsys_rawa CLK_CAM_RAWA_CAMTG>, > + <&topckgen CLK_TOP_CAM>, > + <&topckgen CLK_TOP_CAMTG>, > + <&topckgen CLK_TOP_CAMTM>; > + clock-names = "camsys_cam2mm0_cgpdn", > + "camsys_cam2mm1_cgpdn", > + "camsys_cam2sys_cgpdn", > + "camsys_cam_cgpdn", > + "camsys_camtg_cgpdn", > + "camsys_rawa_larbx_cgpdn", > + "camsys_rawa_cam_cgpdn", > + "camsys_rawa_camtg_cgpdn", > + "topckgen_top_cam", > + "topckgen_top_camtg", > + "topckgen_top_camtm"; > + assigned-clocks = <&topckgen CLK_TOP_CAM>; > + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5>; > + iommus = <&vpp_iommu M4U_PORT_L16A_IMGO_R1>, > + <&vpp_iommu M4U_PORT_L16A_CQI_R1>, > + <&vpp_iommu M4U_PORT_L16A_CQI_R2>, > + <&vpp_iommu M4U_PORT_L16A_BPCI_R1>, > + <&vpp_iommu M4U_PORT_L16A_LSCI_R1>, > + <&vpp_iommu M4U_PORT_L16A_RAWI_R2>, > + <&vpp_iommu M4U_PORT_L16A_RAWI_R3>, > + <&vpp_iommu M4U_PORT_L16A_UFDI_R2>, > + <&vpp_iommu M4U_PORT_L16A_UFDI_R3>, > + <&vpp_iommu M4U_PORT_L16A_RAWI_R4>, > + <&vpp_iommu M4U_PORT_L16A_RAWI_R5>, > + <&vpp_iommu M4U_PORT_L16A_AAI_R1>, > + <&vpp_iommu M4U_PORT_L16A_UFDI_R5>, > + <&vpp_iommu M4U_PORT_L16A_FHO_R1>, > + <&vpp_iommu M4U_PORT_L16A_AAO_R1>, > + <&vpp_iommu M4U_PORT_L16A_TSFSO_R1>, > + <&vpp_iommu M4U_PORT_L16A_FLKO_R1>; > + }; > + }; > + > +... > diff --git a/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml > new file mode 100644 > index 000000000000..30dfd5e5ecb1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek/mediatek,cam-yuv.yaml Similar comments on the rest. Rob

8 months

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Re: [PATCH v1 02/10] media: platform: mediatek: add seninf controller

by AngeloGioacchino Del Regno

Il 09/10/24 13:15, Shu-hsiang Yang ha scritto: > Introduces support for the sensor interface in the MediaTek SoC, > with the focus on CSI and stream control. The key functionalities > include parameter control, metering and maintaining status information, > interrupt handling, and debugging. These features ensure effective > management and debugging of the camera sensor interface hardware. > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang(a)mediatek.com> > --- > .../isp_7x/camsys/mtk_csi_phy_2_0/Makefile | 5 + > .../mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h | 911 ++++++ > .../mtk_cam-seninf-csi0-cphy.h | 69 + > .../mtk_cam-seninf-csi0-dphy.h | 139 + > .../mtk_cam-seninf-hw_phy_2_0.c | 2879 +++++++++++++++++ > .../mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h | 257 ++ > .../mtk_cam-seninf-seninf1-csi2.h | 415 +++ > .../mtk_cam-seninf-seninf1-mux.h | 147 + > .../mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h | 47 + > .../mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h | 49 + > .../mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h | 99 + > 11 files changed, 5017 insertions(+) > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile The PHY driver should go to the PHY directory as a PHY driver - or at least part of this mtk_csi_phy_2_0 driver should go there. I see that this is tightly integrated with the rest of the code in seninf, but there seems to be many functions that are just handling a "real" PHY. > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-cphy.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-csi0-dphy.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-csi2.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1-mux.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-seninf1.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-tg1.h > create mode 100644 drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-top-ctrl.h > > diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile > new file mode 100644 > index 000000000000..e00b8d3904a9 > --- /dev/null > +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/Makefile > @@ -0,0 +1,5 @@ > +# SPDX-License-Identifier: GPL-2.0 > +# Copyright (C) 2022 MediaTek Inc. > + > +mtk-cam-isp-objs += \ > + mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.o > diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h > new file mode 100644 > index 000000000000..ec3c621d742a > --- /dev/null > +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-cammux.h > @@ -0,0 +1,911 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2022 MediaTek Inc. > + */ > + > +#ifndef __SENINF_CAM_MUX_H__ > +#define __SENINF_CAM_MUX_H__ > + > +#define SENINF_CAM_MUX_CTRL_0 0x0000 > +#define RG_SENINF_CAM_MUX0_SRC_SEL_SHIFT 0 > +#define RG_SENINF_CAM_MUX0_SRC_SEL_MASK (0xf << 0) For all definitions: drop _SHIFT and use the GENMASK(x,y) macro. #define RG_SENINF_CAM_MUX0_SRC_SEL GENMASK(7, 0) #define RG_SENINF_CAM_MUX1_SRC_SEL GENMASK(11, 8) etc. > +#define RG_SENINF_CAM_MUX1_SRC_SEL_SHIFT 8 > +#define RG_SENINF_CAM_MUX1_SRC_SEL_MASK (0xf << 8) > +#define RG_SENINF_CAM_MUX2_SRC_SEL_SHIFT 16 > +#define RG_SENINF_CAM_MUX2_SRC_SEL_MASK (0xf << 16) > +#define RG_SENINF_CAM_MUX3_SRC_SEL_SHIFT 24 > +#define RG_SENINF_CAM_MUX3_SRC_SEL_MASK (0xf << 24) ..snip.. > diff --git a/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c > new file mode 100644 > index 000000000000..f24d8a056d0e > --- /dev/null > +++ b/drivers/media/platform/mediatek/isp/isp_7x/camsys/mtk_csi_phy_2_0/mtk_cam-seninf-hw_phy_2_0.c > @@ -0,0 +1,2879 @@ > +// SPDX-License-Identifier: GPL-2.0 > +// Copyright (c) 2022 MediaTek Inc. > + > +#include <linux/module.h> > +#include <linux/delay.h> > + > +#include "../mtk_cam-seninf.h" > +#include "../mtk_cam-seninf-hw.h" > +#include "../mtk_cam-seninf-regs.h" > +#include "mtk_cam-seninf-top-ctrl.h" > +#include "mtk_cam-seninf-seninf1-mux.h" > +#include "mtk_cam-seninf-seninf1.h" > +#include "mtk_cam-seninf-seninf1-csi2.h" > +#include "mtk_cam-seninf-tg1.h" > +#include "mtk_cam-seninf-cammux.h" > +#include "mtk_cam-seninf-mipi-rx-ana-cdphy-csi0a.h" > +#include "mtk_cam-seninf-csi0-cphy.h" > +#include "mtk_cam-seninf-csi0-dphy.h" > +#include "../kd_imgsensor_define_v4l2.h" > + > +/* seninf cfg default, dts may override */ dts may override: for which reason? Why should DT override that? For which usecase? > +static struct mtk_cam_seninf_cfg _seninf_cfg = { > + .mux_num = 8, > + .seninf_num = 4, > + .cam_mux_num = 11, > + .pref_mux_num = 11, > +}; > + > +struct mtk_cam_seninf_cfg *g_seninf_cfg = &_seninf_cfg; That's unused. Drop. > + > +static inline void mtk_cam_seninf_set_di_ch_ctrl(void __iomem *pseninf, > + unsigned int stream_id, > + struct seninf_vc *vc) > +{ > + if (stream_id > 7) No magic numbers, please. #define SOMETHING 7 > + return; > + > + SENINF_BITS(pseninf, SENINF_CSI2_S0_DI_CTRL + (stream_id << 0x2), Is it me, or is SENINF_BITS() not defined?! > + RG_CSI2_DT_SEL, vc->dt); > + SENINF_BITS(pseninf, SENINF_CSI2_S0_DI_CTRL + (stream_id << 0x2), > + RG_CSI2_VC_SEL, vc->vc); > + SENINF_BITS(pseninf, SENINF_CSI2_S0_DI_CTRL + (stream_id << 0x2), > + RG_CSI2_DT_INTERLEAVE_MODE, 1); > + SENINF_BITS(pseninf, SENINF_CSI2_S0_DI_CTRL + (stream_id << 0x2), > + RG_CSI2_VC_INTERLEAVE_EN, 1); > + ..snip.. > +} > + > +int mtk_cam_seninf_init_iomem(struct seninf_ctx *ctx, void __iomem *if_base, > + void __iomem *ana_base) > +{ > + u32 i; > + > + ctx->reg_ana_csi_rx[CSI_PORT_0] = Please don't use "a = b = c" assignments. In this case, that impacts on human readability. > + ctx->reg_ana_csi_rx[CSI_PORT_0A] = ana_base + 0; > + ctx->reg_ana_csi_rx[CSI_PORT_0B] = ana_base + 0x1000; Again, no magic numbers please. #define SOMETHING 0x1000 > + > + ctx->reg_ana_csi_rx[CSI_PORT_1] = > + ctx->reg_ana_csi_rx[CSI_PORT_1A] = ana_base + 0x4000; > + ctx->reg_ana_csi_rx[CSI_PORT_1B] = ana_base + 0x5000; ..snip.. > + return 0; > +} > + > +int mtk_cam_seninf_init_port(struct seninf_ctx *ctx, int port) > +{ > + u32 port_num; > + > + if (port >= CSI_PORT_0A) > + port_num = (port - CSI_PORT_0) >> 1; I think that you really want to use bitfield.h macros to simplify this. > + else > + port_num = port; > + > + ctx->port = port; > + ctx->port_num = port_num; > + ctx->port_a = CSI_PORT_0A + (port_num << 1); > + ctx->port_b = ctx->port_a + 1; > + ctx->is_4d1c = (port == port_num); > + > + switch (port) { > + case CSI_PORT_0: > + ctx->seninf_idx = SENINF_1; Is the CSI port to SENINF mapping supposed to be static and unchangeable? If yes, then you want to add that into an array indexed by CSI_PORT_xx, so that you end up doing ctx->seninf_idx = seninf_csi[port]; > + break; > + case CSI_PORT_0A: > + ctx->seninf_idx = SENINF_1; > + break; > + case CSI_PORT_0B: > + ctx->seninf_idx = SENINF_2; > + break; > + case CSI_PORT_1: > + ctx->seninf_idx = SENINF_3; > + break; > + case CSI_PORT_1A: > + ctx->seninf_idx = SENINF_3; > + break; > + case CSI_PORT_1B: > + ctx->seninf_idx = SENINF_4; > + break; > + case CSI_PORT_2: > + ctx->seninf_idx = SENINF_5; > + break; > + case CSI_PORT_2A: > + ctx->seninf_idx = SENINF_5; > + break; > + case CSI_PORT_2B: > + ctx->seninf_idx = SENINF_6; > + break; > + case CSI_PORT_3: > + ctx->seninf_idx = SENINF_7; > + break; > + case CSI_PORT_3A: > + ctx->seninf_idx = SENINF_7; > + break; > + case CSI_PORT_3B: > + ctx->seninf_idx = SENINF_8; > + break; > + default: > + dev_dbg(ctx->dev, "invalid port %d\n", port); > + return -EINVAL; > + } > + > + return 0; > +} > + > +int mtk_cam_seninf_is_cammux_used(struct seninf_ctx *ctx, int cam_mux) > +{ > + void __iomem *seninf_cam_mux = ctx->reg_if_cam_mux; > + u32 temp = SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_EN); Please, just use readl() or regmap_read() (preferrably the latter, and preferrably also define regmap reg fields). > + > + if (cam_mux >= _seninf_cfg.cam_mux_num) { > + dev_dbg(ctx->dev, > + "%s err cam_mux %d >= SENINF_CAM_MUX_NUM %d\n", > + __func__, cam_mux, _seninf_cfg.cam_mux_num); That shouldn't ever happen, should it. In that case, it's dev_err(), or even a WARN(), if necessary. > + > + return 0; > + } > + > + return !!(temp & (1 << cam_mux)); > +} > + > +int mtk_cam_seninf_cammux(struct seninf_ctx *ctx, int cam_mux) > +{ > + void __iomem *seninf_cam_mux = ctx->reg_if_cam_mux; > + u32 temp; > + > + if (cam_mux >= _seninf_cfg.cam_mux_num) { This check is duplicated across many functions... you want to do something such that it either never happens or it gets commonized. > + dev_dbg(ctx->dev, > + "%s err cam_mux %d >= SENINF_CAM_MUX_NUM %d\n", > + __func__, cam_mux, _seninf_cfg.cam_mux_num); > + > + return 0; You return 0, so there's no problem if this is the wrong cam_mux?!?!? > + } > + > + temp = SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_EN); > + SENINF_WRITE_REG(seninf_cam_mux, SENINF_CAM_MUX_EN, > + temp | (1 << cam_mux)); BIT(cam_mux) > + > + SENINF_WRITE_REG(seninf_cam_mux, SENINF_CAM_MUX_IRQ_STATUS, > + 3 << (cam_mux * 2)); /* clr irq */ > + > + dev_dbg(ctx->dev, "cam_mux %d EN 0x%x IRQ_EN 0x%x IRQ_STATUS 0x%x\n", > + cam_mux, SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_EN), > + SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_IRQ_EN), > + SENINF_READ_REG(seninf_cam_mux, SENINF_CAM_MUX_IRQ_STATUS)); > + > + return 0; > +} > + > + > +int mtk_cam_seninf_set_vc(struct seninf_ctx *ctx, u32 seninf_idx, > + struct seninf_vcinfo *vcinfo) > +{ > + void __iomem *seninf_csi2 = ctx->reg_if_csi2[seninf_idx]; > + int i; > + struct seninf_vc *vc; > + > + if (!vcinfo || !vcinfo->cnt) > + return 0; Does !vcinfo mean that Virtual Channel should not be set? Please add a comment explaining that. > + > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S0_DI_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S1_DI_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S2_DI_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S3_DI_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S4_DI_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S5_DI_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S6_DI_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_S7_DI_CTRL, 0); > + > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_CH0_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_CH1_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_CH2_CTRL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_CH3_CTRL, 0); > + > + for (i = 0; i < vcinfo->cnt; i++) { > + vc = &vcinfo->vc[i]; > + > + /* General Long Packet Data Types: 0x10-0x17 */ > + if (vc->dt >= 0x10 && vc->dt <= 0x17) { > + SENINF_BITS(seninf_csi2, SENINF_CSI2_OPT, > + RG_CSI2_GENERIC_LONG_PACKET_EN, 1); > + } > + > + mtk_cam_seninf_set_di_ch_ctrl(seninf_csi2, i, vc); > + } > + > + dev_dbg(ctx->dev, "DI_CTRL 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S0_DI_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S1_DI_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S2_DI_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S3_DI_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S4_DI_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S5_DI_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S6_DI_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_S7_DI_CTRL)); > + > + dev_dbg(ctx->dev, "CH_CTRL 0x%x 0x%x 0x%x 0x%x\n", > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_CH0_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_CH1_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_CH2_CTRL), > + SENINF_READ_REG(seninf_csi2, SENINF_CSI2_CH3_CTRL)); > + > + return 0; > +} > + ..snip.. > + > +static int csirx_phyA_power_on(struct seninf_ctx *ctx, u32 port_idx, int en) Please, lower case on all functions. csirx_phy_a_power_on(). Also, you want to split this function in two: one should be csirx_phy_a_power_off() and one for power_on(). static void csirx_phy_a_power_off(struct seninf_ctx *ctx, u32 port_idx) { > +{ > + void __iomem *base = ctx->reg_ana_csi_rx[port_idx]; > + > + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_L0_T0AB_EQ_OS_CAL_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_L1_T1AB_EQ_OS_CAL_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_L2_T1BC_EQ_OS_CAL_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_XX_T0BC_EQ_OS_CAL_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_XX_T0CA_EQ_OS_CAL_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_8, RG_CSI0_XX_T1CA_EQ_OS_CAL_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_0, RG_CSI0_BG_LPF_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_0, RG_CSI0_BG_CORE_EN, 0); > + usleep_range(200, 300); > + } static int csirx_phy_a_power_on(struct seninf_ctx *ctx, u32 port_idx) <-- NO int en { void *iomem base = ..... /* Power it off first to ... reset, I believe? */ csirx_phy_a_power_off(); power on sequence here return 0; } > + if (en) { > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_BG_CORE_EN, 1); > + usleep_range(30, 40); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_BG_LPF_EN, 1); > + udelay(1); > + SENINF_BITS(base, CDPHY_RX_ANA_8, > + RG_CSI0_L0_T0AB_EQ_OS_CAL_EN, 1); > + SENINF_BITS(base, CDPHY_RX_ANA_8, > + RG_CSI0_L1_T1AB_EQ_OS_CAL_EN, 1); > + SENINF_BITS(base, CDPHY_RX_ANA_8, > + RG_CSI0_L2_T1BC_EQ_OS_CAL_EN, 1); > + SENINF_BITS(base, CDPHY_RX_ANA_8, > + RG_CSI0_XX_T0BC_EQ_OS_CAL_EN, 1); > + SENINF_BITS(base, CDPHY_RX_ANA_8, > + RG_CSI0_XX_T0CA_EQ_OS_CAL_EN, 1); > + SENINF_BITS(base, CDPHY_RX_ANA_8, > + RG_CSI0_XX_T1CA_EQ_OS_CAL_EN, 1); > + udelay(1); > + } > + > + return 0; > +} > + > +static int apply_efuse_data(struct seninf_ctx *ctx) > +{ void __iomem *base; u32 m_csi_efuse = ctx->m_csi_efuse; u32 port; int ret; > + int ret = 0; > + void __iomem *base; > + u32 port; > + u32 m_csi_efuse = ctx->m_csi_efuse; > + > + if (m_csi_efuse == 0) { > + dev_dbg(ctx->dev, "No efuse data. Returned.\n"); > + return -1; > + } ..snip.. > + > + return ret; return 0; > +} > + > +static int csirx_phyA_init(struct seninf_ctx *ctx) > +{ > + u32 i, port; > + void __iomem *base; > + > + port = ctx->port; > + for (i = 0; i <= ctx->is_4d1c; i++) { Move the setup in a different function, then call it with something(port); if (is_4d1c) something(port_b); > + port = i ? ctx->port_b : ctx->port; > + base = ctx->reg_ana_csi_rx[port]; > + SENINF_BITS(base, CDPHY_RX_ANA_1, > + RG_CSI0_BG_LPRX_VTL_SEL, 0x4); > + SENINF_BITS(base, CDPHY_RX_ANA_1, > + RG_CSI0_BG_LPRX_VTH_SEL, 0x4); > + SENINF_BITS(base, CDPHY_RX_ANA_2, > + RG_CSI0_BG_ALP_RX_VTL_SEL, 0x4); > + SENINF_BITS(base, CDPHY_RX_ANA_2, > + RG_CSI0_BG_ALP_RX_VTH_SEL, 0x4); > + SENINF_BITS(base, CDPHY_RX_ANA_1, > + RG_CSI0_BG_VREF_SEL, 0x8); > + SENINF_BITS(base, CDPHY_RX_ANA_1, > + RG_CSI0_CDPHY_EQ_DES_VREF_SEL, 0x2); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_BW, 0x3); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_IS, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG1_EN, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR0, 0x0); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR1, 0x0); > + SENINF_BITS(base, CDPHY_RX_ANA_9, > + RG_CSI0_RESERVE, 0x3003); > + SENINF_BITS(base, CDPHY_RX_ANA_SETTING_0, > + CSR_CSI_RST_MODE, 0x2); > + > + SENINF_BITS(base, CDPHY_RX_ANA_2, > + RG_CSI0_L0P_T0A_HSRT_CODE, 0x10); > + SENINF_BITS(base, CDPHY_RX_ANA_2, > + RG_CSI0_L0N_T0B_HSRT_CODE, 0x10); > + SENINF_BITS(base, CDPHY_RX_ANA_3, > + RG_CSI0_L1P_T0C_HSRT_CODE, 0x10); > + SENINF_BITS(base, CDPHY_RX_ANA_3, > + RG_CSI0_L1N_T1A_HSRT_CODE, 0x10); > + SENINF_BITS(base, CDPHY_RX_ANA_4, > + RG_CSI0_L2P_T1B_HSRT_CODE, 0x10); > + SENINF_BITS(base, CDPHY_RX_ANA_4, > + RG_CSI0_L2N_T1C_HSRT_CODE, 0x10); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_CPHY_T0_CDR_FIRST_EDGE_EN, 0x0); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_CPHY_T1_CDR_FIRST_EDGE_EN, 0x0); > + SENINF_BITS(base, CDPHY_RX_ANA_2, > + RG_CSI0_CPHY_T0_CDR_SELF_CAL_EN, 0x0); > + SENINF_BITS(base, CDPHY_RX_ANA_2, > + RG_CSI0_CPHY_T1_CDR_SELF_CAL_EN, 0x0); > + > + SENINF_BITS(base, CDPHY_RX_ANA_6, > + RG_CSI0_CPHY_T0_CDR_CK_DELAY, 0x0); > + SENINF_BITS(base, CDPHY_RX_ANA_7, > + RG_CSI0_CPHY_T1_CDR_CK_DELAY, 0x0); > + SENINF_BITS(base, CDPHY_RX_ANA_6, > + RG_CSI0_CPHY_T0_CDR_AB_WIDTH, 0x9); > + SENINF_BITS(base, CDPHY_RX_ANA_6, > + RG_CSI0_CPHY_T0_CDR_BC_WIDTH, 0x9); > + SENINF_BITS(base, CDPHY_RX_ANA_6, > + RG_CSI0_CPHY_T0_CDR_CA_WIDTH, 0x9); > + SENINF_BITS(base, CDPHY_RX_ANA_7, > + RG_CSI0_CPHY_T1_CDR_AB_WIDTH, 0x9); > + SENINF_BITS(base, CDPHY_RX_ANA_7, > + RG_CSI0_CPHY_T1_CDR_BC_WIDTH, 0x9); > + SENINF_BITS(base, CDPHY_RX_ANA_7, > + RG_CSI0_CPHY_T1_CDR_CA_WIDTH, 0x9); > + > + dev_dbg(ctx->dev, "port:%d CDPHY_RX_ANA_0(0x%x)\n", > + port, SENINF_READ_REG(base, CDPHY_RX_ANA_0)); > + } > + > + apply_efuse_data(ctx); > + > + return 0; > +} > + > +static int csirx_dphy_init(struct seninf_ctx *ctx) > +{ > + void __iomem *base = ctx->reg_ana_dphy_top[ctx->port]; > + int settle_delay_dt, settle_delay_ck, hs_trail, hs_trail_en; > + int bit_per_pixel; u8 bits_per_pixel; > + u64 data_rate; > + > + settle_delay_dt = ctx->is_cphy ? ctx->core->cphy_settle_delay_dt : > + ctx->core->dphy_settle_delay_dt; Please set settle_delay_ck and hs_trail here. > + > + SENINF_BITS(base, DPHY_RX_DATA_LANE0_HS_PARAMETER, > + RG_CDPHY_RX_LD0_TRIO0_HS_SETTLE_PARAMETER, > + settle_delay_dt); > + SENINF_BITS(base, DPHY_RX_DATA_LANE1_HS_PARAMETER, > + RG_CDPHY_RX_LD1_TRIO1_HS_SETTLE_PARAMETER, > + settle_delay_dt); > + SENINF_BITS(base, DPHY_RX_DATA_LANE2_HS_PARAMETER, > + RG_CDPHY_RX_LD2_TRIO2_HS_SETTLE_PARAMETER, > + settle_delay_dt); > + SENINF_BITS(base, DPHY_RX_DATA_LANE3_HS_PARAMETER, > + RG_CDPHY_RX_LD3_TRIO3_HS_SETTLE_PARAMETER, > + settle_delay_dt); > + > + settle_delay_ck = ctx->core->settle_delay_ck; > + > + SENINF_BITS(base, DPHY_RX_CLOCK_LANE0_HS_PARAMETER, > + RG_DPHY_RX_LC0_HS_SETTLE_PARAMETER, > + settle_delay_ck); > + SENINF_BITS(base, DPHY_RX_CLOCK_LANE1_HS_PARAMETER, > + RG_DPHY_RX_LC1_HS_SETTLE_PARAMETER, > + settle_delay_ck); > + > + SENINF_BITS(base, DPHY_RX_DATA_LANE0_HS_PARAMETER, > + RG_CDPHY_RX_LD0_TRIO0_HS_PREPARE_PARAMETER, 2); > + SENINF_BITS(base, DPHY_RX_DATA_LANE1_HS_PARAMETER, > + RG_CDPHY_RX_LD1_TRIO1_HS_PREPARE_PARAMETER, 2); > + SENINF_BITS(base, DPHY_RX_DATA_LANE2_HS_PARAMETER, > + RG_CDPHY_RX_LD2_TRIO2_HS_PREPARE_PARAMETER, 2); > + SENINF_BITS(base, DPHY_RX_DATA_LANE3_HS_PARAMETER, > + RG_CDPHY_RX_LD3_TRIO3_HS_PREPARE_PARAMETER, 2); > + > + hs_trail = ctx->hs_trail_parameter; > + > + SENINF_BITS(base, DPHY_RX_DATA_LANE0_HS_PARAMETER, > + RG_DPHY_RX_LD0_HS_TRAIL_PARAMETER, hs_trail); > + SENINF_BITS(base, DPHY_RX_DATA_LANE1_HS_PARAMETER, > + RG_DPHY_RX_LD1_HS_TRAIL_PARAMETER, hs_trail); > + SENINF_BITS(base, DPHY_RX_DATA_LANE2_HS_PARAMETER, > + RG_DPHY_RX_LD2_HS_TRAIL_PARAMETER, hs_trail); > + SENINF_BITS(base, DPHY_RX_DATA_LANE3_HS_PARAMETER, > + RG_DPHY_RX_LD3_HS_TRAIL_PARAMETER, hs_trail); > + > + if (!ctx->is_cphy) { > + bit_per_pixel = 10; data_rate = ctx->customized_pixel_rate ? ctx->customized_pixel_rate : ctx->mipi_pixel_rate; data_rate *= bits_per_pixel; > + if (ctx->customized_pixel_rate != 0) > + data_rate = ctx->customized_pixel_rate * bit_per_pixel; > + else > + data_rate = ctx->mipi_pixel_rate * bit_per_pixel; > + > + do_div(data_rate, ctx->num_data_lanes); > + hs_trail_en = data_rate < 1400000000; > + SENINF_BITS(base, DPHY_RX_DATA_LANE0_HS_PARAMETER, > + RG_DPHY_RX_LD0_HS_TRAIL_EN, hs_trail_en); > + SENINF_BITS(base, DPHY_RX_DATA_LANE1_HS_PARAMETER, > + RG_DPHY_RX_LD1_HS_TRAIL_EN, hs_trail_en); > + SENINF_BITS(base, DPHY_RX_DATA_LANE2_HS_PARAMETER, > + RG_DPHY_RX_LD2_HS_TRAIL_EN, hs_trail_en); > + SENINF_BITS(base, DPHY_RX_DATA_LANE3_HS_PARAMETER, > + RG_DPHY_RX_LD3_HS_TRAIL_EN, hs_trail_en); > + } > + > + return 0; > +} > + > +static int csirx_cphy_init(struct seninf_ctx *ctx) > +{ > + void __iomem *base = ctx->reg_ana_cphy_top[ctx->port]; > + > + SENINF_BITS(base, CPHY_RX_DETECT_CTRL_POST, > + RG_CPHY_RX_DATA_VALID_POST_EN, 1); > + > + return 0; > +} > + > +static int csirx_phy_init(struct seninf_ctx *ctx) > +{ > + csirx_phyA_init(ctx); > + > + csirx_dphy_init(ctx); > + csirx_cphy_init(ctx); > + > + return 0; > +} > + > +static int csirx_seninf_csi2_setting(struct seninf_ctx *ctx) > +{ > + void __iomem *seninf_csi2 = ctx->reg_if_csi2[ctx->seninf_idx]; > + int csi_en; > + > + SENINF_BITS(seninf_csi2, SENINF_CSI2_DBG_CTRL, > + RG_CSI2_DBG_PACKET_CNT_EN, 1); > + > + /* lane/trio count */ > + SENINF_BITS(seninf_csi2, SENINF_CSI2_RESYNC_MERGE_CTRL, > + RG_CSI2_RESYNC_CYCLE_CNT_OPT, 1); > + > + csi_en = (1 << ctx->num_data_lanes) - 1; csi_en = BIT(ctx->num_data_lanes) - 1; or csi_en = GENMASK(ctx->num_data_lanes - 1, 0); > + > + if (!ctx->is_cphy) { > + SENINF_BITS(seninf_csi2, SENINF_CSI2_OPT, RG_CSI2_CPHY_SEL, 0); > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_EN, csi_en); > + SENINF_BITS(seninf_csi2, SENINF_CSI2_HDR_MODE_0, > + RG_CSI2_HEADER_MODE, 0); > + SENINF_BITS(seninf_csi2, SENINF_CSI2_HDR_MODE_0, > + RG_CSI2_HEADER_LEN, 0); > + } else { > + u8 map_hdr_len[] = {0, 1, 2, 4, 5}; u8 map_hdr_len[] = { 0, 1, 2, 4, 5 }; > + > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_EN, csi_en); > + SENINF_BITS(seninf_csi2, SENINF_CSI2_OPT, > + RG_CSI2_CPHY_SEL, 1); > + SENINF_BITS(seninf_csi2, SENINF_CSI2_HDR_MODE_0, > + RG_CSI2_HEADER_MODE, 2); > + SENINF_BITS(seninf_csi2, SENINF_CSI2_HDR_MODE_0, > + RG_CSI2_HEADER_LEN, > + map_hdr_len[ctx->num_data_lanes]); > + } > + > + return 0; > +} > + > +static int csirx_seninf_setting(struct seninf_ctx *ctx) > +{ > + void __iomem *seninf = ctx->reg_if_ctrl[ctx->seninf_idx]; > + > + /* enable/disable seninf csi2 */ > + SENINF_BITS(seninf, SENINF_CSI2_CTRL, RG_SENINF_CSI2_EN, 1); > + > + /* enable/disable seninf, enable after csi2, testmdl is done */ > + SENINF_BITS(seninf, SENINF_CTRL, SENINF_EN, 1); > + > + return 0; > +} > + > +static int csirx_seninf_top_setting(struct seninf_ctx *ctx) > +{ ..snip.. > + > + /* port operation mode */ > + switch (ctx->port) { > + case CSI_PORT_0: > + case CSI_PORT_0A: > + case CSI_PORT_0B: reg = TOP_PHY_CTRL_CSI0; field_cphy = PHY_SENINF_MUX0_CPHY_EN; field_dphy = PHY_SENINF_MUX0_DPHY_EN; break; case CSI_PORT_1: case CSI_PORT_1A: case CSI_PORT_1B: reg = TOP_PHY_CTRL_CSI1; field_cphy = PHY_SENINF_MUX1_CPHY_EN; field_dphy = PHY_SENINF_MUX1_DPHY_EN; break; .... etc } regmap_write_bits(regmap, reg, field_cphy, ctx->is_cphy); regmap_write_bits(regmap, reg, field_dphy, !ctx->is_cphy); > + if (!ctx->is_cphy) { > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI0, > + PHY_SENINF_MUX0_CPHY_EN, 0); > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI0, > + PHY_SENINF_MUX0_DPHY_EN, 1); > + } else { > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI0, > + PHY_SENINF_MUX0_DPHY_EN, 0); > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI0, > + PHY_SENINF_MUX0_CPHY_EN, 1); > + } > + break; > + case CSI_PORT_1: > + case CSI_PORT_1A: > + case CSI_PORT_1B: > + if (!ctx->is_cphy) { > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI1, > + PHY_SENINF_MUX1_CPHY_EN, 0); > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI1, > + PHY_SENINF_MUX1_DPHY_EN, 1); > + } else { > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI1, > + PHY_SENINF_MUX1_DPHY_EN, 0); > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI1, > + PHY_SENINF_MUX1_CPHY_EN, 1); > + } > + break; > + case CSI_PORT_2: > + case CSI_PORT_2A: > + case CSI_PORT_2B: > + if (!ctx->is_cphy) { > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI2, > + PHY_SENINF_MUX2_CPHY_EN, 0); > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI2, > + PHY_SENINF_MUX2_DPHY_EN, 1); > + } else { > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI2, > + PHY_SENINF_MUX2_DPHY_EN, 0); > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI2, > + PHY_SENINF_MUX2_CPHY_EN, 1); > + } > + break; > + case CSI_PORT_3: > + case CSI_PORT_3A: > + case CSI_PORT_3B: > + if (!ctx->is_cphy) { > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI3, > + PHY_SENINF_MUX3_CPHY_EN, 0); > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI3, > + PHY_SENINF_MUX3_DPHY_EN, 1); > + } else { > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI3, > + PHY_SENINF_MUX3_DPHY_EN, 0); > + SENINF_BITS(seninf_top, SENINF_TOP_PHY_CTRL_CSI3, > + PHY_SENINF_MUX3_CPHY_EN, 1); > + } > + break; > + default: > + break; So if this is called with a CSI_PORT that is out of range, we're not erroring out?!?! > + } > + > + return 0; > +} > + > +static int csirx_phyA_setting(struct seninf_ctx *ctx) > +{ > + void __iomem *base, *baseA, *baseB; > + > + base = ctx->reg_ana_csi_rx[ctx->port]; > + baseA = ctx->reg_ana_csi_rx[ctx->port_a]; > + baseB = ctx->reg_ana_csi_rx[ctx->port_b]; > + > + if (!ctx->is_cphy) { /* dphy */ For this huge register write sequence, you want to split it in at least two functions to improve human readability and reduce indentation. > + if (ctx->is_4d1c) { > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_CPHY_EN, 0); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_CPHY_EN, 0); > + /* clear clk sel first */ > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKMODE_EN, 0); > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKMODE_EN, 0); > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKMODE_EN, 0); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKMODE_EN, 0); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKMODE_EN, 0); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKMODE_EN, 0); > + > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKSEL, 1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKSEL, 1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKSEL, 1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKSEL, 1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKSEL, 1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKSEL, 1); > + > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKMODE_EN, 0); > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKMODE_EN, 0); > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKMODE_EN, 1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKMODE_EN, 0); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKMODE_EN, 0); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKMODE_EN, 0); > + > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_BW, 0x3); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_IS, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG1_EN, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR0, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR1, 0x0); > + > + SENINF_BITS(baseB, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_BW, 0x3); > + SENINF_BITS(baseB, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_IS, 0x1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG1_EN, 0x1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR0, 0x1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR1, 0x0); > + } else { > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_CPHY_EN, 0); > + /* clear clk sel first */ > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKMODE_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKMODE_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKMODE_EN, 0); > + > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKSEL, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKSEL, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKSEL, 0); > + > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L0_CKMODE_EN, 0); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L1_CKMODE_EN, 1); > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_DPHY_L2_CKMODE_EN, 0); > + > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_BW, 0x3); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_IS, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG1_EN, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR0, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR1, 0x0); > + } > + } else { /* cphy */ > + if (ctx->is_4d1c) { > + SENINF_BITS(baseA, CDPHY_RX_ANA_0, > + RG_CSI0_CPHY_EN, 1); > + SENINF_BITS(baseB, CDPHY_RX_ANA_0, > + RG_CSI0_CPHY_EN, 1); > + > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_BW, 0x3); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_IS, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG1_EN, 0x0); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR0, 0x3); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR1, 0x0); > + > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_BW, 0x3); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_IS, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG1_EN, 0x0); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR0, 0x3); > + SENINF_BITS(baseA, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR1, 0x0); > + } else { > + SENINF_BITS(base, CDPHY_RX_ANA_0, > + RG_CSI0_CPHY_EN, 1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_BW, 0x3); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_IS, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_LATCH_EN, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG0_EN, 0x1); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_DG1_EN, 0x0); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR0, 0x3); > + SENINF_BITS(base, CDPHY_RX_ANA_5, > + RG_CSI0_CDPHY_EQ_SR1, 0x0); > + } > + } > + > + /* phyA power on */ > + if (ctx->is_4d1c) { > + csirx_phyA_power_on(ctx, ctx->port_a, 1); > + csirx_phyA_power_on(ctx, ctx->port_b, 1); > + } else { > + csirx_phyA_power_on(ctx, ctx->port, 1); > + } > + > + return 0; > +} > + > +static int csirx_dphy_setting(struct seninf_ctx *ctx) > +{ > + void __iomem *base = ctx->reg_ana_dphy_top[ctx->port]; > + > + if (ctx->is_4d1c) { > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD3_SEL, 4); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD2_SEL, 0); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD1_SEL, 3); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD0_SEL, 1); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LC0_SEL, 2); > + > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD0_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD1_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD2_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD3_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LC0_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LC1_EN, 0); > + } else { > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD3_SEL, 5); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD2_SEL, 3); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD1_SEL, 2); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LD0_SEL, 0); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LC1_SEL, 4); > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, RG_DPHY_RX_LC0_SEL, 1); > + > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD0_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD1_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD2_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LD3_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LC0_EN, 1); > + SENINF_BITS(base, DPHY_RX_LANE_EN, DPHY_RX_LC1_EN, 1); > + } > + > + SENINF_BITS(base, DPHY_RX_LANE_SELECT, DPHY_RX_CK_DATA_MUX_EN, 1); > + > + return 0; > +} > + > +static int csirx_cphy_setting(struct seninf_ctx *ctx) > +{ > + void __iomem *base = ctx->reg_ana_cphy_top[ctx->port]; u32 reg_lprx[] = { CPHY_RX_TR0_LPRX_EN, CPHY_RX_TR1_LPRX_EN, ...TR2, ...TR3 }; > + > + switch (ctx->port) { > + case CSI_PORT_0: > + case CSI_PORT_1: > + case CSI_PORT_2: > + case CSI_PORT_3: > + case CSI_PORT_0A: > + case CSI_PORT_1A: > + case CSI_PORT_2A: > + case CSI_PORT_3A: for (i = 0; i < ctx->num_data_lanes; i++) regmap_write_bits(regmap, CPHY_RX_CTRL, reg_lprx[i], 1); for (; i < ARRAY_SIZE(reg_lprx); i++) regmap_write_bits(regmap, CPHY_RX_CTRL, reg_lprx[i], 0); > + if (ctx->num_data_lanes == 3) { > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR0_LPRX_EN, 1); > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR1_LPRX_EN, 1); > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR2_LPRX_EN, 1); > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR3_LPRX_EN, 0); > + } else if (ctx->num_data_lanes == 2) { > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR0_LPRX_EN, 1); > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR1_LPRX_EN, 1); > + } else { > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR0_LPRX_EN, 1); > + } > + break; > + case CSI_PORT_0B: > + case CSI_PORT_1B: > + case CSI_PORT_2B: > + case CSI_PORT_3B: for (i = 0; i < ctx->num_data_lanes; i++) { regmap_write_bits(regmap, CPHY_RX_CTRL, reg_lprx[i], 0); regmap_write_bits(regmap, CPHY_RX_CTRL, reg_lprx[i+2], 1); } > + if (ctx->num_data_lanes == 2) { > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR2_LPRX_EN, 1); > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR3_LPRX_EN, 1); > + } else { > + SENINF_BITS(base, CPHY_RX_CTRL, CPHY_RX_TR2_LPRX_EN, 1); > + } > + break; > + default: > + break; > + } > + > + return 0; > +} > + > +static int csirx_phy_setting(struct seninf_ctx *ctx) > +{ > + csirx_phyA_setting(ctx); > + Please, if (ctx->is_cphy) x() else y() > + if (!ctx->is_cphy) > + csirx_dphy_setting(ctx); > + else > + csirx_cphy_setting(ctx); > + > + return 0; > +} > + > +int mtk_cam_seninf_set_csi_mipi(struct seninf_ctx *ctx) > +{ > + csirx_phy_init(ctx); > + > + /* seninf csi2 */ > + csirx_seninf_csi2_setting(ctx); > + > + /* seninf */ > + csirx_seninf_setting(ctx); > + > + /* seninf top */ > + csirx_seninf_top_setting(ctx); > + > + /* phy */ > + csirx_phy_setting(ctx); > + > + return 0; > +} > + > +int mtk_cam_seninf_poweroff(struct seninf_ctx *ctx) > +{ > + void __iomem *seninf_csi2; > + > + seninf_csi2 = ctx->reg_if_csi2[ctx->seninf_idx]; > + > + SENINF_WRITE_REG(seninf_csi2, SENINF_CSI2_EN, 0x0); > + > + if (ctx->is_4d1c) { > + csirx_phyA_power_on(ctx, ctx->port_a, 0); > + csirx_phyA_power_on(ctx, ctx->port_b, 0); > + } else { > + csirx_phyA_power_on(ctx, ctx->port, 0); > + } > + > + return 0; > +} > + > +int mtk_cam_seninf_reset(struct seninf_ctx *ctx, u32 seninf_idx) > +{ > + int i; > + void __iomem *seninf_mux; > + void __iomem *seninf = ctx->reg_if_ctrl[seninf_idx]; > + > + SENINF_BITS(seninf, SENINF_CSI2_CTRL, SENINF_CSI2_SW_RST, 1); What about adding a reset controller that includes SENINF_CSI(x)_SW_RST? Also, why are you resetting only CSI2 and not the others? > + udelay(1); > + SENINF_BITS(seninf, SENINF_CSI2_CTRL, SENINF_CSI2_SW_RST, 0); > + > + dev_dbg(ctx->dev, "reset seninf %d\n", seninf_idx); > + > + for (i = SENINF_MUX1; i < _seninf_cfg.mux_num; i++) > + if (mtk_cam_seninf_get_top_mux_ctrl(ctx, i) == seninf_idx && > + mtk_cam_seninf_is_mux_used(ctx, i)) { > + seninf_mux = ctx->reg_if_mux[i]; > + SENINF_BITS(seninf_mux, SENINF_MUX_CTRL_0, > + SENINF_MUX_SW_RST, 1); > + udelay(1); > + SENINF_BITS(seninf_mux, SENINF_MUX_CTRL_0, > + SENINF_MUX_SW_RST, 0); > + dev_dbg(ctx->dev, "reset mux %d\n", i); > + } > + > + return 0; > +} > + > +int mtk_cam_seninf_set_idle(struct seninf_ctx *ctx) > +{ > + int i; > + struct seninf_vcinfo *vcinfo = &ctx->vcinfo; > + struct seninf_vc *vc; > + > + for (i = 0; i < vcinfo->cnt; i++) { > + vc = &vcinfo->vc[i]; > + if (vc->enable) { > + mtk_cam_seninf_disable_mux(ctx, vc->mux); > + mtk_cam_seninf_disable_cammux(ctx, vc->cam); > + ctx->pad2cam[vc->out_pad] = 0xff; > + } > + } > + > + return 0; > +} > + > +int mtk_cam_seninf_get_mux_meter(struct seninf_ctx *ctx, u32 mux, > + struct mtk_cam_seninf_mux_meter *meter) > +{ > + void __iomem *seninf_mux; > + s64 hv, hb, vv, vb, w, h; > + u64 mipi_pixel_rate, vb_in_us, hb_in_us, line_time_in_us; > + u32 res; > + > + seninf_mux = ctx->reg_if_mux[mux]; > + > + SENINF_BITS(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_CTRL, > + RG_SENINF_MUX_FRAME_SIZE_MON_EN, 1); > + > + hv = SENINF_READ_REG(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_H_VALID); > + hb = SENINF_READ_REG(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_H_BLANK); > + vv = SENINF_READ_REG(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_V_VALID); > + vb = SENINF_READ_REG(seninf_mux, SENINF_MUX_FRAME_SIZE_MON_V_BLANK); > + res = SENINF_READ_REG(seninf_mux, SENINF_MUX_SIZE); > + > + w = res & 0xffff; Another case of bitfield.h macros open-coded, or missed opportunity to just use regmap to simplify this. > + h = res >> 16; And same here, of course. > + > + if (ctx->fps_n && ctx->fps_d) { > + mipi_pixel_rate = w * ctx->fps_n * (vv + vb); > + do_div(mipi_pixel_rate, ctx->fps_d); Use div_s64() for safe 64-bits division. > + do_div(mipi_pixel_rate, hv); > + > + vb_in_us = vb * ctx->fps_d * 1000000; > + do_div(vb_in_us, vv + vb); > + do_div(vb_in_us, ctx->fps_n); > + > + hb_in_us = hb * ctx->fps_d * 1000000; > + do_div(hb_in_us, vv + vb); > + do_div(hb_in_us, ctx->fps_n); > + > + line_time_in_us = (hv + hb) * ctx->fps_d * 1000000; > + do_div(line_time_in_us, vv + vb); > + do_div(line_time_in_us, ctx->fps_n); > + > + meter->mipi_pixel_rate = mipi_pixel_rate; > + meter->vb_in_us = vb_in_us; > + meter->hb_in_us = hb_in_us; > + meter->line_time_in_us = line_time_in_us; > + } else { > + meter->mipi_pixel_rate = -1; > + meter->vb_in_us = -1; > + meter->hb_in_us = -1; > + meter->line_time_in_us = -1; > + } > + > + meter->width = w; > + meter->height = h; > + > + meter->h_valid = hv; > + meter->h_blank = hb; > + meter->v_valid = vv; > + meter->v_blank = vb; > + > + return 0; > +} > + > +ssize_t mtk_cam_seninf_show_status(struct device *dev, > + struct device_attribute *attr, char *buf) > +{ > + int i, len; > + struct seninf_core *core; struct seninf_core *core = dev_get_drvdata(dev); > + struct seninf_ctx *ctx; > + struct seninf_vc *vc; > + struct media_link *link; > + struct media_pad *pad; > + struct mtk_cam_seninf_mux_meter meter; > + void __iomem *csi2, *pmux; > + void __iomem *rx, *pcammux; int i, len = 0; > + > + core = dev_get_drvdata(dev); > + len = 0; > + > + mutex_lock(&core->mutex); > + > + list_for_each_entry(ctx, &core->list, list) { > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\n[%s] port %d intf %d test %d cphy %d lanes %d\n", > + ctx->subdev.name, ctx->port, ctx->seninf_idx, > + ctx->is_test_model, ctx->is_cphy, > + ctx->num_data_lanes); > + > + pad = &ctx->pads[PAD_SINK]; > + list_for_each_entry(link, &pad->entity->links, list) { > + if (link->sink == pad) { > + len += snprintf(buf + len, PAGE_SIZE - len, > + "source %s flags 0x%lx\n", > + link->source->entity->name, > + link->flags); > + } > + } > + > + if (!ctx->streaming) > + continue; > + > + csi2 = ctx->reg_if_csi2[ctx->seninf_idx]; > + rx = ctx->reg_ana_dphy_top[ctx->port]; > + > + len += snprintf(buf + len, PAGE_SIZE - len, > + "csi2 irq_stat 0x%08x\n", > + SENINF_READ_REG(csi2, SENINF_CSI2_IRQ_STATUS)); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "csi2 line_frame_num 0x%08x\n", > + SENINF_READ_REG(csi2, SENINF_CSI2_LINE_FRAME_NUM)); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "csi2 packet_status 0x%08x\n", > + SENINF_READ_REG(csi2, SENINF_CSI2_PACKET_STATUS)); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "csi2 packet_cnt_status 0x%08x\n", > + SENINF_READ_REG(csi2, SENINF_CSI2_PACKET_CNT_STATUS)); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "rx-ana settle ck 0x%02x dt 0x%02x\n", > + SENINF_READ_BITS(rx, DPHY_RX_CLOCK_LANE0_HS_PARAMETER, > + RG_DPHY_RX_LC0_HS_SETTLE_PARAMETER), > + SENINF_READ_BITS(rx, > + DPHY_RX_DATA_LANE0_HS_PARAMETER, > + RG_CDPHY_RX_LD0_TRIO0_HS_SETTLE_PARAMETER)); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "rx-ana trail en %u param 0x%02x\n", > + SENINF_READ_BITS(rx, DPHY_RX_DATA_LANE0_HS_PARAMETER, > + RG_DPHY_RX_LD0_HS_TRAIL_EN), > + SENINF_READ_BITS(rx, DPHY_RX_DATA_LANE0_HS_PARAMETER, > + RG_DPHY_RX_LD0_HS_TRAIL_PARAMETER)); > + > + len += snprintf(buf + len, PAGE_SIZE - len, > + "data_not_enough_cnt : <%d>", > + ctx->data_not_enough_cnt); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "err_lane_resync_cnt : <%d>", > + ctx->err_lane_resync_cnt); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "crc_err_cnt : <%d>", ctx->crc_err_flag); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "ecc_err_double_cnt : <%d>", > + ctx->ecc_err_double_cnt); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "ecc_err_corrected_cnt : <%d>\n", > + ctx->ecc_err_corrected_cnt); > + > + for (i = 0; i < ctx->vcinfo.cnt; i++) { > + vc = &ctx->vcinfo.vc[i]; > + pmux = ctx->reg_if_mux[vc->mux]; > + pcammux = ctx->reg_if_cam_mux; > + > + len += snprintf(buf + len, PAGE_SIZE - len, > + "[%d] vc 0x%x dt 0x%x mux %d cam %d\n", > + i, vc->vc, vc->dt, vc->mux, vc->cam); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\tmux[%d] en %d src %d irq_stat 0x%x\n", > + vc->mux, > + mtk_cam_seninf_is_mux_used(ctx, vc->mux), > + mtk_cam_seninf_get_top_mux_ctrl(ctx, vc->mux), > + SENINF_READ_REG(pmux, SENINF_MUX_IRQ_STATUS)); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\t\tfifo_overrun_cnt : <%d>\n", > + ctx->fifo_overrun_cnt); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\tcam[%d] en %d src %d exp 0x%x res 0x%x irq_stat 0x%x\n", > + vc->cam, > + mtk_cam_seninf_is_cammux_used(ctx, vc->cam), > + mtk_cam_seninf_get_cammux_ctrl(ctx, vc->cam), > + mtk_cam_seninf_get_cammux_exp(ctx, vc->cam), > + mtk_cam_seninf_get_cammux_res(ctx, vc->cam), > + SENINF_READ_REG(pcammux, > + SENINF_CAM_MUX_IRQ_STATUS)); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\t\tsize_err_cnt : <%d>\n", > + ctx->size_err_cnt); > + > + if (vc->feature == VC_RAW_DATA || > + vc->feature == VC_STAGGER_NE || > + vc->feature == VC_STAGGER_ME || > + vc->feature == VC_STAGGER_SE) { > + mtk_cam_seninf_get_mux_meter(ctx, vc->mux, > + &meter); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\t--- mux meter ---\n"); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\twidth %d height %d\n", > + meter.width, meter.height); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\th_valid %d, h_blank %d\n", > + meter.h_valid, meter.h_blank); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\tv_valid %d, v_blank %d\n", > + meter.v_valid, meter.v_blank); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\tmipi_pixel_rate %lld\n", > + meter.mipi_pixel_rate); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\tv_blank %lld us\n", > + meter.vb_in_us); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\th_blank %lld us\n", > + meter.hb_in_us); > + len += snprintf(buf + len, PAGE_SIZE - len, > + "\tline_time %lld us\n", > + meter.line_time_in_us); > + } > + } > + } > + > + mutex_unlock(&core->mutex); > + > + return len; > +} > + > +#define SENINF_DRV_DEBUG_MAX_DELAY 400 > + > +static inline void > +mtk_cam_seninf_clear_matched_cam_mux_irq(struct seninf_ctx *ctx, > + u32 cam_mux_idx, Why is this a u32 param?.... > + u32 vc_idx, > + s32 enabled) > +{ > + u8 used_cammux; ...if this is a u8 local variable? (cam_mux_idx should be u8 instead - same for vc_idx) > + > + if (cam_mux_idx >= SENINF_CAM_MUX_NUM) { > + dev_info(ctx->dev, "unsupport cam_mux(%u)", cam_mux_idx); > + return; > + } > + if (vc_idx >= SENINF_VC_MAXCNT) { > + dev_info(ctx->dev, "unsupport vc_idx(%u)", vc_idx); > + return; > + } > + > + used_cammux = ctx->vcinfo.vc[vc_idx].cam; > + if (used_cammux == cam_mux_idx && > + enabled & (1 << cam_mux_idx)) { > + dev_dbg(ctx->dev, > + "before clear cam mux%u recSize = 0x%x, irq = 0x%x", > + cam_mux_idx, > + SENINF_READ_REG(ctx->reg_if_cam_mux, > + SENINF_CAM_MUX0_CHK_RES + (0x10 * cam_mux_idx)), > + SENINF_READ_REG(ctx->reg_if_cam_mux, > + SENINF_CAM_MUX_IRQ_STATUS)); > + > + SENINF_WRITE_REG(ctx->reg_if_cam_mux, > + SENINF_CAM_MUX_IRQ_STATUS, > + 3 << (cam_mux_idx * 2)); > + } > +} > + > +static inline void mtk_cam_seninf_check_matched_cam_mux(struct seninf_ctx *ctx, > + u32 cam_mux_idx, > + u32 vc_idx, > + s32 enabled, > + s32 irq_status) > +{ > + u8 used_cammux; > + > + if (cam_mux_idx >= SENINF_CAM_MUX_NUM) { > + dev_info(ctx->dev, "unsupport cam_mux(%u)", cam_mux_idx); > + return; > + } > + if (vc_idx >= SENINF_VC_MAXCNT) { > + dev_info(ctx->dev, "unsupport vc_idx(%u)", vc_idx); > + return; > + } > + > + used_cammux = ctx->vcinfo.vc[vc_idx].cam; > + > + if (used_cammux == cam_mux_idx && enabled & (1 << cam_mux_idx)) { > + int rec_size = SENINF_READ_REG(ctx->reg_if_cam_mux, > + SENINF_CAM_MUX0_CHK_RES + (0x10 * cam_mux_idx)); > + int exp_size = SENINF_READ_REG(ctx->reg_if_cam_mux, > + SENINF_CAM_MUX0_CHK_CTL_1 + (0x10 * cam_mux_idx)); > + if (rec_size != exp_size) { > + dev_dbg(ctx->dev, > + "cam mux%u size mismatch, (rec, exp) = (0x%x, 0x%x)", > + cam_mux_idx, rec_size, exp_size); > + } > + if ((irq_status & > + (3 << (cam_mux_idx * 2))) != 0) { > + dev_dbg(ctx->dev, > + "cam mux%u size mismatch!, irq = 0x%x", > + cam_mux_idx, irq_status); > + } > + } > +} > + ..snip.. > + > +#define SBUF 256 > +int mtk_cam_seninf_irq_handler(int irq, void *data) > +{ > + struct seninf_core *core = (struct seninf_core *)data; > + unsigned long flags; /* for mipi err detection */ > + struct seninf_ctx *ctx; > + struct seninf_vc *vc; > + void __iomem *csi2, *pmux, *seninf_cam_mux; > + int i; > + unsigned int csi_irq_ro; > + unsigned int mux_irq_ro; > + unsigned int cam_irq_exp_ro; > + unsigned int cam_irq_res_ro; > + char seninf_log[SBUF]; > + unsigned int wcnt = 0; > + > + spin_lock_irqsave(&core->spinlock_irq, flags); > + > + /* debug for set_reg case: REG_KEY_CSI_IRQ_EN */ > + if (core->csi_irq_en_flag) { > + list_for_each_entry(ctx, &core->list, list) { > + csi2 = ctx->reg_if_csi2[ctx->seninf_idx]; > + csi_irq_ro = > + SENINF_READ_REG(csi2, SENINF_CSI2_IRQ_STATUS); > + > + if (csi_irq_ro) { > + SENINF_WRITE_REG(csi2, SENINF_CSI2_IRQ_STATUS, > + 0xFFFFFFFF); > + } > + > + if (csi_irq_ro & (0x1 << RO_CSI2_ECC_ERR_CORRECTED_IRQ_SHIFT)) > + ctx->ecc_err_corrected_cnt++; > + if (csi_irq_ro & (0x1 << RO_CSI2_ECC_ERR_DOUBLE_IRQ_SHIFT)) > + ctx->ecc_err_double_cnt++; > + if (csi_irq_ro & (0x1 << RO_CSI2_CRC_ERR_IRQ_SHIFT)) > + ctx->crc_err_cnt++; > + if (csi_irq_ro & (0x1 << RO_CSI2_ERR_LANE_RESYNC_IRQ_SHIFT)) > + ctx->err_lane_resync_cnt++; > + if (csi_irq_ro & (0x1 << RO_CSI2_RECEIVE_DATA_NOT_ENOUGH_IRQ_SHIFT)) > + ctx->data_not_enough_cnt++; > + > + for (i = 0; i < ctx->vcinfo.cnt; i++) { > + vc = &ctx->vcinfo.vc[i]; > + pmux = ctx->reg_if_mux[vc->mux]; > + seninf_cam_mux = ctx->reg_if_cam_mux; > + > + mux_irq_ro = SENINF_READ_REG(pmux, > + SENINF_MUX_IRQ_STATUS); > + > + cam_irq_exp_ro = SENINF_READ_REG(seninf_cam_mux, > + SENINF_CAM_MUX0_CHK_CTL_1 + > + (0x10 * (vc->cam))); > + > + cam_irq_res_ro = SENINF_READ_REG(seninf_cam_mux, > + SENINF_CAM_MUX0_CHK_RES + > + (0x10 * (vc->cam))); > + > + if (mux_irq_ro) > + SENINF_WRITE_REG(pmux, > + SENINF_MUX_IRQ_STATUS, > + 0xFFFFFFFF); > + > + if (cam_irq_res_ro != cam_irq_exp_ro) > + SENINF_WRITE_REG(seninf_cam_mux, > + SENINF_CAM_MUX0_CHK_RES + > + (0x10 * (vc->cam)), > + 0xFFFFFFFF); > + > + if (mux_irq_ro & (0x1 << 0)) > + ctx->fifo_overrun_cnt++; > + > + if (cam_irq_res_ro != cam_irq_exp_ro) > + ctx->size_err_cnt++; > + } > + > + /* dump status counter: debug for electrical signal */ > + if (ctx->data_not_enough_cnt >= core->detection_cnt || > + ctx->err_lane_resync_cnt >= core->detection_cnt || > + ctx->crc_err_cnt >= core->detection_cnt || > + ctx->ecc_err_double_cnt >= core->detection_cnt || > + ctx->ecc_err_corrected_cnt >= core->detection_cnt || > + ctx->fifo_overrun_cnt >= core->detection_cnt || > + ctx->size_err_cnt >= core->detection_cnt) { > + /* disable all interrupts */ > + SENINF_WRITE_REG(csi2, SENINF_CSI2_IRQ_EN, 0x80000000); > + > + if (ctx->data_not_enough_cnt >= core->detection_cnt) > + ctx->data_not_enough_flag = 1; > + if (ctx->err_lane_resync_cnt >= core->detection_cnt) > + ctx->err_lane_resync_flag = 1; > + if (ctx->crc_err_cnt >= core->detection_cnt) > + ctx->crc_err_flag = 1; > + if (ctx->ecc_err_double_cnt >= core->detection_cnt) > + ctx->ecc_err_double_flag = 1; > + if (ctx->ecc_err_corrected_cnt >= core->detection_cnt) > + ctx->ecc_err_corrected_flag = 1; > + if (ctx->fifo_overrun_cnt >= core->detection_cnt) > + ctx->fifo_overrun_flag = 1; > + if (ctx->size_err_cnt >= core->detection_cnt) > + ctx->size_err_flag = 1; > + > + wcnt = snprintf(seninf_log, SBUF, "info: %s", __func__); You're not even printing seninf_log, so either print it (no, please don't) or just drop it. > + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt, > + " data_not_enough_count: %d", > + ctx->data_not_enough_cnt); > + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt, > + " err_lane_resync_count: %d", > + ctx->err_lane_resync_cnt); > + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt, > + " crc_err_count: %d", > + ctx->crc_err_cnt); > + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt, > + " ecc_err_double_count: %d", > + ctx->ecc_err_double_cnt); > + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt, > + " ecc_err_corrected_count: %d", > + ctx->ecc_err_corrected_cnt); > + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt, > + " fifo_overrun_count: %d", > + ctx->fifo_overrun_cnt); > + wcnt += snprintf(seninf_log + wcnt, SBUF - wcnt, > + " size_err_count: %d", > + ctx->size_err_cnt); > + } > + } > + } > + > + spin_unlock_irqrestore(&core->spinlock_irq, flags); > + > + return 0; > +} > + > +int mtk_cam_seninf_set_sw_cfg_busy(struct seninf_ctx *ctx, bool enable, > + int index) > +{ > + void __iomem *seninf_cam_mux = ctx->reg_if_cam_mux; mask = index ? RG_SENINF_CAM_MUX_DYN_SWITCH_BSY1 : RG_SENINF_CAM_MUX_DYN_SWITCH_BSY0 > + > + if (index == 0) > + SENINF_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_CTRL, > + RG_SENINF_CAM_MUX_DYN_SWITCH_BSY0, enable); > + else > + SENINF_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_CTRL, > + RG_SENINF_CAM_MUX_DYN_SWITCH_BSY1, enable); > + return 0; > +} > + > +int mtk_cam_seninf_set_cam_mux_dyn_en(struct seninf_ctx *ctx, bool enable, > + int cam_mux, int index) > +{ > + void __iomem *seninf_cam_mux = ctx->reg_if_cam_mux; > + u32 tmp = 0; > + > + if (index == 0) { > + tmp = SENINF_READ_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_EN, > + RG_SENINF_CAM_MUX_DYN_SWITCH_EN0); regmap_set_bits() will definitely help here. > + if (enable) > + tmp = tmp | (1 << cam_mux); > + else > + tmp = tmp & ~(1 << cam_mux); > + > + SENINF_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_EN, > + RG_SENINF_CAM_MUX_DYN_SWITCH_EN0, tmp); > + } else { > + tmp = SENINF_READ_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_EN, > + RG_SENINF_CAM_MUX_DYN_SWITCH_EN1); > + if (enable) > + tmp = tmp | (1 << cam_mux); > + else > + tmp = tmp & ~(1 << cam_mux); > + > + SENINF_BITS(seninf_cam_mux, SENINF_CAM_MUX_DYN_EN, > + RG_SENINF_CAM_MUX_DYN_SWITCH_EN1, tmp); > + } > + > + return 0; > +} > + There is surely more to say on this driver, and it's far from being near to upstream quality. Please start with addressing these comments on the entire series, then we can go on with further reviews. Regards, Angelo

8 months

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[PATCH AUTOSEL 6.11 72/76] drm/amdgpu: nuke the VM PD/PT shadow handling

by Sasha Levin

From: Christian König <christian.koenig(a)amd.com> [ Upstream commit 7181faaa4703705939580abffaf9cb5d6b50dbb7 ] This was only used as workaround for recovering the page tables after VRAM was lost and is no longer necessary after the function amdgpu_vm_bo_reset_state_machine() started to do the same. Compute never used shadows either, so the only proplematic case left is SVM and that is most likely not recoverable in any way when VRAM is lost. Signed-off-by: Christian König <christian.koenig(a)amd.com> Acked-by: Lijo Lazar <lijo.lazar(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 87 +-------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 67 +--------------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 21 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 56 +------------ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 19 +---- 7 files changed, 6 insertions(+), 265 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 137a88b8de453..a1b2bf3db55b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1091,10 +1091,6 @@ struct amdgpu_device { struct amdgpu_virt virt; - /* link all shadow bo */ - struct list_head shadow_list; - struct mutex shadow_list_lock; - /* record hw reset is performed */ bool has_hw_reset; u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bcacf2e35eba0..dfd468729d52b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4073,9 +4073,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->mm_stats.lock); spin_lock_init(&adev->wb.lock); - INIT_LIST_HEAD(&adev->shadow_list); - mutex_init(&adev->shadow_list_lock); - INIT_LIST_HEAD(&adev->reset_list); INIT_LIST_HEAD(&adev->ras_list); @@ -4980,80 +4977,6 @@ static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) return 0; } -/** - * amdgpu_device_recover_vram - Recover some VRAM contents - * - * @adev: amdgpu_device pointer - * - * Restores the contents of VRAM buffers from the shadows in GTT. Used to - * restore things like GPUVM page tables after a GPU reset where - * the contents of VRAM might be lost. - * - * Returns: - * 0 on success, negative error code on failure. - */ -static int amdgpu_device_recover_vram(struct amdgpu_device *adev) -{ - struct dma_fence *fence = NULL, *next = NULL; - struct amdgpu_bo *shadow; - struct amdgpu_bo_vm *vmbo; - long r = 1, tmo; - - if (amdgpu_sriov_runtime(adev)) - tmo = msecs_to_jiffies(8000); - else - tmo = msecs_to_jiffies(100); - - dev_info(adev->dev, "recover vram bo from shadow start\n"); - mutex_lock(&adev->shadow_list_lock); - list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { - /* If vm is compute context or adev is APU, shadow will be NULL */ - if (!vmbo->shadow) - continue; - shadow = vmbo->shadow; - - /* No need to recover an evicted BO */ - if (!shadow->tbo.resource || - shadow->tbo.resource->mem_type != TTM_PL_TT || - shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || - shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) - continue; - - r = amdgpu_bo_restore_shadow(shadow, &next); - if (r) - break; - - if (fence) { - tmo = dma_fence_wait_timeout(fence, false, tmo); - dma_fence_put(fence); - fence = next; - if (tmo == 0) { - r = -ETIMEDOUT; - break; - } else if (tmo < 0) { - r = tmo; - break; - } - } else { - fence = next; - } - } - mutex_unlock(&adev->shadow_list_lock); - - if (fence) - tmo = dma_fence_wait_timeout(fence, false, tmo); - dma_fence_put(fence); - - if (r < 0 || tmo <= 0) { - dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); - return -EIO; - } - - dev_info(adev->dev, "recover vram bo from shadow done\n"); - return 0; -} - - /** * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf * @@ -5116,12 +5039,8 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, if (r) return r; - if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { + if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) amdgpu_inc_vram_lost(adev); - r = amdgpu_device_recover_vram(adev); - } - if (r) - return r; /* need to be called during full access so we can't do it later like * bare-metal does. @@ -5541,9 +5460,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, } } - if (!r) - r = amdgpu_device_recover_vram(tmp_adev); - else + if (r) tmp_adev->asic_reset_res = r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index e32161f6b67a3..a987f671b1d53 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -77,24 +77,6 @@ static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) amdgpu_bo_destroy(tbo); } -static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); - struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo; - struct amdgpu_bo_vm *vmbo; - - bo = shadow_bo->parent; - vmbo = to_amdgpu_bo_vm(bo); - /* in case amdgpu_device_recover_vram got NULL of bo->parent */ - if (!list_empty(&vmbo->shadow_list)) { - mutex_lock(&adev->shadow_list_lock); - list_del_init(&vmbo->shadow_list); - mutex_unlock(&adev->shadow_list_lock); - } - - amdgpu_bo_destroy(tbo); -} - /** * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo * @bo: buffer object to be checked @@ -108,8 +90,7 @@ static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) { if (bo->destroy == &amdgpu_bo_destroy || - bo->destroy == &amdgpu_bo_user_destroy || - bo->destroy == &amdgpu_bo_vm_destroy) + bo->destroy == &amdgpu_bo_user_destroy) return true; return false; @@ -722,52 +703,6 @@ int amdgpu_bo_create_vm(struct amdgpu_device *adev, return r; } -/** - * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list - * - * @vmbo: BO that will be inserted into the shadow list - * - * Insert a BO to the shadow list. - */ -void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); - - mutex_lock(&adev->shadow_list_lock); - list_add_tail(&vmbo->shadow_list, &adev->shadow_list); - vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo); - vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy; - mutex_unlock(&adev->shadow_list_lock); -} - -/** - * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow - * - * @shadow: &amdgpu_bo shadow to be restored - * @fence: dma_fence associated with the operation - * - * Copies a buffer object's shadow content back to the object. - * This is used for recovering a buffer from its shadow in case of a gpu - * reset where vram context may be lost. - * - * Returns: - * 0 for success or a negative error code on failure. - */ -int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) - -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - uint64_t shadow_addr, parent_addr; - - shadow_addr = amdgpu_bo_gpu_offset(shadow); - parent_addr = amdgpu_bo_gpu_offset(shadow->parent); - - return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, - amdgpu_bo_size(shadow), NULL, fence, - true, false, 0); -} - /** * amdgpu_bo_kmap - map an &amdgpu_bo buffer object * @bo: &amdgpu_bo buffer object to be mapped diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index bc42ccbde659a..a4fa1f296daec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -130,8 +130,6 @@ struct amdgpu_bo_user { struct amdgpu_bo_vm { struct amdgpu_bo bo; - struct amdgpu_bo *shadow; - struct list_head shadow_list; struct amdgpu_vm_bo_base entries[]; }; @@ -269,22 +267,6 @@ static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED; } -/** - * amdgpu_bo_shadowed - check if the BO is shadowed - * - * @bo: BO to be tested. - * - * Returns: - * NULL if not shadowed or else return a BO pointer. - */ -static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo) -{ - if (bo->tbo.type == ttm_bo_type_kernel) - return to_amdgpu_bo_vm(bo)->shadow; - - return NULL; -} - bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); @@ -343,9 +325,6 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo); void amdgpu_bo_get_memory(struct amdgpu_bo *bo, struct amdgpu_mem_stats *stats); -void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo); -int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, - struct dma_fence **fence); uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, uint32_t domain); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index a060c28f0877c..8cda1d02dade3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -465,7 +465,6 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, { uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm); struct amdgpu_vm_bo_base *bo_base; - struct amdgpu_bo *shadow; struct amdgpu_bo *bo; int r; @@ -486,16 +485,10 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, spin_unlock(&vm->status_lock); bo = bo_base->bo; - shadow = amdgpu_bo_shadowed(bo); r = validate(param, bo); if (r) return r; - if (shadow) { - r = validate(param, shadow); - if (r) - return r; - } if (bo->tbo.type != ttm_bo_type_kernel) { amdgpu_vm_bo_moved(bo_base); @@ -2123,10 +2116,6 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, { struct amdgpu_vm_bo_base *bo_base; - /* shadow bo doesn't have bo base, its validation needs its parent */ - if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo)) - bo = bo->parent; - for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; @@ -2454,7 +2443,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, root_bo = amdgpu_bo_ref(&root->bo); r = amdgpu_bo_reserve(root_bo, true); if (r) { - amdgpu_bo_unref(&root->shadow); amdgpu_bo_unref(&root_bo); goto error_free_delayed; } @@ -2546,11 +2534,6 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) vm->last_update = dma_fence_get_stub(); vm->is_compute_context = true; - /* Free the shadow bo for compute VM */ - amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow); - - goto unreserve_bo; - unreserve_bo: amdgpu_bo_unreserve(vm->root.bo); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index e39d6e7643bfb..c8e0b8cfd3363 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -383,14 +383,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (r) return r; - if (vmbo->shadow) { - struct amdgpu_bo *shadow = vmbo->shadow; - - r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx); - if (r) - return r; - } - if (!drm_dev_enter(adev_to_drm(adev), &idx)) return -ENODEV; @@ -448,10 +440,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id) { struct amdgpu_bo_param bp; - struct amdgpu_bo *bo; - struct dma_resv *resv; unsigned int num_entries; - int r; memset(&bp, 0, sizeof(bp)); @@ -484,42 +473,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (vm->root.bo) bp.resv = vm->root.bo->tbo.base.resv; - r = amdgpu_bo_create_vm(adev, &bp, vmbo); - if (r) - return r; - - bo = &(*vmbo)->bo; - if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) { - (*vmbo)->shadow = NULL; - return 0; - } - - if (!bp.resv) - WARN_ON(dma_resv_lock(bo->tbo.base.resv, - NULL)); - resv = bp.resv; - memset(&bp, 0, sizeof(bp)); - bp.size = amdgpu_vm_pt_size(adev, level); - bp.domain = AMDGPU_GEM_DOMAIN_GTT; - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; - bp.type = ttm_bo_type_kernel; - bp.resv = bo->tbo.base.resv; - bp.bo_ptr_size = sizeof(struct amdgpu_bo); - bp.xcp_id_plus1 = xcp_id + 1; - - r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow); - - if (!resv) - dma_resv_unlock(bo->tbo.base.resv); - - if (r) { - amdgpu_bo_unref(&bo); - return r; - } - - amdgpu_bo_add_to_shadow_list(*vmbo); - - return 0; + return amdgpu_bo_create_vm(adev, &bp, vmbo); } /** @@ -569,7 +523,6 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, return 0; error_free_pt: - amdgpu_bo_unref(&pt->shadow); amdgpu_bo_unref(&pt_bo); return r; } @@ -581,17 +534,10 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, */ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) { - struct amdgpu_bo *shadow; - if (!entry->bo) return; entry->bo->vm_bo = NULL; - shadow = amdgpu_bo_shadowed(entry->bo); - if (shadow) { - ttm_bo_set_bulk_move(&shadow->tbo, NULL); - amdgpu_bo_unref(&shadow); - } ttm_bo_set_bulk_move(&entry->bo->tbo, NULL); spin_lock(&entry->vm->status_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 9b748d7058b5c..390432a22ddd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -35,16 +35,7 @@ */ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table) { - int r; - - r = amdgpu_ttm_alloc_gart(&table->bo.tbo); - if (r) - return r; - - if (table->shadow) - r = amdgpu_ttm_alloc_gart(&table->shadow->tbo); - - return r; + return amdgpu_ttm_alloc_gart(&table->bo.tbo); } /* Allocate a new job for @count PTE updates */ @@ -273,17 +264,13 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, if (!p->pages_addr) { /* set page commands needed */ - if (vmbo->shadow) - amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr, - count, incr, flags); amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count, incr, flags); return 0; } /* copy commands needed */ - ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * - (vmbo->shadow ? 2 : 1); + ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; /* for padding */ ndw -= 7; @@ -298,8 +285,6 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, pte[i] |= flags; } - if (vmbo->shadow) - amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes); amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes); pe += nptes * 8; -- 2.43.0

8 months

2
2
0 0

[PATCH AUTOSEL 6.10 66/70] drm/amdgpu: nuke the VM PD/PT shadow handling

by Sasha Levin

From: Christian König <christian.koenig(a)amd.com> [ Upstream commit 7181faaa4703705939580abffaf9cb5d6b50dbb7 ] This was only used as workaround for recovering the page tables after VRAM was lost and is no longer necessary after the function amdgpu_vm_bo_reset_state_machine() started to do the same. Compute never used shadows either, so the only proplematic case left is SVM and that is most likely not recoverable in any way when VRAM is lost. Signed-off-by: Christian König <christian.koenig(a)amd.com> Acked-by: Lijo Lazar <lijo.lazar(a)amd.com> Signed-off-by: Alex Deucher <alexander.deucher(a)amd.com> Signed-off-by: Sasha Levin <sashal(a)kernel.org> --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 87 +-------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 67 +--------------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 21 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 56 +------------ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 19 +---- 7 files changed, 6 insertions(+), 265 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f87d53e183c3d..b48e8066c01cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1078,10 +1078,6 @@ struct amdgpu_device { struct amdgpu_virt virt; - /* link all shadow bo */ - struct list_head shadow_list; - struct mutex shadow_list_lock; - /* record hw reset is performed */ bool has_hw_reset; u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e66546df0bc19..1df57a02a7598 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4072,9 +4072,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->mm_stats.lock); spin_lock_init(&adev->wb.lock); - INIT_LIST_HEAD(&adev->shadow_list); - mutex_init(&adev->shadow_list_lock); - INIT_LIST_HEAD(&adev->reset_list); INIT_LIST_HEAD(&adev->ras_list); @@ -4979,80 +4976,6 @@ static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) return 0; } -/** - * amdgpu_device_recover_vram - Recover some VRAM contents - * - * @adev: amdgpu_device pointer - * - * Restores the contents of VRAM buffers from the shadows in GTT. Used to - * restore things like GPUVM page tables after a GPU reset where - * the contents of VRAM might be lost. - * - * Returns: - * 0 on success, negative error code on failure. - */ -static int amdgpu_device_recover_vram(struct amdgpu_device *adev) -{ - struct dma_fence *fence = NULL, *next = NULL; - struct amdgpu_bo *shadow; - struct amdgpu_bo_vm *vmbo; - long r = 1, tmo; - - if (amdgpu_sriov_runtime(adev)) - tmo = msecs_to_jiffies(8000); - else - tmo = msecs_to_jiffies(100); - - dev_info(adev->dev, "recover vram bo from shadow start\n"); - mutex_lock(&adev->shadow_list_lock); - list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { - /* If vm is compute context or adev is APU, shadow will be NULL */ - if (!vmbo->shadow) - continue; - shadow = vmbo->shadow; - - /* No need to recover an evicted BO */ - if (!shadow->tbo.resource || - shadow->tbo.resource->mem_type != TTM_PL_TT || - shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || - shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) - continue; - - r = amdgpu_bo_restore_shadow(shadow, &next); - if (r) - break; - - if (fence) { - tmo = dma_fence_wait_timeout(fence, false, tmo); - dma_fence_put(fence); - fence = next; - if (tmo == 0) { - r = -ETIMEDOUT; - break; - } else if (tmo < 0) { - r = tmo; - break; - } - } else { - fence = next; - } - } - mutex_unlock(&adev->shadow_list_lock); - - if (fence) - tmo = dma_fence_wait_timeout(fence, false, tmo); - dma_fence_put(fence); - - if (r < 0 || tmo <= 0) { - dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); - return -EIO; - } - - dev_info(adev->dev, "recover vram bo from shadow done\n"); - return 0; -} - - /** * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf * @@ -5112,12 +5035,8 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, if (r) return r; - if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { + if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) amdgpu_inc_vram_lost(adev); - r = amdgpu_device_recover_vram(adev); - } - if (r) - return r; /* need to be called during full access so we can't do it later like * bare-metal does. @@ -5529,9 +5448,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, } } - if (!r) - r = amdgpu_device_recover_vram(tmp_adev); - else + if (r) tmp_adev->asic_reset_res = r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index c556c8b653fa4..5f3b2c157824e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -77,24 +77,6 @@ static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) amdgpu_bo_destroy(tbo); } -static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); - struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo; - struct amdgpu_bo_vm *vmbo; - - bo = shadow_bo->parent; - vmbo = to_amdgpu_bo_vm(bo); - /* in case amdgpu_device_recover_vram got NULL of bo->parent */ - if (!list_empty(&vmbo->shadow_list)) { - mutex_lock(&adev->shadow_list_lock); - list_del_init(&vmbo->shadow_list); - mutex_unlock(&adev->shadow_list_lock); - } - - amdgpu_bo_destroy(tbo); -} - /** * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo * @bo: buffer object to be checked @@ -108,8 +90,7 @@ static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) { if (bo->destroy == &amdgpu_bo_destroy || - bo->destroy == &amdgpu_bo_user_destroy || - bo->destroy == &amdgpu_bo_vm_destroy) + bo->destroy == &amdgpu_bo_user_destroy) return true; return false; @@ -722,52 +703,6 @@ int amdgpu_bo_create_vm(struct amdgpu_device *adev, return r; } -/** - * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list - * - * @vmbo: BO that will be inserted into the shadow list - * - * Insert a BO to the shadow list. - */ -void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); - - mutex_lock(&adev->shadow_list_lock); - list_add_tail(&vmbo->shadow_list, &adev->shadow_list); - vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo); - vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy; - mutex_unlock(&adev->shadow_list_lock); -} - -/** - * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow - * - * @shadow: &amdgpu_bo shadow to be restored - * @fence: dma_fence associated with the operation - * - * Copies a buffer object's shadow content back to the object. - * This is used for recovering a buffer from its shadow in case of a gpu - * reset where vram context may be lost. - * - * Returns: - * 0 for success or a negative error code on failure. - */ -int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) - -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - uint64_t shadow_addr, parent_addr; - - shadow_addr = amdgpu_bo_gpu_offset(shadow); - parent_addr = amdgpu_bo_gpu_offset(shadow->parent); - - return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, - amdgpu_bo_size(shadow), NULL, fence, - true, false, 0); -} - /** * amdgpu_bo_kmap - map an &amdgpu_bo buffer object * @bo: &amdgpu_bo buffer object to be mapped diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index bc42ccbde659a..a4fa1f296daec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -130,8 +130,6 @@ struct amdgpu_bo_user { struct amdgpu_bo_vm { struct amdgpu_bo bo; - struct amdgpu_bo *shadow; - struct list_head shadow_list; struct amdgpu_vm_bo_base entries[]; }; @@ -269,22 +267,6 @@ static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED; } -/** - * amdgpu_bo_shadowed - check if the BO is shadowed - * - * @bo: BO to be tested. - * - * Returns: - * NULL if not shadowed or else return a BO pointer. - */ -static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo) -{ - if (bo->tbo.type == ttm_bo_type_kernel) - return to_amdgpu_bo_vm(bo)->shadow; - - return NULL; -} - bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); @@ -343,9 +325,6 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo); void amdgpu_bo_get_memory(struct amdgpu_bo *bo, struct amdgpu_mem_stats *stats); -void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo); -int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, - struct dma_fence **fence); uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, uint32_t domain); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 0f7106066480e..4820277e3c550 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -465,7 +465,6 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, { uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm); struct amdgpu_vm_bo_base *bo_base; - struct amdgpu_bo *shadow; struct amdgpu_bo *bo; int r; @@ -486,16 +485,10 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, spin_unlock(&vm->status_lock); bo = bo_base->bo; - shadow = amdgpu_bo_shadowed(bo); r = validate(param, bo); if (r) return r; - if (shadow) { - r = validate(param, shadow); - if (r) - return r; - } if (bo->tbo.type != ttm_bo_type_kernel) { amdgpu_vm_bo_moved(bo_base); @@ -2125,10 +2118,6 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, { struct amdgpu_vm_bo_base *bo_base; - /* shadow bo doesn't have bo base, its validation needs its parent */ - if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo)) - bo = bo->parent; - for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; @@ -2456,7 +2445,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, root_bo = amdgpu_bo_ref(&root->bo); r = amdgpu_bo_reserve(root_bo, true); if (r) { - amdgpu_bo_unref(&root->shadow); amdgpu_bo_unref(&root_bo); goto error_free_delayed; } @@ -2548,11 +2536,6 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) vm->last_update = dma_fence_get_stub(); vm->is_compute_context = true; - /* Free the shadow bo for compute VM */ - amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow); - - goto unreserve_bo; - unreserve_bo: amdgpu_bo_unreserve(vm->root.bo); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index f07647a9a9d97..ad3a9e594a406 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -383,14 +383,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (r) return r; - if (vmbo->shadow) { - struct amdgpu_bo *shadow = vmbo->shadow; - - r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx); - if (r) - return r; - } - if (!drm_dev_enter(adev_to_drm(adev), &idx)) return -ENODEV; @@ -448,10 +440,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id) { struct amdgpu_bo_param bp; - struct amdgpu_bo *bo; - struct dma_resv *resv; unsigned int num_entries; - int r; memset(&bp, 0, sizeof(bp)); @@ -484,42 +473,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (vm->root.bo) bp.resv = vm->root.bo->tbo.base.resv; - r = amdgpu_bo_create_vm(adev, &bp, vmbo); - if (r) - return r; - - bo = &(*vmbo)->bo; - if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) { - (*vmbo)->shadow = NULL; - return 0; - } - - if (!bp.resv) - WARN_ON(dma_resv_lock(bo->tbo.base.resv, - NULL)); - resv = bp.resv; - memset(&bp, 0, sizeof(bp)); - bp.size = amdgpu_vm_pt_size(adev, level); - bp.domain = AMDGPU_GEM_DOMAIN_GTT; - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; - bp.type = ttm_bo_type_kernel; - bp.resv = bo->tbo.base.resv; - bp.bo_ptr_size = sizeof(struct amdgpu_bo); - bp.xcp_id_plus1 = xcp_id + 1; - - r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow); - - if (!resv) - dma_resv_unlock(bo->tbo.base.resv); - - if (r) { - amdgpu_bo_unref(&bo); - return r; - } - - amdgpu_bo_add_to_shadow_list(*vmbo); - - return 0; + return amdgpu_bo_create_vm(adev, &bp, vmbo); } /** @@ -569,7 +523,6 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, return 0; error_free_pt: - amdgpu_bo_unref(&pt->shadow); amdgpu_bo_unref(&pt_bo); return r; } @@ -581,17 +534,10 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, */ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) { - struct amdgpu_bo *shadow; - if (!entry->bo) return; entry->bo->vm_bo = NULL; - shadow = amdgpu_bo_shadowed(entry->bo); - if (shadow) { - ttm_bo_set_bulk_move(&shadow->tbo, NULL); - amdgpu_bo_unref(&shadow); - } ttm_bo_set_bulk_move(&entry->bo->tbo, NULL); spin_lock(&entry->vm->status_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 9b748d7058b5c..390432a22ddd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -35,16 +35,7 @@ */ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table) { - int r; - - r = amdgpu_ttm_alloc_gart(&table->bo.tbo); - if (r) - return r; - - if (table->shadow) - r = amdgpu_ttm_alloc_gart(&table->shadow->tbo); - - return r; + return amdgpu_ttm_alloc_gart(&table->bo.tbo); } /* Allocate a new job for @count PTE updates */ @@ -273,17 +264,13 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, if (!p->pages_addr) { /* set page commands needed */ - if (vmbo->shadow) - amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr, - count, incr, flags); amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count, incr, flags); return 0; } /* copy commands needed */ - ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * - (vmbo->shadow ? 2 : 1); + ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; /* for padding */ ndw -= 7; @@ -298,8 +285,6 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, pte[i] |= flags; } - if (vmbo->shadow) - amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes); amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes); pe += nptes * 8; -- 2.43.0

8 months

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Re: [PATCH 1/3] dma-buf: replace symbolic permission S_IRUGO with octal 0444

by Sumit Semwal

Hello Pintu, On Tue, 1 Oct 2024 at 23:16, Pintu Kumar <quic_pintu(a)quicinc.com> wrote: > > Symbolic permissions are not preferred, instead use the octal. > Also, fix other warnings/errors as well for cleanup. > > WARNING: Block comments use * on subsequent lines > + /* only support discovering the end of the buffer, > + but also allow SEEK_SET to maintain the idiomatic > > WARNING: Block comments use a trailing */ on a separate line > + SEEK_END(0), SEEK_CUR(0) pattern */ > > WARNING: Block comments use a trailing */ on a separate line > + * before passing the sgt back to the exporter. */ > > ERROR: "foo * bar" should be "foo *bar" > +static struct sg_table * __map_dma_buf(struct dma_buf_attachment *attach, > > WARNING: Symbolic permissions 'S_IRUGO' are not preferred. Consider using octal permissions '0444'. > + d = debugfs_create_file("bufinfo", S_IRUGO, dma_buf_debugfs_dir, > > total: 1 errors, 4 warnings, 1746 lines checked > > Signed-off-by: Pintu Kumar <quic_pintu(a)quicinc.com> Thanks for this patch - could you please also mention in the commit log how did you find this? It looks like you ran checkpatch, but it's not clear from the commit log. Since this patch does multiple things related to checkpatch warnings (change S_IRUGO to 0444, comments correction, function declaration correction), can I please ask you to change the commit title to also reflect that? > --- > drivers/dma-buf/dma-buf.c | 12 +++++++----- > 1 file changed, 7 insertions(+), 5 deletions(-) > > diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c > index 8892bc701a66..2e63d50e46d3 100644 > --- a/drivers/dma-buf/dma-buf.c > +++ b/drivers/dma-buf/dma-buf.c > @@ -176,8 +176,9 @@ static loff_t dma_buf_llseek(struct file *file, loff_t offset, int whence) > dmabuf = file->private_data; > > /* only support discovering the end of the buffer, > - but also allow SEEK_SET to maintain the idiomatic > - SEEK_END(0), SEEK_CUR(0) pattern */ > + * but also allow SEEK_SET to maintain the idiomatic > + * SEEK_END(0), SEEK_CUR(0) pattern. > + */ > if (whence == SEEK_END) > base = dmabuf->size; > else if (whence == SEEK_SET) > @@ -782,13 +783,14 @@ static void mangle_sg_table(struct sg_table *sg_table) > /* To catch abuse of the underlying struct page by importers mix > * up the bits, but take care to preserve the low SG_ bits to > * not corrupt the sgt. The mixing is undone in __unmap_dma_buf > - * before passing the sgt back to the exporter. */ > + * before passing the sgt back to the exporter. > + */ > for_each_sgtable_sg(sg_table, sg, i) > sg->page_link ^= ~0xffUL; > #endif > > } > -static struct sg_table * __map_dma_buf(struct dma_buf_attachment *attach, > +static struct sg_table *__map_dma_buf(struct dma_buf_attachment *attach, > enum dma_data_direction direction) > { > struct sg_table *sg_table; > @@ -1694,7 +1696,7 @@ static int dma_buf_init_debugfs(void) > > dma_buf_debugfs_dir = d; > > - d = debugfs_create_file("bufinfo", S_IRUGO, dma_buf_debugfs_dir, > + d = debugfs_create_file("bufinfo", 0444, dma_buf_debugfs_dir, > NULL, &dma_buf_debug_fops); > if (IS_ERR(d)) { > pr_debug("dma_buf: debugfs: failed to create node bufinfo\n"); > -- > 2.17.1 > Best, Sumit.

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