- Linaro-mm-sig - lists.linaro.org

Re: [PATCH 3/9] mm/cma: Allow dynamically creating CMA areas

by Thierry Reding

On Tue, Sep 02, 2025 at 10:27:01AM -0700, Frank van der Linden wrote: > On Tue, Sep 2, 2025 at 8:46 AM Thierry Reding <thierry.reding(a)gmail.com> wrote: > > > > From: Thierry Reding <treding(a)nvidia.com> > > > > There is no technical reason why there should be a limited number of CMA > > regions, so extract some code into helpers and use them to create extra > > functions (cma_create() and cma_free()) that allow creating and freeing, > > respectively, CMA regions dynamically at runtime. > > > > Note that these dynamically created CMA areas are treated specially and > > do not contribute to the number of total CMA pages so that this count > > still only applies to the fixed number of CMA areas. > > > > Signed-off-by: Thierry Reding <treding(a)nvidia.com> > > --- > > include/linux/cma.h | 16 ++++++++ > > mm/cma.c | 89 ++++++++++++++++++++++++++++++++++----------- > > 2 files changed, 83 insertions(+), 22 deletions(-) [...] > I agree that supporting dynamic CMA areas would be good. However, by > doing it like this, these CMA areas are invisible to the rest of the > system. E.g. cma_for_each_area() does not know about them. It seems a > bit inconsistent that there will now be some areas that are globally > known, and some that are not. That was kind of the point of this experiment. When I started on this I ran into the case where I was running out of predefined CMA areas and as I went looking for ways on how to fix this, I realized that there's not much reason to keep a global list of these areas. And even less reason to limit the number of CMA areas to this predefined list. Very little code outside of the core CMA code even uses this. There's one instance of cma_for_each_area() that I don't grok. There's another early MMU fixup for CMA areas in 32-bit ARM that. Other than that there's a few places where the total CMA page count is shown for informational purposes and I don't know how useful that really is because totalcma_pages doesn't really track how many pages are used for CMA, but pages that could potentially be used for CMA. And that's about it. It seems like there are cases where we might really need to globally know about some of these areas, specifically ones that are allocated very early during boot and then used for very specific purposes. However, it seems to me like CMA is more universally useful than just for these cases and I don't see the usefulness of tracking these more generic uses. > I am being somewhat selfish here, as I have some WIP code that needs > the global list :-) But I think the inconsistency is a more general > point than just what I want (and the s390 code does use > cma_for_each_area()). Maybe you could keep maintaining a global > structure containing all areas? If it's really useful to be able to access all CMA areas, then we could easily just add them all to a global linked list upon activation (we may still want/need to keep the predefined list around for all those early allocation cases). That way we'd get the best of both worlds. > What do you think are the chances of running out of the global count > of areas? Well, I did run out of CMA areas during the early VPR testing because I was initially testing with 16 areas and a different allocation scheme that turned out to cause too many resizes in common cases. However, given that the default is 8 on normal systems (20 on NUMA) and is configurable, it means that even with restricting this to 4 for VPR doesn't always guarantee that all 4 are available. Again, yes, we could keep bumping that number, but why not turn this into something a bit more robust where nobody has to know or care about how many there are? > Also, you say that "these are treated specially and do not contribute > to the number of total CMA pages". But, if I'm reading this right, you > do call cma_activate_area(), which will do > init_cma_reserved_pageblock() for each pageblock in it. Which adjusts > the CMA counters for the zone they are in. But your change does not > adjust totalcma_pages for dynamically created areas. That seems > inconsistent, too. I was referring to just totalcma_pages that isn't impacted by these dynamically allocated regions. This is, again, because I don't see why that information would be useful. It's a fairly easy change to update that value, so if people prefer that, I can add that. I don't see an immediate connection between totalcma_pages and init_cma_reserved_pageblock(). I thought the latter was primarily useful for making sure that the CMA pages can be migrated, which is still critical for this use-case. Thierry

3 months, 1 week

1
0
0 0

Re: [PATCH v9 06/11] firmware: qcom: scm: add support for object invocation

by kernel test robot

Hi Amirreza, kernel test robot noticed the following build warnings: [auto build test WARNING on 33bcf93b9a6b028758105680f8b538a31bc563cf] url: https://github.com/intel-lab-lkp/linux/commits/Amirreza-Zarrabi/tee-allow-a… base: 33bcf93b9a6b028758105680f8b538a31bc563cf patch link: https://lore.kernel.org/r/20250901-qcom-tee-using-tee-ss-without-mem-obj-v9… patch subject: [PATCH v9 06/11] firmware: qcom: scm: add support for object invocation config: i386-buildonly-randconfig-001-20250903 (https://download.01.org/0day-ci/archive/20250903/202509030554.WR3MNpCE-lkp@…) compiler: gcc-12 (Debian 12.2.0-14+deb12u1) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250903/202509030554.WR3MNpCE-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202509030554.WR3MNpCE-lkp@intel.com/ All warnings (new ones prefixed by >>): In file included from include/linux/device.h:15, from include/linux/dma-mapping.h:5, from drivers/firmware/qcom/qcom_scm.c:13: drivers/firmware/qcom/qcom_scm.c: In function 'qcom_scm_qtee_init': >> drivers/firmware/qcom/qcom_scm.c:2208:35: warning: format '%d' expects argument of type 'int', but argument 3 has type 'long int' [-Wformat=] 2208 | dev_err(scm->dev, "qcomtee: register failed: %d\n", | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/dev_printk.h:110:30: note: in definition of macro 'dev_printk_index_wrap' 110 | _p_func(dev, fmt, ##__VA_ARGS__); \ | ^~~ include/linux/dev_printk.h:154:56: note: in expansion of macro 'dev_fmt' 154 | dev_printk_index_wrap(_dev_err, KERN_ERR, dev, dev_fmt(fmt), ##__VA_ARGS__) | ^~~~~~~ drivers/firmware/qcom/qcom_scm.c:2208:17: note: in expansion of macro 'dev_err' 2208 | dev_err(scm->dev, "qcomtee: register failed: %d\n", | ^~~~~~~ drivers/firmware/qcom/qcom_scm.c:2208:63: note: format string is defined here 2208 | dev_err(scm->dev, "qcomtee: register failed: %d\n", | ~^ | | | int | %ld vim +2208 drivers/firmware/qcom/qcom_scm.c 2188 2189 static void qcom_scm_qtee_init(struct qcom_scm *scm) 2190 { 2191 struct platform_device *qtee_dev; 2192 u64 result, response_type; 2193 int ret; 2194 2195 /* 2196 * Probe for smcinvoke support. This will fail due to invalid buffers, 2197 * but first, it checks whether the call is supported in QTEE syscall 2198 * handler. If it is not supported, -EIO is returned. 2199 */ 2200 ret = qcom_scm_qtee_invoke_smc(0, 0, 0, 0, &result, &response_type); 2201 if (ret == -EIO) 2202 return; 2203 2204 /* Setup QTEE interface device. */ 2205 qtee_dev = platform_device_register_data(scm->dev, "qcomtee", 2206 PLATFORM_DEVID_NONE, NULL, 0); 2207 if (IS_ERR(qtee_dev)) { > 2208 dev_err(scm->dev, "qcomtee: register failed: %d\n", 2209 PTR_ERR(qtee_dev)); 2210 return; 2211 } 2212 2213 ret = devm_add_action_or_reset(scm->dev, qcom_scm_qtee_free, qtee_dev); 2214 if (ret) 2215 dev_err(scm->dev, "qcomtee: add action failed: %d\n", ret); 2216 } 2217 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

3 months, 1 week

1
0
0 0

[PATCH v1 00/10] vfio/pci: Allow MMIO regions to be exported through dma-buf

by Leon Romanovsky

Changelog: v1: * Changed commit messages. * Reused DMA_ATTR_MMIO attribute. * Returned support for multiple DMA ranges per-dMABUF. v0: https://lore.kernel.org/all/cover.1753274085.git.leonro@nvidia.com --------------------------------------------------------------------------- Based on "[PATCH v1 00/16] dma-mapping: migrate to physical address-based API" https://lore.kernel.org/all/cover.1754292567.git.leon@kernel.org series. --------------------------------------------------------------------------- This series extends the VFIO PCI subsystem to support exporting MMIO regions from PCI device BARs as dma-buf objects, enabling safe sharing of non-struct page memory with controlled lifetime management. This allows RDMA and other subsystems to import dma-buf FDs and build them into memory regions for PCI P2P operations. The series supports a use case for SPDK where a NVMe device will be owned by SPDK through VFIO but interacting with a RDMA device. The RDMA device may directly access the NVMe CMB or directly manipulate the NVMe device's doorbell using PCI P2P. However, as a general mechanism, it can support many other scenarios with VFIO. This dmabuf approach can be usable by iommufd as well for generic and safe P2P mappings. In addition to the SPDK use-case mentioned above, the capability added in this patch series can also be useful when a buffer (located in device memory such as VRAM) needs to be shared between any two dGPU devices or instances (assuming one of them is bound to VFIO PCI) as long as they are P2P DMA compatible. The implementation provides a revocable attachment mechanism using dma-buf move operations. MMIO regions are normally pinned as BARs don't change physical addresses, but access is revoked when the VFIO device is closed or a PCI reset is issued. This ensures kernel self-defense against potentially hostile userspace. The series includes significant refactoring of the PCI P2PDMA subsystem to separate core P2P functionality from memory allocation features, making it more modular and suitable for VFIO use cases that don't need struct page support. ----------------------------------------------------------------------- The series is based originally on https://lore.kernel.org/all/20250307052248.405803-1-vivek.kasireddy@intel.c… but heavily rewritten to be based on DMA physical API. ----------------------------------------------------------------------- The WIP branch can be found here: https://git.kernel.org/pub/scm/linux/kernel/git/leon/linux-rdma.git/log/?h=… Thanks Leon Romanovsky (8): PCI/P2PDMA: Remove redundant bus_offset from map state PCI/P2PDMA: Separate the mmap() support from the core logic PCI/P2PDMA: Simplify bus address mapping API PCI/P2PDMA: Refactor to separate core P2P functionality from memory allocation PCI/P2PDMA: Export pci_p2pdma_map_type() function types: move phys_vec definition to common header vfio/pci: Enable peer-to-peer DMA transactions by default vfio/pci: Add dma-buf export support for MMIO regions Vivek Kasireddy (2): vfio: Export vfio device get and put registration helpers vfio/pci: Share the core device pointer while invoking feature functions block/blk-mq-dma.c | 7 +- drivers/iommu/dma-iommu.c | 4 +- drivers/pci/p2pdma.c | 154 ++++++++---- drivers/vfio/pci/Kconfig | 20 ++ drivers/vfio/pci/Makefile | 2 + drivers/vfio/pci/vfio_pci_config.c | 22 +- drivers/vfio/pci/vfio_pci_core.c | 59 +++-- drivers/vfio/pci/vfio_pci_dmabuf.c | 390 +++++++++++++++++++++++++++++ drivers/vfio/pci/vfio_pci_priv.h | 23 ++ drivers/vfio/vfio_main.c | 2 + include/linux/dma-buf.h | 1 + include/linux/pci-p2pdma.h | 114 +++++---- include/linux/types.h | 5 + include/linux/vfio.h | 2 + include/linux/vfio_pci_core.h | 4 + include/uapi/linux/vfio.h | 25 ++ kernel/dma/direct.c | 4 +- mm/hmm.c | 2 +- 18 files changed, 715 insertions(+), 125 deletions(-) create mode 100644 drivers/vfio/pci/vfio_pci_dmabuf.c -- 2.50.1

3 months, 1 week

3
18
0 0

[PATCH v11 0/9] TEE subsystem for protected dma-buf allocations

by Jens Wiklander

Hi, This patch set allocates the protected DMA-bufs from a DMA-heap instantiated from the TEE subsystem. The TEE subsystem handles the DMA-buf allocations since it is the TEE (OP-TEE, AMD-TEE, TS-TEE, or perhaps a future QTEE) which sets up the protection for the memory used for the DMA-bufs. The DMA-heap uses a protected memory pool provided by the backend TEE driver, allowing it to choose how to allocate the protected physical memory. The allocated DMA-bufs must be imported with a new TEE_IOC_SHM_REGISTER_FD before they can be passed as arguments when requesting services from the secure world. Three use-cases (Secure Video Playback, Trusted UI, and Secure Video Recording) have been identified so far to serve as examples of what can be expected. The use-cases have predefined DMA-heap names, "protected,secure-video", "protected,trusted-ui", and "protected,secure-video-record". The backend driver registers protected memory pools for the use-cases it supports. Each use-case has its own protected memory pool since different use-cases require isolation from different parts of the system. A protected memory pool can be based on a static carveout instantiated while probing the TEE backend driver, or dynamically allocated from CMA (dma_alloc_pages()) and made protected as needed by the TEE. This can be tested on a RockPi 4B+ with the following steps: repo init -u https://github.com/jenswi-linaro/manifest.git -m rockpi4.xml \ -b prototype/sdp-v11 repo sync -j8 cd build make toolchains -j$(nproc) make all -j$(nproc) # Copy ../out/rockpi4.img to an SD card and boot the RockPi from that # Connect a monitor to the RockPi # login and at the prompt: gst-launch-1.0 videotestsrc ! \ aesenc key=1f9423681beb9a79215820f6bda73d0f \ iv=e9aa8e834d8d70b7e0d254ff670dd718 serialize-iv=true ! \ aesdec key=1f9423681beb9a79215820f6bda73d0f ! \ kmssink The aesdec module has been hacked to use an OP-TEE TA to decrypt the stream into protected DMA-bufs which are consumed by the kmssink. The primitive QEMU tests from previous patch sets can be tested on RockPi in the same way using: xtest --sdp-basic The primitive tests are tested on QEMU with the following steps: repo init -u https://github.com/jenswi-linaro/manifest.git -m qemu_v8.xml \ -b prototype/sdp-v11 repo sync -j8 cd build make toolchains -j$(nproc) make SPMC_AT_EL=1 all -j$(nproc) make SPMC_AT_EL=1 run-only # login and at the prompt: xtest --sdp-basic The SPMC_AT_EL=1 parameter configures the build with FF-A and an SPMC at S-EL1 inside OP-TEE. The parameter can be changed to SPMC_AT_EL=n to test without FF-A using the original SMC ABI instead. Please remember to do %make arm-tf-clean for TF-A to be rebuilt properly using the new configuration. https://optee.readthedocs.io/en/latest/building/prerequisites.html list dependencies required to build the above. The primitive tests are pretty basic, mostly checking that a Trusted Application in the secure world can access and manipulate the memory. There are also some negative tests for out of bounds buffers, etc. Thanks, Jens Changes since V10: * Changed the new ABI OPTEE_MSG_CMD_GET_PROTMEM_CONFIG to report a list of u32 memory attributes instead of u16 endpoints to make room for both endpoint and access permissions in each entry. * In "tee: new ioctl to a register tee_shm from a dmabuf file descriptor", remove the unused path for DMA-bufs allocated by other means than the on in the TEE SS. * In "tee: implement protected DMA-heap", handle unloading of the backend driver module implementing the heap. The heap is reference counted and also calls tee_device_get() to guarantee that the module remains available while the heap is instantiated. * In "optee: support protected memory allocation", use dma_coerce_mask_and_coherent() instead of open-coding the function. * Added Sumit's R-B to - "optee: smc abi: dynamic protected memory allocation" - "optee: FF-A: dynamic protected memory allocation" - "optee: support protected memory allocation" - "tee: implement protected DMA-heap" - "dma-buf: dma-heap: export declared functions" Changes since V9: * Adding Sumit's R-B to "optee: sync secure world ABI headers" * Update commit message as requested for "dma-buf: dma-heap: export declared functions". * In "tee: implement protected DMA-heap": - add the hidden config option TEE_DMABUF_HEAPS to tell if the TEE subsystem can support DMA heaps - add a pfn_valid() to check that the passed physical address can be used by __pfn_to_page() and friends - remove the memremap() call, the caller is should do that instead if needed * In "tee: add tee_shm_alloc_dma_mem()" guard the calls to dma_alloc_pages() and dma_free_pages() with TEE_DMABUF_HEAPS to avoid linking errors in some configurations * In "optee: support protected memory allocation": - add the hidden config option OPTEE_STATIC_PROTMEM_POOL to tell if the driver can support a static protected memory pool - optee_protmem_pool_init() is slightly refactored to make the patches that follow easier - Call devm_memremap() before calling tee_protmem_static_pool_alloc() Changes since V8: * Using dma_alloc_pages() instead of cma_alloc() so the direct dependency on CMA can be removed together with the patches "cma: export cma_alloc() and cma_release()" and "dma-contiguous: export dma_contiguous_default_area". The patch * Renaming the patch "tee: add tee_shm_alloc_cma_phys_mem()" to "tee: add tee_shm_alloc_dma_mem()" * Setting DMA mask for the OP-TEE TEE device based on input from the secure world instead of relying on the parent device so following patches are removed: "tee: tee_device_alloc(): copy dma_mask from parent device" and "optee: pass parent device to tee_device_alloc()". * Adding Sumit Garg's R-B to "tee: refactor params_from_user()" * In the patch "tee: implement protected DMA-heap", map the physical memory passed to tee_protmem_static_pool_alloc(). Changes since V7: * Adding "dma-buf: dma-heap: export declared functions", "cma: export cma_alloc() and cma_release()", and "dma-contiguous: export dma_contiguous_default_area" to export the symbols needed to keep the TEE subsystem as a load module. * Removing CONFIG_TEE_DMABUF_HEAP and CONFIG_TEE_CMA since they aren't needed any longer. * Addressing review comments in "optee: sync secure world ABI headers" * Better align protected memory pool initialization between the smc-abi and ffa-abi parts of the optee driver. * Removing the patch "optee: account for direction while converting parameters" Changes since V6: * Restricted memory is now known as protected memory since to use the same term as https://docs.vulkan.org/guide/latest/protected.html. Update all patches to consistently use protected memory. * In "tee: implement protected DMA-heap" add the hidden config option TEE_DMABUF_HEAP to tell if the DMABUF_HEAPS functions are available for the TEE subsystem * Adding "tee: refactor params_from_user()", broken out from the patch "tee: new ioctl to a register tee_shm from a dmabuf file descriptor" * For "tee: new ioctl to a register tee_shm from a dmabuf file descriptor": - Update commit message to mention protected memory - Remove and open code tee_shm_get_parent_shm() in param_from_user_memref() * In "tee: add tee_shm_alloc_cma_phys_mem" add the hidden config option TEE_CMA to tell if the CMA functions are available for the TEE subsystem * For "tee: tee_device_alloc(): copy dma_mask from parent device" and "optee: pass parent device to tee_device_alloc", added Reviewed-by: Sumit Garg <sumit.garg(a)kernel.org> Changes since V5: * Removing "tee: add restricted memory allocation" and "tee: add TEE_IOC_RSTMEM_FD_INFO" * Adding "tee: implement restricted DMA-heap", "tee: new ioctl to a register tee_shm from a dmabuf file descriptor", "tee: add tee_shm_alloc_cma_phys_mem()", "optee: pass parent device to tee_device_alloc()", and "tee: tee_device_alloc(): copy dma_mask from parent device" * The two TEE driver OPs "rstmem_alloc()" and "rstmem_free()" are replaced with a struct tee_rstmem_pool abstraction. * Replaced the the TEE_IOC_RSTMEM_ALLOC user space API with the DMA-heap API Changes since V4: * Adding the patch "tee: add TEE_IOC_RSTMEM_FD_INFO" needed by the GStreamer demo * Removing the dummy CPU access and mmap functions from the dma_buf_ops * Fixing a compile error in "optee: FF-A: dynamic restricted memory allocation" reported by kernel test robot <lkp(a)intel.com> Changes since V3: * Make the use_case and flags field in struct tee_shm u32's instead of u16's * Add more description for TEE_IOC_RSTMEM_ALLOC in the header file * Import namespace DMA_BUF in module tee, reported by lkp(a)intel.com * Added a note in the commit message for "optee: account for direction while converting parameters" why it's needed * Factor out dynamic restricted memory allocation from "optee: support restricted memory allocation" into two new commits "optee: FF-A: dynamic restricted memory allocation" and "optee: smc abi: dynamic restricted memory allocation" * Guard CMA usage with #ifdef CONFIG_CMA, effectively disabling dynamic restricted memory allocate if CMA isn't configured Changes since the V2 RFC: * Based on v6.12 * Replaced the flags for SVP and Trusted UID memory with a u32 field with unique id for each use case * Added dynamic allocation of restricted memory pools * Added OP-TEE ABI both with and without FF-A for dynamic restricted memory * Added support for FF-A with FFA_LEND Changes since the V1 RFC: * Based on v6.11 * Complete rewrite, replacing the restricted heap with TEE_IOC_RSTMEM_ALLOC Changes since Olivier's post [2]: * Based on Yong Wu's post [1] where much of dma-buf handling is done in the generic restricted heap * Simplifications and cleanup * New commit message for "dma-buf: heaps: add Linaro restricted dmabuf heap support" * Replaced the word "secure" with "restricted" where applicable Etienne Carriere (1): tee: new ioctl to a register tee_shm from a dmabuf file descriptor Jens Wiklander (8): optee: sync secure world ABI headers dma-buf: dma-heap: export declared functions tee: implement protected DMA-heap tee: refactor params_from_user() tee: add tee_shm_alloc_dma_mem() optee: support protected memory allocation optee: FF-A: dynamic protected memory allocation optee: smc abi: dynamic protected memory allocation drivers/dma-buf/dma-heap.c | 3 + drivers/tee/Kconfig | 5 + drivers/tee/Makefile | 1 + drivers/tee/optee/Kconfig | 5 + drivers/tee/optee/Makefile | 1 + drivers/tee/optee/core.c | 7 + drivers/tee/optee/ffa_abi.c | 146 ++++++++- drivers/tee/optee/optee_ffa.h | 27 +- drivers/tee/optee/optee_msg.h | 84 ++++- drivers/tee/optee/optee_private.h | 15 +- drivers/tee/optee/optee_smc.h | 37 ++- drivers/tee/optee/protmem.c | 335 ++++++++++++++++++++ drivers/tee/optee/smc_abi.c | 141 ++++++++- drivers/tee/tee_core.c | 157 +++++++--- drivers/tee/tee_heap.c | 500 ++++++++++++++++++++++++++++++ drivers/tee/tee_private.h | 14 + drivers/tee/tee_shm.c | 157 +++++++++- include/linux/tee_core.h | 59 ++++ include/linux/tee_drv.h | 10 + include/uapi/linux/tee.h | 31 ++ 20 files changed, 1668 insertions(+), 67 deletions(-) create mode 100644 drivers/tee/optee/protmem.c create mode 100644 drivers/tee/tee_heap.c base-commit: 038d61fd642278bab63ee8ef722c50d10ab01e8f -- 2.43.0

3 months, 2 weeks

1
10
0 0

[PATCH v3 00/14] Rust abstractions for shmem-backed GEM objects

by Lyude Paul

This is the next version of the shmem backed GEM objects series originally from Asahi, previously posted by Daniel Almeida. Along with bindings for shmem backed GEM objects. This applies on top of Danilo and Abdiel's sgtable patches: https://lkml.org/lkml/2025/8/28/1018 Asahi Lina (2): rust: helpers: Add bindings/wrappers for dma_resv_lock rust: drm: gem: shmem: Add DRM shmem helper abstraction Lyude Paul (12): rust: drm: gem: Simplify use of generics rust: drm: gem: Add DriverFile type alias rust: drm: gem: Drop Object::SIZE rust: drm: gem: Support driver-private GEM object types rust: drm: gem: Add raw_dma_resv() function drm/gem/shmem: Extract drm_gem_shmem_init() from drm_gem_shmem_create() drm/gem/shmem: Extract drm_gem_shmem_release() from drm_gem_shmem_free() rust: gem: Introduce DriverObject::Args rust: drm: gem: Introduce SGTableRef rust: Add dma_buf stub bindings rust: drm: gem: Add export() callback rust: drm: gem: Add BaseObject::prime_export() drivers/gpu/drm/drm_gem_shmem_helper.c | 98 +++++-- drivers/gpu/drm/nova/driver.rs | 8 +- drivers/gpu/drm/nova/gem.rs | 15 +- include/drm/drm_gem_shmem_helper.h | 2 + rust/bindings/bindings_helper.h | 3 + rust/helpers/dma-resv.c | 13 + rust/helpers/drm.c | 48 +++- rust/helpers/helpers.c | 1 + rust/kernel/dma_buf.rs | 39 +++ rust/kernel/drm/device.rs | 17 +- rust/kernel/drm/driver.rs | 5 +- rust/kernel/drm/gem/mod.rs | 274 +++++++++++++++---- rust/kernel/drm/gem/shmem.rs | 365 +++++++++++++++++++++++++ rust/kernel/lib.rs | 1 + 14 files changed, 783 insertions(+), 106 deletions(-) create mode 100644 rust/helpers/dma-resv.c create mode 100644 rust/kernel/dma_buf.rs create mode 100644 rust/kernel/drm/gem/shmem.rs base-commit: 09f90256e8902793f594517ef440698585eb3595 prerequisite-patch-id: 0e1b1f9a665317ff569a37df6ff49cd1880b04f8 prerequisite-patch-id: 178b864e6d1b88ee299dcc05d1a7a4c89ec7ed51 prerequisite-patch-id: 7f72c4bfd0e5f50b6d2f8ce96751782894a3ba81 prerequisite-patch-id: 62fa6de7d3ae99dc54c092087bd716e6749545fd prerequisite-patch-id: 3d14d56ca93b0831837aa26b802100a250adeac6 prerequisite-patch-id: 7a12f4b0e7588874ce589b41b70671dc261b9468 prerequisite-patch-id: c44763ec35c4e4431e769df088b98424cbddf7df prerequisite-patch-id: a9e008c179b1c2fbe76654a191e5018880383d49 prerequisite-patch-id: 1e9ce500ce25188c575be608cd39e15a59836f83 prerequisite-patch-id: 39ca3a210a6c365434924c07a0c98a074eb73b97 prerequisite-patch-id: a747e05834cdb8b8f727e1f7c8b110c636cadab8 prerequisite-patch-id: 24833689bdecd3fc7a604e13bfe203ccd2fca6f0 -- 2.50.0

3 months, 2 weeks

1
5
0 0

Re: [PATCH v8 09/11] qcomtee: add primordial object

by Bjorn Andersson

On Wed, Aug 20, 2025 at 04:38:56PM -0700, Amirreza Zarrabi wrote: Looking at other commits in drivers/tee/ I'd expect the subject prefix to be "tee: qcom: ". > After booting, the kernel provides a static object known as the > primordial object. This object is utilized by QTEE for native > kernel services such as yield or privileged operations. > > Acked-by: Sumit Garg <sumit.garg(a)oss.qualcomm.com> > Tested-by: Neil Armstrong <neil.armstrong(a)linaro.org> > Tested-by: Harshal Dev <quic_hdev(a)quicinc.com> > Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi(a)oss.qualcomm.com> > --- > drivers/tee/qcomtee/Makefile | 1 + > drivers/tee/qcomtee/core.c | 19 ++++++++--- > drivers/tee/qcomtee/primordial_obj.c | 66 ++++++++++++++++++++++++++++++++++++ > drivers/tee/qcomtee/qcomtee.h | 3 ++ > 4 files changed, 84 insertions(+), 5 deletions(-) > > diff --git a/drivers/tee/qcomtee/Makefile b/drivers/tee/qcomtee/Makefile > index 600af2b8f1c1..78f8e899d143 100644 > --- a/drivers/tee/qcomtee/Makefile > +++ b/drivers/tee/qcomtee/Makefile > @@ -3,5 +3,6 @@ obj-$(CONFIG_QCOMTEE) += qcomtee.o > qcomtee-objs += async.o > qcomtee-objs += call.o > qcomtee-objs += core.o > +qcomtee-objs += primordial_obj.o > qcomtee-objs += shm.o > qcomtee-objs += user_obj.o > diff --git a/drivers/tee/qcomtee/core.c b/drivers/tee/qcomtee/core.c > index 578299a3eabc..561a48319f91 100644 > --- a/drivers/tee/qcomtee/core.c > +++ b/drivers/tee/qcomtee/core.c > @@ -31,10 +31,12 @@ int qcomtee_next_arg_type(struct qcomtee_arg *u, int i, > } > > /* > - * QTEE expects IDs with the QCOMTEE_MSG_OBJECT_NS_BIT set for objects > - * of the QCOMTEE_OBJECT_TYPE_CB type. > + * QTEE expects IDs with QCOMTEE_MSG_OBJECT_NS_BIT set for objects of > + * QCOMTEE_OBJECT_TYPE_CB type. The first ID with QCOMTEE_MSG_OBJECT_NS_BIT > + * set is reserved for the primordial object. > */ > -#define QCOMTEE_OBJECT_ID_START (QCOMTEE_MSG_OBJECT_NS_BIT + 1) > +#define QCOMTEE_OBJECT_PRIMORDIAL (QCOMTEE_MSG_OBJECT_NS_BIT) > +#define QCOMTEE_OBJECT_ID_START (QCOMTEE_OBJECT_PRIMORDIAL + 1) > #define QCOMTEE_OBJECT_ID_END (U32_MAX) > > #define QCOMTEE_OBJECT_SET(p, type, ...) \ > @@ -157,7 +159,9 @@ static void qcomtee_object_release(struct kref *refcount) > */ > int qcomtee_object_get(struct qcomtee_object *object) > { > - if (object != NULL_QCOMTEE_OBJECT && object != ROOT_QCOMTEE_OBJECT) > + if (object != &qcomtee_primordial_object && > + object != NULL_QCOMTEE_OBJECT && > + object != ROOT_QCOMTEE_OBJECT) > return kref_get_unless_zero(&object->refcount); > > return 0; > @@ -169,7 +173,9 @@ int qcomtee_object_get(struct qcomtee_object *object) > */ > void qcomtee_object_put(struct qcomtee_object *object) > { > - if (object != NULL_QCOMTEE_OBJECT && object != ROOT_QCOMTEE_OBJECT) > + if (object != &qcomtee_primordial_object && > + object != NULL_QCOMTEE_OBJECT && > + object != ROOT_QCOMTEE_OBJECT) > kref_put(&object->refcount, qcomtee_object_release); > } > > @@ -261,6 +267,9 @@ qcomtee_local_object_get(struct qcomtee_object_invoke_ctx *oic, > struct qcomtee *qcomtee = tee_get_drvdata(oic->ctx->teedev); > struct qcomtee_object *object; > > + if (object_id == QCOMTEE_OBJECT_PRIMORDIAL) > + return &qcomtee_primordial_object; > + > guard(rcu)(); > object = xa_load(&qcomtee->xa_local_objects, object_id); > /* It already checks for %NULL_QCOMTEE_OBJECT. */ > diff --git a/drivers/tee/qcomtee/primordial_obj.c b/drivers/tee/qcomtee/primordial_obj.c > new file mode 100644 > index 000000000000..df94fbf5f141 > --- /dev/null > +++ b/drivers/tee/qcomtee/primordial_obj.c > @@ -0,0 +1,66 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt I don't see any pr_*() functions in this file, please drop this. Regards, Bjorn > + > +#include <linux/delay.h> > + > +#include "qcomtee.h" > + > +/** > + * DOC: Primordial Object > + * > + * After boot, the kernel provides a static object of type > + * %QCOMTEE_OBJECT_TYPE_CB called the primordial object. This object is used > + * for native kernel services or privileged operations. > + * > + * We support: > + * - %QCOMTEE_OBJECT_OP_YIELD to yield by the thread running in QTEE. > + * - %QCOMTEE_OBJECT_OP_SLEEP to wait for a period of time. > + */ > + > +#define QCOMTEE_OBJECT_OP_YIELD 1 > +#define QCOMTEE_OBJECT_OP_SLEEP 2 > + > +static int > +qcomtee_primordial_obj_dispatch(struct qcomtee_object_invoke_ctx *oic, > + struct qcomtee_object *primordial_object_unused, > + u32 op, struct qcomtee_arg *args) > +{ > + int err = 0; > + > + switch (op) { > + case QCOMTEE_OBJECT_OP_YIELD: > + cond_resched(); > + /* No output object. */ > + oic->data = NULL; > + break; > + case QCOMTEE_OBJECT_OP_SLEEP: > + /* Check message format matched QCOMTEE_OBJECT_OP_SLEEP op. */ > + if (qcomtee_args_len(args) != 1 || > + args[0].type != QCOMTEE_ARG_TYPE_IB || > + args[0].b.size < sizeof(u32)) > + return -EINVAL; > + > + msleep(*(u32 *)(args[0].b.addr)); > + /* No output object. */ > + oic->data = NULL; > + break; > + default: > + err = -EINVAL; > + } > + > + return err; > +} > + > +static struct qcomtee_object_operations qcomtee_primordial_obj_ops = { > + .dispatch = qcomtee_primordial_obj_dispatch, > +}; > + > +struct qcomtee_object qcomtee_primordial_object = { > + .name = "primordial", > + .object_type = QCOMTEE_OBJECT_TYPE_CB, > + .ops = &qcomtee_primordial_obj_ops > +}; > diff --git a/drivers/tee/qcomtee/qcomtee.h b/drivers/tee/qcomtee/qcomtee.h > index f34be992e68b..084b3882017e 100644 > --- a/drivers/tee/qcomtee/qcomtee.h > +++ b/drivers/tee/qcomtee/qcomtee.h > @@ -140,4 +140,7 @@ int qcomtee_user_object_submit(struct tee_context *ctx, > struct tee_param *params, int num_params, > int req_id, int errno); > > +/* (2) Primordial Object. */ > +extern struct qcomtee_object qcomtee_primordial_object; > + > #endif /* QCOMTEE_H */ > > -- > 2.34.1 >

3 months, 2 weeks

1
0
0 0

Re: [PATCH v8 06/11] firmware: qcom: scm: add support for object invocation

by Bjorn Andersson

On Wed, Aug 20, 2025 at 04:38:53PM -0700, Amirreza Zarrabi wrote: > diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c [..] > +static void qcom_scm_qtee_free(void *data) > +{ > + struct platform_device *qtee_dev = data; > + > + platform_device_unregister(qtee_dev); > +} > + > +static int qcom_scm_qtee_init(struct qcom_scm *scm) > +{ > + struct platform_device *qtee_dev; > + u64 result, response_type; > + int ret; > + > + /* > + * Check if QTEE supports smcinvoke: > + * This will fail due to invalid buffers, but first, it checks whether > + * the call is supported in QTEE syscall handler. > + * If not supported, -EIO is returned. > + */ > + ret = qcom_scm_qtee_invoke_smc(0, 0, 0, 0, &result, &response_type); > + if (ret == -EIO) > + return -EIO; > + > + /* Setup QTEE interface device. */ > + qtee_dev = platform_device_alloc("qcomtee", -1); > + if (!qtee_dev) > + return -ENOMEM; > + > + qtee_dev->dev.parent = scm->dev; > + > + ret = platform_device_add(qtee_dev); > + if (ret) { > + platform_device_put(qtee_dev); > + return ret; > + } Wouldn't this work instead of the alloc + parent + add? qtee_dev = platform_device_alloc_data(scm->dev, "qcomtee", -1, NULL, 0); if (IS_ERR(qtee_dev)) return PTR_ERR(qtee_dev); > + > + return devm_add_action_or_reset(scm->dev, qcom_scm_qtee_free, qtee_dev); > +} > + > /** > * qcom_scm_is_available() - Checks if SCM is available > */ > @@ -2326,6 +2450,16 @@ static int qcom_scm_probe(struct platform_device *pdev) > ret = qcom_scm_qseecom_init(scm); > WARN(ret < 0, "failed to initialize qseecom: %d\n", ret); > > + /* > + * Initialize the QTEE object interface. > + * > + * This only represents the availability for QTEE object invocation > + * and callback support. On failure, ignore the result. Any subsystem > + * depending on it may fail if it tries to access this interface. > + */ > + ret = qcom_scm_qtee_init(scm); > + dev_warn_probe(scm->dev, ret, "Failed to initialize qcomtee\n"); A successful boot of db410c (APQ8016) now has the following in the log: [ 0.161437] qcom_scm firmware:scm: error -EIO: Failed to initialize qcomtee If the target doesn't implement qtee, I'd expect that you tell me that - or preferably stay silent. Looking at the other error conditions, we find -ENOMEM, for which you should also avoid printing. In fact, I believe all other error paths of qcom_scm_qtee_init() will have printed an error already (if not, please move the error print to the place(s) where it's needed). As you're ignoring the return value, please then also change the return type of the function to void. Regards, Bjorn > + > return 0; > }

3 months, 2 weeks

1
0
0 0

Re: [PATCH v4 3/3] drm: tiny: Add support for Mayqueen Pixpaper e-ink panel

by Thomas Zimmermann

Hi, apologies for the slow review. This looks good already with only a few small requests below. Am 05.08.25 um 07:40 schrieb LiangCheng Wang: > Introduce a DRM driver for the Mayqueen Pixpaper e-ink display panel, > which is controlled via SPI. The driver supports a 122x250 resolution > display with XRGB8888 format. > > Also, add a MAINTAINERS entry for the Pixpaper driver. > > Signed-off-by: LiangCheng Wang <zaq14760(a)gmail.com> > --- > MAINTAINERS | 7 + > drivers/gpu/drm/tiny/Kconfig | 15 + > drivers/gpu/drm/tiny/Makefile | 1 + > drivers/gpu/drm/tiny/pixpaper-regs.h | 428 +++++++++++++++++++ Please integrate this header file to the top of pixpaper.c. There are no other users of these values and the file is still of manageable size. > drivers/gpu/drm/tiny/pixpaper.c | 789 +++++++++++++++++++++++++++++++++++ > 5 files changed, 1240 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index 1b57dd4fcf0154cdea9f83bccf5be3325f87d993..fe25537276c25eabfb38253c0e1352ed0d1ebb86 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -7866,6 +7866,13 @@ T: git https://gitlab.freedesktop.org/drm/misc/kernel.git > F: Documentation/devicetree/bindings/display/repaper.txt > F: drivers/gpu/drm/tiny/repaper.c > > +DRM DRIVER FOR PIXPAPER E-INK PANEL > +M: LiangCheng Wang <zaq14760(a)gmail.com> > +S: Maintained > +F: Documentation/devicetree/bindings/display/mayqueen,pixpaper.yaml > +F: drivers/gpu/drm/tiny/pixpaper-regs.h > +F: drivers/gpu/drm/tiny/pixpaper.c You should add L: dri-devel(a)lists.freedesktop.org as well, so others can tell the correct mailing list. > + > DRM DRIVER FOR QEMU'S CIRRUS DEVICE > M: Dave Airlie <airlied(a)redhat.com> > M: Gerd Hoffmann <kraxel(a)redhat.com> > diff --git a/drivers/gpu/drm/tiny/Kconfig b/drivers/gpu/drm/tiny/Kconfig > index 06e54694a7f2fe1649e1886f039926b24f698e0d..94a5bf61a115929640022128e20c723ab7c0e735 100644 > --- a/drivers/gpu/drm/tiny/Kconfig > +++ b/drivers/gpu/drm/tiny/Kconfig > @@ -82,6 +82,21 @@ config DRM_PANEL_MIPI_DBI > https://github.com/notro/panel-mipi-dbi/wiki. > To compile this driver as a module, choose M here. > > +config DRM_PIXPAPER > + tristate "DRM support for PIXPAPER display panels" > + depends on DRM && SPI > + select DRM_CLIENT_SELECTION > + select DRM_GEM_DMA_HELPER > + select DRM_KMS_HELPER > + help > + DRM driver for the Mayqueen Pixpaper e-ink display panel. > + > + This driver supports small e-paper displays connected over SPI, > + with a resolution of 122x250 and XRGB8888 framebuffer format. > + It is intended for low-power embedded applications. > + > + If M is selected, the module will be built as pixpaper.ko. > + > config TINYDRM_HX8357D > tristate "DRM support for HX8357D display panels" > depends on DRM && SPI > diff --git a/drivers/gpu/drm/tiny/Makefile b/drivers/gpu/drm/tiny/Makefile > index 4a9ff61ec25420e2c0a648c04eaab7ca25dd5407..48d30bf6152f979404ac1004174587823a30109e 100644 > --- a/drivers/gpu/drm/tiny/Makefile > +++ b/drivers/gpu/drm/tiny/Makefile > @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_BOCHS) += bochs.o > obj-$(CONFIG_DRM_CIRRUS_QEMU) += cirrus-qemu.o > obj-$(CONFIG_DRM_GM12U320) += gm12u320.o > obj-$(CONFIG_DRM_PANEL_MIPI_DBI) += panel-mipi-dbi.o > +obj-$(CONFIG_DRM_PIXPAPER) += pixpaper.o > obj-$(CONFIG_TINYDRM_HX8357D) += hx8357d.o > obj-$(CONFIG_TINYDRM_ILI9163) += ili9163.o > obj-$(CONFIG_TINYDRM_ILI9225) += ili9225.o > diff --git a/drivers/gpu/drm/tiny/pixpaper-regs.h b/drivers/gpu/drm/tiny/pixpaper-regs.h > new file mode 100644 > index 0000000000000000000000000000000000000000..d6ea0531ded6879c13de334345cef7add210b931 > --- /dev/null > +++ b/drivers/gpu/drm/tiny/pixpaper-regs.h > @@ -0,0 +1,428 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Register definitions for PIXPAPER e-ink panel > + * > + * Author: LiangCheng Wang <zaq14760(a)gmail.com> > + */ > + > +#ifndef __PIXPAPER_REGS_H__ > +#define __PIXPAPER_REGS_H__ > + > +/* > + * Note on Undocumented Commands/Registers: > + * > + * Several commands and register parameters defined in this header are not > + * documented in the datasheet. Their values and usage have been derived > + * through analysis of existing userspace example programs. > + * > + * These 'unknown' definitions are crucial for the proper initialization > + * and stable operation of the panel. Modifying these values without > + * thorough understanding may lead to display anomalies, panel damage, > + * or unexpected behavior. > + */ > + > +/* Command definitions */ > +#define PIXPAPER_CMD_PANEL_SETTING 0x00 /* R00H: Panel settings */ > +#define PIXPAPER_CMD_POWER_SETTING 0x01 /* R01H: Power settings */ > +#define PIXPAPER_CMD_POWER_OFF 0x02 /* R02H: Power off */ > +#define PIXPAPER_CMD_POWER_OFF_SEQUENCE 0x03 /* R03H: Power off sequence */ > +#define PIXPAPER_CMD_POWER_ON 0x04 /* R04H: Power on */ > +#define PIXPAPER_CMD_BOOSTER_SOFT_START 0x06 /* R06H: Booster soft start */ > +#define PIXPAPER_CMD_DEEP_SLEEP 0x07 /* R07H: Deep sleep */ > +#define PIXPAPER_CMD_DATA_START_TRANSMISSION 0x10 > +/* R10H: Data transmission start */ > +#define PIXPAPER_CMD_DISPLAY_REFRESH 0x12 /* R12H: Display refresh */ > +#define PIXPAPER_CMD_PLL_CONTROL 0x30 /* R30H: PLL control */ > +#define PIXPAPER_CMD_TEMP_SENSOR_CALIB 0x41 > +/* R41H: Temperature sensor calibration */ > +#define PIXPAPER_CMD_UNKNOWN_4D 0x4D /* R4DH: Unknown command */ > +#define PIXPAPER_CMD_VCOM_INTERVAL 0x50 /* R50H: VCOM interval */ > +#define PIXPAPER_CMD_UNKNOWN_60 0x60 /* R60H: Unknown command */ > +#define PIXPAPER_CMD_RESOLUTION_SETTING 0x61 /* R61H: Resolution settings */ > +#define PIXPAPER_CMD_GATE_SOURCE_START 0x65 /* R65H: Gate/source start */ > +#define PIXPAPER_CMD_UNKNOWN_B4 0xB4 /* RB4H: Unknown command */ > +#define PIXPAPER_CMD_UNKNOWN_B5 0xB5 /* RB5H: Unknown command */ > +#define PIXPAPER_CMD_UNKNOWN_E0 0xE0 /* RE0H: Unknown command */ > +#define PIXPAPER_CMD_POWER_SAVING 0xE3 /* RE3H: Power saving */ > +#define PIXPAPER_CMD_UNKNOWN_E7 0xE7 /* RE7H: Unknown command */ > +#define PIXPAPER_CMD_UNKNOWN_E9 0xE9 /* RE9H: Unknown command */ > + > +/* R00H PSR - First Parameter */ > +#define PIXPAPER_PSR_RST_N BIT(0) > +/* Bit 0: RST_N, 1=no effect (default), 0=reset with booster OFF */ > +#define PIXPAPER_PSR_SHD_N BIT(1) > +/* Bit 1: SHD_N, 1=booster ON (default), 0=booster OFF */ > +#define PIXPAPER_PSR_SHL BIT(2) > +/* Bit 2: SHL, 1=shift right (default), 0=shift left */ > +#define PIXPAPER_PSR_UD BIT(3) > +/* Bit 3: UD, 1=scan up (default), 0=scan down */ > +#define PIXPAPER_PSR_PST_MODE BIT(5) > +/* Bit 5: PST_MODE, 0=frame scanning (default), 1=external */ > +#define PIXPAPER_PSR_RES_MASK (3 << 6) > +/* Bits 7-6: RES[1:0], resolution setting */ > +#define PIXPAPER_PSR_RES_176x296 (0x0 << 6) /* 00: 176x296 */ > +#define PIXPAPER_PSR_RES_128x296 (0x1 << 6) /* 01: 128x296 */ > +#define PIXPAPER_PSR_RES_128x250 (0x2 << 6) /* 10: 128x250 */ > +#define PIXPAPER_PSR_RES_112x204 (0x3 << 6) /* 11: 112x204 */ > +#define PIXPAPER_PSR_CONFIG \ > + (PIXPAPER_PSR_RST_N | PIXPAPER_PSR_SHD_N | PIXPAPER_PSR_SHL | \ > + PIXPAPER_PSR_UD) > +/* 0x0F: Default settings, resolution set by R61H */ > + > +/* R00H PSR - Second Parameter */ > +#define PIXPAPER_PSR2_VC_LUTZ \ > + (1 << 0) /* Bit 0: VC_LUTZ, 1=VCOM float after refresh (default), 0=no effect */ > +#define PIXPAPER_PSR2_NORG \ > + (1 << 1) /* Bit 1: NORG, 1=VCOM to GND before power off, 0=no effect (default) */ > +#define PIXPAPER_PSR2_TIEG \ > + (1 << 2) /* Bit 2: TIEG, 1=VGN to GND on power off, 0=no effect (default) */ > +#define PIXPAPER_PSR2_TS_AUTO \ > + (1 << 3) /* Bit 3: TS_AUTO, 1=sensor on RST_N low to high (default), 0=on booster */ > +#define PIXPAPER_PSR2_VCMZ \ > + (1 << 4) /* Bit 4: VCMZ, 1=VCOM always floating, 0=no effect (default) */ > +#define PIXPAPER_PSR2_FOPT \ > + (1 << 5) /* Bit 5: FOPT, 0=scan 1 frame (default), 1=no scan, HiZ */ > +#define PIXPAPER_PSR_CONFIG2 \ > + (PIXPAPER_PSR2_VC_LUTZ | \ > + PIXPAPER_PSR2_TS_AUTO) /* 0x09: Default VCOM and temp sensor settings */ > + > +/* R01H PWR - Power Setting Register */ > +/* First Parameter */ > +#define PIXPAPER_PWR_VDG_EN \ > + (1 << 0) /* Bit 0: VDG_EN, 1=internal DCDC for VGP/VGN (default), 0=external */ > +#define PIXPAPER_PWR_VDS_EN \ > + (1 << 1) /* Bit 1: VDS_EN, 1=internal regulator for VSP/VSN (default), 0=external */ > +#define PIXPAPER_PWR_VSC_EN \ > + (1 << 2) /* Bit 2: VSC_EN, 1=internal regulator for VSPL (default), 0=external */ > +#define PIXPAPER_PWR_V_MODE \ > + (1 << 3) /* Bit 3: V_MODE, 0=Mode0 (default), 1=Mode1 */ > +#define PIXPAPER_PWR_CONFIG1 \ > + (PIXPAPER_PWR_VDG_EN | PIXPAPER_PWR_VDS_EN | \ > + PIXPAPER_PWR_VSC_EN) /* 0x07: Internal power for VGP/VGN, VSP/VSN, VSPL */ > + > +/* Second Parameter */ > +#define PIXPAPER_PWR_VGPN_MASK \ > + (3 << 0) /* Bits 1-0: VGPN, VGP/VGN voltage levels */ > +#define PIXPAPER_PWR_VGPN_20V (0x0 << 0) /* 00: VGP=20V, VGN=-20V (default) */ > +#define PIXPAPER_PWR_VGPN_17V (0x1 << 0) /* 01: VGP=17V, VGN=-17V */ > +#define PIXPAPER_PWR_VGPN_15V (0x2 << 0) /* 10: VGP=15V, VGN=-15V */ > +#define PIXPAPER_PWR_VGPN_10V (0x3 << 0) /* 11: VGP=10V, VGN=-10V */ > +#define PIXPAPER_PWR_CONFIG2 PIXPAPER_PWR_VGPN_20V /* 0x00: VGP=20V, VGN=-20V */ > + > +/* Third, Fourth, Sixth Parameters (VSP_1, VSPL_0, VSPL_1) */ > +#define PIXPAPER_PWR_VSP_8_2V 0x22 /* VSP_1/VSPL_1: 8.2V (34 decimal) */ > +#define PIXPAPER_PWR_VSPL_15V 0x78 /* VSPL_0: 15V (120 decimal) */ > + > +/* Fifth Parameter (VSN_1) */ > +#define PIXPAPER_PWR_VSN_4V 0x0A /* VSN_1: -4V (10 decimal) */ > + > +/* R03H PFS - Power Off Sequence Setting Register */ > +/* First Parameter */ > +#define PIXPAPER_PFS_T_VDS_OFF_MASK \ > + (3 << 0) /* Bits 1-0: T_VDS_OFF, VSP/VSN power-off sequence */ > +#define PIXPAPER_PFS_T_VDS_OFF_20MS (0x0 << 0) /* 00: 20 ms (default) */ > +#define PIXPAPER_PFS_T_VDS_OFF_40MS (0x1 << 0) /* 01: 40 ms */ > +#define PIXPAPER_PFS_T_VDS_OFF_60MS (0x2 << 0) /* 10: 60 ms */ > +#define PIXPAPER_PFS_T_VDS_OFF_80MS (0x3 << 0) /* 11: 80 ms */ > +#define PIXPAPER_PFS_T_VDPG_OFF_MASK \ > + (3 << 4) /* Bits 5-4: T_VDPG_OFF, VGP/VGN power-off sequence */ > +#define PIXPAPER_PFS_T_VDPG_OFF_20MS (0x0 << 4) /* 00: 20 ms (default) */ > +#define PIXPAPER_PFS_T_VDPG_OFF_40MS (0x1 << 4) /* 01: 40 ms */ > +#define PIXPAPER_PFS_T_VDPG_OFF_60MS (0x2 << 4) /* 10: 60 ms */ > +#define PIXPAPER_PFS_T_VDPG_OFF_80MS (0x3 << 4) /* 11: 80 ms */ > +#define PIXPAPER_PFS_CONFIG1 \ > + (PIXPAPER_PFS_T_VDS_OFF_20MS | \ > + PIXPAPER_PFS_T_VDPG_OFF_20MS) /* 0x10: Default 20 ms for VSP/VSN and VGP/VGN */ > + > +/* Second Parameter */ > +#define PIXPAPER_PFS_VGP_EXT_MASK \ > + (0xF << 0) /* Bits 3-0: VGP_EXT, VGP extension time */ > +#define PIXPAPER_PFS_VGP_EXT_0MS (0x0 << 0) /* 0000: 0 ms */ > +#define PIXPAPER_PFS_VGP_EXT_500MS (0x1 << 0) /* 0001: 500 ms */ > +#define PIXPAPER_PFS_VGP_EXT_1000MS (0x2 << 0) /* 0010: 1000 ms */ > +#define PIXPAPER_PFS_VGP_EXT_1500MS (0x3 << 0) /* 0011: 1500 ms */ > +#define PIXPAPER_PFS_VGP_EXT_2000MS (0x4 << 0) /* 0100: 2000 ms (default) */ > +#define PIXPAPER_PFS_VGP_EXT_2500MS (0x5 << 0) /* 0101: 2500 ms */ > +#define PIXPAPER_PFS_VGP_EXT_3000MS (0x6 << 0) /* 0110: 3000 ms */ > +#define PIXPAPER_PFS_VGP_EXT_3500MS (0x7 << 0) /* 0111: 3500 ms */ > +#define PIXPAPER_PFS_VGP_EXT_4000MS (0x8 << 0) /* 1000: 4000 ms */ > +#define PIXPAPER_PFS_VGP_EXT_4500MS (0x9 << 0) /* 1001: 4500 ms */ > +#define PIXPAPER_PFS_VGP_EXT_5000MS (0xA << 0) /* 1010: 5000 ms */ > +#define PIXPAPER_PFS_VGP_EXT_5500MS (0xB << 0) /* 1011: 5500 ms */ > +#define PIXPAPER_PFS_VGP_EXT_6000MS (0xC << 0) /* 1100: 6000 ms */ > +#define PIXPAPER_PFS_VGP_EXT_6500MS (0xD << 0) /* 1101: 6500 ms */ > +#define PIXPAPER_PFS_VGP_LEN_MASK \ > + (0xF << 4) /* Bits 7-4: VGP_LEN, VGP at 10V during power-off */ > +#define PIXPAPER_PFS_VGP_LEN_0MS (0x0 << 4) /* 0000: 0 ms */ > +#define PIXPAPER_PFS_VGP_LEN_500MS (0x1 << 4) /* 0001: 500 ms */ > +#define PIXPAPER_PFS_VGP_LEN_1000MS (0x2 << 4) /* 0010: 1000 ms */ > +#define PIXPAPER_PFS_VGP_LEN_1500MS (0x3 << 4) /* 0011: 1500 ms */ > +#define PIXPAPER_PFS_VGP_LEN_2000MS (0x4 << 4) /* 0100: 2000 ms */ > +#define PIXPAPER_PFS_VGP_LEN_2500MS (0x5 << 4) /* 0101: 2500 ms (default) */ > +#define PIXPAPER_PFS_VGP_LEN_3000MS (0x6 << 4) /* 0110: 3000 ms */ > +#define PIXPAPER_PFS_VGP_LEN_3500MS (0x7 << 4) /* 0111: 3500 ms */ > +#define PIXPAPER_PFS_VGP_LEN_4000MS (0x8 << 4) /* 1000: 4000 ms */ > +#define PIXPAPER_PFS_VGP_LEN_4500MS (0x9 << 4) /* 1001: 4500 ms */ > +#define PIXPAPER_PFS_VGP_LEN_5000MS (0xA << 4) /* 1010: 5000 ms */ > +#define PIXPAPER_PFS_VGP_LEN_5500MS (0xB << 4) /* 1011: 5500 ms */ > +#define PIXPAPER_PFS_VGP_LEN_6000MS (0xC << 4) /* 1100: 6000 ms */ > +#define PIXPAPER_PFS_VGP_LEN_6500MS (0xD << 4) /* 1101: 6500 ms */ > +#define PIXPAPER_PFS_CONFIG2 \ > + (PIXPAPER_PFS_VGP_EXT_1000MS | \ > + PIXPAPER_PFS_VGP_LEN_2500MS) /* 0x54: VGP extension 1000 ms, VGP at 10V for 2500 ms */ > + > +/* Third Parameter */ > +#define PIXPAPER_PFS_XON_LEN_MASK \ > + (0xF << 0) /* Bits 3-0: XON_LEN, XON enable time */ > +#define PIXPAPER_PFS_XON_LEN_0MS (0x0 << 0) /* 0000: 0 ms */ > +#define PIXPAPER_PFS_XON_LEN_500MS (0x1 << 0) /* 0001: 500 ms */ > +#define PIXPAPER_PFS_XON_LEN_1000MS (0x2 << 0) /* 0010: 1000 ms */ > +#define PIXPAPER_PFS_XON_LEN_1500MS (0x3 << 0) /* 0011: 1500 ms */ > +#define PIXPAPER_PFS_XON_LEN_2000MS (0x4 << 0) /* 0100: 2000 ms (default) */ > +#define PIXPAPER_PFS_XON_LEN_2500MS (0x5 << 0) /* 0101: 2500 ms */ > +#define PIXPAPER_PFS_XON_LEN_3000MS (0x6 << 0) /* 0110: 3000 ms */ > +#define PIXPAPER_PFS_XON_LEN_3500MS (0x7 << 0) /* 0111: 3500 ms */ > +#define PIXPAPER_PFS_XON_LEN_4000MS (0x8 << 0) /* 1000: 4000 ms */ > +#define PIXPAPER_PFS_XON_LEN_4500MS (0x9 << 0) /* 1001: 4500 ms */ > +#define PIXPAPER_PFS_XON_LEN_5000MS (0xA << 0) /* 1010: 5000 ms */ > +#define PIXPAPER_PFS_XON_LEN_5500MS (0xB << 0) /* 1011: 5500 ms */ > +#define PIXPAPER_PFS_XON_LEN_6000MS (0xC << 0) /* 1100: 6000 ms */ > +#define PIXPAPER_PFS_XON_DLY_MASK \ > + (0xF << 4) /* Bits 7-4: XON_DLY, XON delay time */ > +#define PIXPAPER_PFS_XON_DLY_0MS (0x0 << 4) /* 0000: 0 ms */ > +#define PIXPAPER_PFS_XON_DLY_500MS (0x1 << 4) /* 0001: 500 ms */ > +#define PIXPAPER_PFS_XON_DLY_1000MS (0x2 << 4) /* 0010: 1000 ms */ > +#define PIXPAPER_PFS_XON_DLY_1500MS (0x3 << 4) /* 0011: 1500 ms */ > +#define PIXPAPER_PFS_XON_DLY_2000MS (0x4 << 4) /* 0100: 2000 ms (default) */ > +#define PIXPAPER_PFS_XON_DLY_2500MS (0x5 << 4) /* 0101: 2500 ms */ > +#define PIXPAPER_PFS_XON_DLY_3000MS (0x6 << 4) /* 0110: 3000 ms */ > +#define PIXPAPER_PFS_XON_DLY_3500MS (0x7 << 4) /* 0111: 3500 ms */ > +#define PIXPAPER_PFS_XON_DLY_4000MS (0x8 << 4) /* 1000: 4000 ms */ > +#define PIXPAPER_PFS_XON_DLY_4500MS (0x9 << 4) /* 1001: 4500 ms */ > +#define PIXPAPER_PFS_XON_DLY_5000MS (0xA << 4) /* 1010: 5000 ms */ > +#define PIXPAPER_PFS_XON_DLY_5500MS (0xB << 4) /* 1011: 5500 ms */ > +#define PIXPAPER_PFS_XON_DLY_6000MS (0xC << 4) /* 1100: 6000 ms */ > +#define PIXPAPER_PFS_CONFIG3 \ > + (PIXPAPER_PFS_XON_LEN_2000MS | \ > + PIXPAPER_PFS_XON_DLY_2000MS) /* 0x44: XON enable and delay at 2000 ms */ > + > +/* R06H BTST - Booster Soft Start Command */ > +/* First Parameter */ > +#define PIXPAPER_BTST_PHA_SFT_MASK \ > + (3 << 0) /* Bits 1-0: PHA_SFT, soft start period for phase A */ > +#define PIXPAPER_BTST_PHA_SFT_10MS (0x0 << 0) /* 00: 10 ms (default) */ > +#define PIXPAPER_BTST_PHA_SFT_20MS (0x1 << 0) /* 01: 20 ms */ > +#define PIXPAPER_BTST_PHA_SFT_30MS (0x2 << 0) /* 10: 30 ms */ > +#define PIXPAPER_BTST_PHA_SFT_40MS (0x3 << 0) /* 11: 40 ms */ > +#define PIXPAPER_BTST_PHB_SFT_MASK \ > + (3 << 2) /* Bits 3-2: PHB_SFT, soft start period for phase B */ > +#define PIXPAPER_BTST_PHB_SFT_10MS (0x0 << 2) /* 00: 10 ms (default) */ > +#define PIXPAPER_BTST_PHB_SFT_20MS (0x1 << 2) /* 01: 20 ms */ > +#define PIXPAPER_BTST_PHB_SFT_30MS (0x2 << 2) /* 10: 30 ms */ > +#define PIXPAPER_BTST_PHB_SFT_40MS (0x3 << 2) /* 11: 40 ms */ > +#define PIXPAPER_BTST_CONFIG1 \ > + (PIXPAPER_BTST_PHA_SFT_40MS | \ > + PIXPAPER_BTST_PHB_SFT_40MS) /* 0x0F: 40 ms for phase A and B */ > + > +/* Second to Seventh Parameters (Driving Strength or Minimum OFF Time) */ > +#define PIXPAPER_BTST_CONFIG2 0x0A /* Strength11 */ > +#define PIXPAPER_BTST_CONFIG3 0x2F /* Period48 */ > +#define PIXPAPER_BTST_CONFIG4 0x25 /* Strength38 */ > +#define PIXPAPER_BTST_CONFIG5 0x22 /* Period35 */ > +#define PIXPAPER_BTST_CONFIG6 0x2E /* Strength47 */ > +#define PIXPAPER_BTST_CONFIG7 0x21 /* Period34 */ > + > +/* R12H: DRF (Display Refresh) */ > +#define PIXPAPER_DRF_VCOM_AC 0x00 /* AC VCOM: VCOM follows LUTC (default) */ > +#define PIXPAPER_DRF_VCOM_DC 0x01 /* DC VCOM: VCOM fixed to VCOMDC */ > + > +/* R30H PLL - PLL Control Register */ > +/* First Parameter */ > +#define PIXPAPER_PLL_FR_MASK (0x7 << 0) /* Bits 2-0: FR, frame rate */ > +#define PIXPAPER_PLL_FR_12_5HZ (0x0 << 0) /* 000: 12.5 Hz */ > +#define PIXPAPER_PLL_FR_25HZ (0x1 << 0) /* 001: 25 Hz */ > +#define PIXPAPER_PLL_FR_50HZ (0x2 << 0) /* 010: 50 Hz (default) */ > +#define PIXPAPER_PLL_FR_65HZ (0x3 << 0) /* 011: 65 Hz */ > +#define PIXPAPER_PLL_FR_75HZ (0x4 << 0) /* 100: 75 Hz */ > +#define PIXPAPER_PLL_FR_85HZ (0x5 << 0) /* 101: 85 Hz */ > +#define PIXPAPER_PLL_FR_100HZ (0x6 << 0) /* 110: 100 Hz */ > +#define PIXPAPER_PLL_FR_120HZ (0x7 << 0) /* 111: 120 Hz */ > +#define PIXPAPER_PLL_DFR \ > + (1 << 3) /* Bit 3: Dynamic frame rate, 0=disabled (default), 1=enabled */ > +#define PIXPAPER_PLL_CONFIG \ > + (PIXPAPER_PLL_FR_50HZ) /* 0x02: 50 Hz, dynamic frame rate disabled */ > + > +/* R41H TSE - Temperature Sensor Calibration Register */ > +/* First Parameter */ > +#define PIXPAPER_TSE_TO_MASK \ > + (0xF << 0) /* Bits 3-0: TO[3:0], temperature offset */ > +#define PIXPAPER_TSE_TO_POS_0C (0x0 << 0) /* 0000: +0°C (default) */ > +#define PIXPAPER_TSE_TO_POS_0_5C (0x1 << 0) /* 0001: +0.5°C */ > +#define PIXPAPER_TSE_TO_POS_1C (0x2 << 0) /* 0010: +1°C */ > +#define PIXPAPER_TSE_TO_POS_1_5C (0x3 << 0) /* 0011: +1.5°C */ > +#define PIXPAPER_TSE_TO_POS_2C (0x4 << 0) /* 0100: +2°C */ > +#define PIXPAPER_TSE_TO_POS_2_5C (0x5 << 0) /* 0101: +2.5°C */ > +#define PIXPAPER_TSE_TO_POS_3C (0x6 << 0) /* 0110: +3°C */ > +#define PIXPAPER_TSE_TO_POS_3_5C (0x7 << 0) /* 0111: +3.5°C */ > +#define PIXPAPER_TSE_TO_NEG_4C (0x8 << 0) /* 1000: -4°C */ > +#define PIXPAPER_TSE_TO_NEG_3_5C (0x9 << 0) /* 1001: -3.5°C */ > +#define PIXPAPER_TSE_TO_NEG_3C (0xA << 0) /* 1010: -3°C */ > +#define PIXPAPER_TSE_TO_NEG_2_5C (0xB << 0) /* 1011: -2.5°C */ > +#define PIXPAPER_TSE_TO_NEG_2C (0xC << 0) /* 1100: -2°C */ > +#define PIXPAPER_TSE_TO_NEG_1_5C (0xD << 0) /* 1101: -1.5°C */ > +#define PIXPAPER_TSE_TO_NEG_1C (0xE << 0) /* 1110: -1°C */ > +#define PIXPAPER_TSE_TO_NEG_0_5C (0xF << 0) /* 1111: -0.5°C */ > +#define PIXPAPER_TSE_TO_FINE_MASK \ > + (0x3 << 4) /* Bits 5-4: TO[5:4], fine adjustment for positive offsets */ > +#define PIXPAPER_TSE_TO_FINE_0C (0x0 << 4) /* 00: +0.0°C (default) */ > +#define PIXPAPER_TSE_TO_FINE_0_25C (0x1 << 4) /* 01: +0.25°C */ > +#define PIXPAPER_TSE_ENABLE \ > + (0 << 7) /* Bit 7: TSE, 0=internal sensor enabled (default), 1=disabled (external) */ > +#define PIXPAPER_TSE_DISABLE \ > + (1 << 7) /* Bit 7: TSE, 1=internal sensor disabled, use external */ > +#define PIXPAPER_TSE_CONFIG \ > + (PIXPAPER_TSE_TO_POS_0C | PIXPAPER_TSE_TO_FINE_0C | \ > + PIXPAPER_TSE_ENABLE) /* 0x00: Internal sensor enabled, +0°C offset */ > + > +/* R4DH */ > +#define PIXPAPER_UNKNOWN_4D_CONFIG \ > + 0x78 /* This value is essential for initialization, derived from userspace examples. */ > + > +/* R50H CDI - VCOM and DATA Interval Setting Register */ > +/* First Parameter */ > +#define PIXPAPER_CDI_INTERVAL_MASK \ > + (0xF << 0) /* Bits 3-0: CDI[3:0], VCOM and data interval (hsync) */ > +#define PIXPAPER_CDI_17_HSYNC (0x0 << 0) /* 0000: 17 hsync */ > +#define PIXPAPER_CDI_16_HSYNC (0x1 << 0) /* 0001: 16 hsync */ > +#define PIXPAPER_CDI_15_HSYNC (0x2 << 0) /* 0010: 15 hsync */ > +#define PIXPAPER_CDI_14_HSYNC (0x3 << 0) /* 0011: 14 hsync */ > +#define PIXPAPER_CDI_13_HSYNC (0x4 << 0) /* 0100: 13 hsync */ > +#define PIXPAPER_CDI_12_HSYNC (0x5 << 0) /* 0101: 12 hsync */ > +#define PIXPAPER_CDI_11_HSYNC (0x6 << 0) /* 0110: 11 hsync */ > +#define PIXPAPER_CDI_10_HSYNC (0x7 << 0) /* 0111: 10 hsync (default) */ > +#define PIXPAPER_CDI_9_HSYNC (0x8 << 0) /* 1000: 9 hsync */ > +#define PIXPAPER_CDI_8_HSYNC (0x9 << 0) /* 1001: 8 hsync */ > +#define PIXPAPER_CDI_7_HSYNC (0xA << 0) /* 1010: 7 hsync */ > +#define PIXPAPER_CDI_6_HSYNC (0xB << 0) /* 1011: 6 hsync */ > +#define PIXPAPER_CDI_5_HSYNC (0xC << 0) /* 1100: 5 hsync */ > +#define PIXPAPER_CDI_4_HSYNC (0xD << 0) /* 1101: 4 hsync */ > +#define PIXPAPER_CDI_3_HSYNC (0xE << 0) /* 1110: 3 hsync */ > +#define PIXPAPER_CDI_2_HSYNC (0xF << 0) /* 1111: 2 hsync */ > +#define PIXPAPER_CDI_DDX \ > + (1 << 4) /* Bit 4: DDX, 0=grayscale mapping 0, 1=grayscale mapping 1 (default) */ > +#define PIXPAPER_CDI_VBD_MASK \ > + (0x7 << 5) /* Bits 7-5: VBD[2:0], border data selection */ > +#define PIXPAPER_CDI_VBD_FLOAT (0x0 << 5) /* 000: Floating (DDX=0 or 1) */ > +#define PIXPAPER_CDI_VBD_GRAY3_DDX0 \ > + (0x1 << 5) /* 001: Gray3 (border_buf=011) when DDX=0 */ > +#define PIXPAPER_CDI_VBD_GRAY2_DDX0 \ > + (0x2 << 5) /* 010: Gray2 (border_buf=010) when DDX=0 */ > +#define PIXPAPER_CDI_VBD_GRAY1_DDX0 \ > + (0x3 << 5) /* 011: Gray1 (border_buf=001) when DDX=0 */ > +#define PIXPAPER_CDI_VBD_GRAY0_DDX0 \ > + (0x4 << 5) /* 100: Gray0 (border_buf=000) when DDX=0 */ > +#define PIXPAPER_CDI_VBD_GRAY0_DDX1 \ > + (0x0 << 5) /* 000: Gray0 (border_buf=000) when DDX=1 */ > +#define PIXPAPER_CDI_VBD_GRAY1_DDX1 \ > + (0x1 << 5) /* 001: Gray1 (border_buf=001) when DDX=1 */ > +#define PIXPAPER_CDI_VBD_GRAY2_DDX1 \ > + (0x2 << 5) /* 010: Gray2 (border_buf=010) when DDX=1 */ > +#define PIXPAPER_CDI_VBD_GRAY3_DDX1 \ > + (0x3 << 5) /* 011: Gray3 (border_buf=011) when DDX=1 */ > +#define PIXPAPER_CDI_VBD_FLOAT_DDX1 (0x4 << 5) /* 100: Floating when DDX=1 */ > +#define PIXPAPER_CDI_CONFIG \ > + (PIXPAPER_CDI_10_HSYNC | PIXPAPER_CDI_DDX | \ > + PIXPAPER_CDI_VBD_GRAY1_DDX1) /* 0x37: 10 hsync, DDX=1, border Gray1 */ > + > +/* R60H */ > +#define PIXPAPER_UNKNOWN_60_CONFIG1 \ > + 0x02 /* This value is essential for initialization, derived from userspace examples. */ > +#define PIXPAPER_UNKNOWN_60_CONFIG2 \ > + 0x02 /* This value is essential for initialization, derived from userspace examples. */ > + > +/* R61H TRES - Resolution Setting Register */ > +#define PIXPAPER_TRES_HRES_H \ > + ((PIXPAPER_PANEL_BUFFER_WIDTH >> 8) & \ > + 0xFF) /* HRES[9:8]: High byte of horizontal resolution (128) */ > +#define PIXPAPER_TRES_HRES_L \ > + (PIXPAPER_PANEL_BUFFER_WIDTH & \ > + 0xFF) /* HRES[7:0]: Low byte of horizontal resolution (128 = 0x80) */ > +#define PIXPAPER_TRES_VRES_H \ > + ((PIXPAPER_HEIGHT >> 8) & \ > + 0xFF) /* VRES[9:8]: High byte of vertical resolution (250) */ > +#define PIXPAPER_TRES_VRES_L \ > + (PIXPAPER_HEIGHT & \ > + 0xFF) /* VRES[7:0]: Low byte of vertical resolution (250 = 0xFA) */ > + > +/* R65H GSST - Gate/Source Start Setting Register */ > +#define PIXPAPER_GSST_S_START 0x00 /* S_Start[7:0]: First source line (S0) */ > +#define PIXPAPER_GSST_RESERVED 0x00 /* Reserved byte */ > +#define PIXPAPER_GSST_G_START_H \ > + 0x00 /* G_Start[8]: High bit of first gate line (G0) */ > +#define PIXPAPER_GSST_G_START_L \ > + 0x00 /* G_Start[7:0]: Low byte of first gate line (G0) */ > + > +/* RB4H */ > +#define PIXPAPER_UNKNOWN_B4_CONFIG \ > + 0xD0 /* This value is essential for initialization, derived from userspace examples. */ > + > +/* RB5H */ > +#define PIXPAPER_UNKNOWN_B5_CONFIG \ > + 0x03 /* This value is essential for initialization, derived from userspace examples. */ > + > +/* RE0H */ > +#define PIXPAPER_UNKNOWN_E0_CONFIG \ > + 0x00 /* This value is essential for initialization, derived from userspace examples. */ > + > +/* RE3H PWS - Power Saving Register */ > +/* First Parameter */ > +#define PIXPAPER_PWS_VCOM_W_MASK \ > + (0xF \ > + << 4) /* Bits 7-4: VCOM_W[3:0], VCOM power-saving width (line periods) */ > +#define PIXPAPER_PWS_VCOM_W_0 (0x0 << 4) /* 0000: 0 line periods */ > +#define PIXPAPER_PWS_VCOM_W_1 (0x1 << 4) /* 0001: 1 line period */ > +#define PIXPAPER_PWS_VCOM_W_2 (0x2 << 4) /* 0010: 2 line periods */ > +#define PIXPAPER_PWS_VCOM_W_3 (0x3 << 4) /* 0011: 3 line periods */ > +#define PIXPAPER_PWS_VCOM_W_4 (0x4 << 4) /* 0100: 4 line periods */ > +#define PIXPAPER_PWS_VCOM_W_5 (0x5 << 4) /* 0101: 5 line periods */ > +#define PIXPAPER_PWS_VCOM_W_6 (0x6 << 4) /* 0110: 6 line periods */ > +#define PIXPAPER_PWS_VCOM_W_7 (0x7 << 4) /* 0111: 7 line periods */ > +#define PIXPAPER_PWS_VCOM_W_8 (0x8 << 4) /* 1000: 8 line periods */ > +#define PIXPAPER_PWS_VCOM_W_9 (0x9 << 4) /* 1001: 9 line periods */ > +#define PIXPAPER_PWS_VCOM_W_10 (0xA << 4) /* 1010: 10 line periods */ > +#define PIXPAPER_PWS_VCOM_W_11 (0xB << 4) /* 1011: 11 line periods */ > +#define PIXPAPER_PWS_VCOM_W_12 (0xC << 4) /* 1100: 12 line periods */ > +#define PIXPAPER_PWS_VCOM_W_13 (0xD << 4) /* 1101: 13 line periods */ > +#define PIXPAPER_PWS_VCOM_W_14 (0xE << 4) /* 1110: 14 line periods */ > +#define PIXPAPER_PWS_VCOM_W_15 (0xF << 4) /* 1111: 15 line periods */ > +#define PIXPAPER_PWS_SD_W_MASK \ > + (0xF << 0) /* Bits 3-0: SD_W[3:0], source power-saving width (660 ns units) */ > +#define PIXPAPER_PWS_SD_W_0 (0x0 << 0) /* 0000: 0 ns */ > +#define PIXPAPER_PWS_SD_W_1 (0x1 << 0) /* 0001: 660 ns */ > +#define PIXPAPER_PWS_SD_W_2 (0x2 << 0) /* 0010: 1320 ns */ > +#define PIXPAPER_PWS_SD_W_3 (0x3 << 0) /* 0011: 1980 ns */ > +#define PIXPAPER_PWS_SD_W_4 (0x4 << 0) /* 0100: 2640 ns */ > +#define PIXPAPER_PWS_SD_W_5 (0x5 << 0) /* 0101: 3300 ns */ > +#define PIXPAPER_PWS_SD_W_6 (0x6 << 0) /* 0110: 3960 ns */ > +#define PIXPAPER_PWS_SD_W_7 (0x7 << 0) /* 0111: 4620 ns */ > +#define PIXPAPER_PWS_SD_W_8 (0x8 << 0) /* 1000: 5280 ns */ > +#define PIXPAPER_PWS_SD_W_9 (0x9 << 0) /* 1001: 5940 ns */ > +#define PIXPAPER_PWS_SD_W_10 (0xA << 0) /* 1010: 6600 ns */ > +#define PIXPAPER_PWS_SD_W_11 (0xB << 0) /* 1011: 7260 ns */ > +#define PIXPAPER_PWS_SD_W_12 (0xC << 0) /* 1100: 7920 ns */ > +#define PIXPAPER_PWS_SD_W_13 (0xD << 0) /* 1101: 8580 ns */ > +#define PIXPAPER_PWS_SD_W_14 (0xE << 0) /* 1110: 9240 ns */ > +#define PIXPAPER_PWS_SD_W_15 (0xF << 0) /* 1111: 9900 ns */ > +#define PIXPAPER_PWS_CONFIG \ > + (PIXPAPER_PWS_VCOM_W_2 | \ > + PIXPAPER_PWS_SD_W_2) /* 0x22: VCOM 2 line periods (160 µs), source 1320 ns */ > + > +/* RE7H */ > +#define PIXPAPER_UNKNOWN_E7_CONFIG \ > + 0x1C /* This value is essential for initialization, derived from userspace examples. */ > + > +/* RE9H */ > +#define PIXPAPER_UNKNOWN_E9_CONFIG \ > + 0x01 /* This value is essential for initialization, derived from userspace examples. */ > + > +#endif /* __PIXPAPER_REGS_H__ */ > diff --git a/drivers/gpu/drm/tiny/pixpaper.c b/drivers/gpu/drm/tiny/pixpaper.c > new file mode 100644 > index 0000000000000000000000000000000000000000..75643ed337120b5713706e0cbd942785db2aba12 > --- /dev/null > +++ b/drivers/gpu/drm/tiny/pixpaper.c > @@ -0,0 +1,789 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * DRM driver for PIXPAPER e-ink panel > + * > + * Author: LiangCheng Wang <zaq14760(a)gmail.com>, > + */ > +#include <linux/delay.h> > +#include <linux/module.h> > +#include <linux/spi/spi.h> > + > +#include <drm/clients/drm_client_setup.h> > +#include <drm/drm_atomic.h> > +#include <drm/drm_atomic_helper.h> > +#include <drm/drm_drv.h> > +#include <drm/drm_fbdev_shmem.h> > +#include <drm/drm_framebuffer.h> > +#include <drm/drm_gem_atomic_helper.h> > +#include <drm/drm_gem_shmem_helper.h> > +#include <drm/drm_gem_framebuffer_helper.h> > +#include <drm/drm_probe_helper.h> > + > +#include "pixpaper-regs.h" > + > +MODULE_IMPORT_NS("DMA_BUF"); > + > +/* > + * The panel has a visible resolution of 122x250. > + * However, the controller requires the horizontal resolution to be aligned to 128 pixels. > + * No porch or sync timing values are provided in the datasheet, so we define minimal > + * placeholder values to satisfy the DRM framework. > + */ > + > +/* Panel visible resolution */ > +#define PIXPAPER_WIDTH 122 > +#define PIXPAPER_HEIGHT 250 > + > +/* Controller requires 128 horizontal pixels total (for memory alignment) */ > +#define PIXPAPER_HTOTAL 128 > +#define PIXPAPER_HFP 2 > +#define PIXPAPER_HSYNC 2 > +#define PIXPAPER_HBP (PIXPAPER_HTOTAL - PIXPAPER_WIDTH - PIXPAPER_HFP - PIXPAPER_HSYNC) > + > +/* > + * According to the datasheet, the total vertical blanking must be 55 lines, > + * regardless of how the vertical back porch is set. > + * Here we allocate VFP=2, VSYNC=2, and VBP=51 to sum up to 55 lines. > + * Total vertical lines = 250 (visible) + 55 (blanking) = 305. > + */ > +#define PIXPAPER_VTOTAL (250 + 55) > +#define PIXPAPER_VFP 2 > +#define PIXPAPER_VSYNC 2 > +#define PIXPAPER_VBP (55 - PIXPAPER_VFP - PIXPAPER_VSYNC) > + > +/* > + * Pixel clock calculation: > + * pixel_clock = htotal * vtotal * refresh_rate > + * = 128 * 305 * 50 > + * = 1,952,000 Hz = 1952 kHz > + */ > +#define PIXPAPER_PIXEL_CLOCK 1952 > + > +#define PIXPAPER_WIDTH_MM 24 /* approximate from 23.7046mm */ > +#define PIXPAPER_HEIGHT_MM 49 /* approximate from 48.55mm */ > + > +#define PIXPAPER_SPI_BITS_PER_WORD 8 > +#define PIXPAPER_SPI_SPEED_DEFAULT 1000000 > + > +#define PIXPAPER_PANEL_BUFFER_WIDTH 128 > +#define PIXPAPER_PANEL_BUFFER_TWO_BYTES_PER_ROW (PIXPAPER_PANEL_BUFFER_WIDTH / 4) > + > +#define PIXPAPER_COLOR_THRESHOLD_LOW_CHANNEL 60 > +#define PIXPAPER_COLOR_THRESHOLD_HIGH_CHANNEL 200 > +#define PIXPAPER_COLOR_THRESHOLD_YELLOW_MIN_GREEN 180 > + > +struct pixpaper_error_ctx { > + int errno_code; > +}; > + > +struct pixpaper_panel { > + struct drm_device drm; > + struct drm_plane plane; > + struct drm_crtc crtc; > + struct drm_encoder encoder; > + struct drm_connector connector; > + > + struct spi_device *spi; > + struct gpio_desc *reset; > + struct gpio_desc *busy; > + struct gpio_desc *dc; > +}; > + > +static inline struct pixpaper_panel *to_pixpaper_panel(struct drm_device *drm) > +{ > + return container_of(drm, struct pixpaper_panel, drm); > +} > + > +static void pixpaper_wait_busy(struct pixpaper_panel *panel) I'd rather call this helper 'pixpaper_wait_for_panel()' or 'pixpaper_wait_for_hw()'. Makes it clear what you're waiting for. And since the code does sleep, it's not really busy waiting anyway. > +{ > + unsigned int timeout_ms = 10000; > + unsigned long timeout_jiffies = jiffies + msecs_to_jiffies(timeout_ms); > + > + usleep_range(1000, 1500); > + while (gpiod_get_value_cansleep(panel->busy) != 1) { > + if (time_after(jiffies, timeout_jiffies)) { > + drm_warn(&panel->drm, "Busy wait timed out\n"); > + return; > + } > + usleep_range(100, 200); > + } > +} > + > +static void pixpaper_spi_sync(struct spi_device *spi, struct spi_message *msg, > + struct pixpaper_error_ctx *err) > +{ > + if (err->errno_code) > + return; > + > + int ret = spi_sync(spi, msg); > + > + if (ret < 0) > + err->errno_code = ret; > +} > + > +static void pixpaper_send_cmd(struct pixpaper_panel *panel, u8 cmd, > + struct pixpaper_error_ctx *err) > +{ > + if (err->errno_code) > + return; > + > + struct spi_transfer xfer = { > + .tx_buf = &cmd, > + .len = 1, > + }; > + struct spi_message msg; > + > + spi_message_init(&msg); > + spi_message_add_tail(&xfer, &msg); > + > + gpiod_set_value_cansleep(panel->dc, 0); > + usleep_range(1, 5); > + pixpaper_spi_sync(panel->spi, &msg, err); > +} > + > +static void pixpaper_send_data(struct pixpaper_panel *panel, u8 data, > + struct pixpaper_error_ctx *err) > +{ > + if (err->errno_code) > + return; > + > + struct spi_transfer xfer = { > + .tx_buf = &data, > + .len = 1, > + }; > + struct spi_message msg; > + > + spi_message_init(&msg); > + spi_message_add_tail(&xfer, &msg); > + > + gpiod_set_value_cansleep(panel->dc, 1); > + usleep_range(1, 5); > + pixpaper_spi_sync(panel->spi, &msg, err); > +} > + > +static int pixpaper_panel_hw_init(struct pixpaper_panel *panel) > +{ > + struct pixpaper_error_ctx err = { .errno_code = 0 }; > + > + gpiod_set_value_cansleep(panel->reset, 0); > + msleep(50); > + gpiod_set_value_cansleep(panel->reset, 1); > + msleep(50); > + > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_UNKNOWN_4D, &err); > + pixpaper_send_data(panel, PIXPAPER_UNKNOWN_4D_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_PANEL_SETTING, &err); > + pixpaper_send_data(panel, PIXPAPER_PSR_CONFIG, &err); > + pixpaper_send_data(panel, PIXPAPER_PSR_CONFIG2, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_POWER_SETTING, &err); > + pixpaper_send_data(panel, PIXPAPER_PWR_CONFIG1, &err); > + pixpaper_send_data(panel, PIXPAPER_PWR_CONFIG2, &err); > + pixpaper_send_data(panel, PIXPAPER_PWR_VSP_8_2V, &err); > + pixpaper_send_data(panel, PIXPAPER_PWR_VSPL_15V, &err); > + pixpaper_send_data(panel, PIXPAPER_PWR_VSN_4V, &err); > + pixpaper_send_data(panel, PIXPAPER_PWR_VSP_8_2V, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_POWER_OFF_SEQUENCE, &err); > + pixpaper_send_data(panel, PIXPAPER_PFS_CONFIG1, &err); > + pixpaper_send_data(panel, PIXPAPER_PFS_CONFIG2, &err); > + pixpaper_send_data(panel, PIXPAPER_PFS_CONFIG3, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_BOOSTER_SOFT_START, &err); > + pixpaper_send_data(panel, PIXPAPER_BTST_CONFIG1, &err); > + pixpaper_send_data(panel, PIXPAPER_BTST_CONFIG2, &err); > + pixpaper_send_data(panel, PIXPAPER_BTST_CONFIG3, &err); > + pixpaper_send_data(panel, PIXPAPER_BTST_CONFIG4, &err); > + pixpaper_send_data(panel, PIXPAPER_BTST_CONFIG5, &err); > + pixpaper_send_data(panel, PIXPAPER_BTST_CONFIG6, &err); > + pixpaper_send_data(panel, PIXPAPER_BTST_CONFIG7, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_PLL_CONTROL, &err); > + pixpaper_send_data(panel, PIXPAPER_PLL_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_TEMP_SENSOR_CALIB, &err); > + pixpaper_send_data(panel, PIXPAPER_TSE_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_VCOM_INTERVAL, &err); > + pixpaper_send_data(panel, PIXPAPER_CDI_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_UNKNOWN_60, &err); > + pixpaper_send_data(panel, PIXPAPER_UNKNOWN_60_CONFIG1, &err); > + pixpaper_send_data(panel, PIXPAPER_UNKNOWN_60_CONFIG2, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_RESOLUTION_SETTING, &err); > + pixpaper_send_data(panel, PIXPAPER_TRES_HRES_H, &err); > + pixpaper_send_data(panel, PIXPAPER_TRES_HRES_L, &err); > + pixpaper_send_data(panel, PIXPAPER_TRES_VRES_H, &err); > + pixpaper_send_data(panel, PIXPAPER_TRES_VRES_L, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_GATE_SOURCE_START, &err); > + pixpaper_send_data(panel, PIXPAPER_GSST_S_START, &err); > + pixpaper_send_data(panel, PIXPAPER_GSST_RESERVED, &err); > + pixpaper_send_data(panel, PIXPAPER_GSST_G_START_H, &err); > + pixpaper_send_data(panel, PIXPAPER_GSST_G_START_L, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_UNKNOWN_E7, &err); > + pixpaper_send_data(panel, PIXPAPER_UNKNOWN_E7_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_POWER_SAVING, &err); > + pixpaper_send_data(panel, PIXPAPER_PWS_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_UNKNOWN_E0, &err); > + pixpaper_send_data(panel, PIXPAPER_UNKNOWN_E0_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_UNKNOWN_B4, &err); > + pixpaper_send_data(panel, PIXPAPER_UNKNOWN_B4_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_UNKNOWN_B5, &err); > + pixpaper_send_data(panel, PIXPAPER_UNKNOWN_B5_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_UNKNOWN_E9, &err); > + pixpaper_send_data(panel, PIXPAPER_UNKNOWN_E9_CONFIG, &err); > + if (err.errno_code) > + goto init_fail; > + pixpaper_wait_busy(panel); > + > + return 0; > + > +init_fail: > + drm_err(&panel->drm, "Hardware initialization failed (err=%d)\n", > + err.errno_code); > + return err.errno_code; > +} > + > +/* > + * Convert framebuffer pixels to 2-bit e-paper format: > + * 00 - White > + * 01 - Black > + * 10 - Yellow > + * 11 - Red > + */ > +static u8 pack_pixels_to_byte(u32 *src_pixels, int i, int j, > + struct drm_framebuffer *fb) > +{ > + u8 packed_byte = 0; > + int k; > + > + for (k = 0; k < 4; k++) { > + int current_pixel_x = j * 4 + k; > + u8 two_bit_val; > + > + if (current_pixel_x < PIXPAPER_WIDTH) { > + u32 pixel_offset = > + (i * (fb->pitches[0] / 4)) + current_pixel_x; > + u32 pixel = src_pixels[pixel_offset]; Pixel data in DRM is always given in little endian. If you bit-shift the rgb components on a big-endian system, you'd get incorrect results. The fix is easy: declare src_pixels as '__le32 *src_pixels' and read each pixel with le32_to_cpu(). > + u32 r = (pixel >> 16) & 0xFF; > + u32 g = (pixel >> 8) & 0xFF; > + u32 b = pixel & 0xFF; > + > + if (r < PIXPAPER_COLOR_THRESHOLD_LOW_CHANNEL && > + g < PIXPAPER_COLOR_THRESHOLD_LOW_CHANNEL && > + b < PIXPAPER_COLOR_THRESHOLD_LOW_CHANNEL) { > + two_bit_val = 0b00; > + } else if (r > PIXPAPER_COLOR_THRESHOLD_HIGH_CHANNEL && > + g > PIXPAPER_COLOR_THRESHOLD_HIGH_CHANNEL && > + b > PIXPAPER_COLOR_THRESHOLD_HIGH_CHANNEL) { > + two_bit_val = 0b01; > + } else if (r > PIXPAPER_COLOR_THRESHOLD_HIGH_CHANNEL && > + g < PIXPAPER_COLOR_THRESHOLD_LOW_CHANNEL && > + b < PIXPAPER_COLOR_THRESHOLD_LOW_CHANNEL) { > + two_bit_val = 0b11; > + } else if (r > PIXPAPER_COLOR_THRESHOLD_HIGH_CHANNEL && > + g > PIXPAPER_COLOR_THRESHOLD_YELLOW_MIN_GREEN && > + b < PIXPAPER_COLOR_THRESHOLD_LOW_CHANNEL) { > + two_bit_val = 0b10; > + } else { > + two_bit_val = 0b01; > + } > + } else { > + two_bit_val = 0b01; > + } > + > + packed_byte |= two_bit_val << ((3 - k) * 2); > + } > + > + return packed_byte; > +} > + > +static int pixpaper_plane_helper_atomic_check(struct drm_plane *plane, > + struct drm_atomic_state *state) > +{ > + struct drm_plane_state *new_plane_state = > + drm_atomic_get_new_plane_state(state, plane); > + struct drm_crtc *new_crtc = new_plane_state->crtc; > + struct drm_crtc_state *new_crtc_state = NULL; > + int ret; > + > + if (new_crtc) > + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_crtc); > + > + ret = drm_atomic_helper_check_plane_state(new_plane_state, > + new_crtc_state, DRM_PLANE_NO_SCALING, > + DRM_PLANE_NO_SCALING, false, false); > + if (ret) > + return ret; > + else if (!new_plane_state->visible) > + return 0; > + > + return 0; > +} > + > +static int pixpaper_crtc_helper_atomic_check(struct drm_crtc *crtc, > + struct drm_atomic_state *state) > +{ > + struct drm_crtc_state *crtc_state = > + drm_atomic_get_new_crtc_state(state, crtc); > + > + if (!crtc_state->enable) > + return 0; > + > + return drm_atomic_helper_check_crtc_primary_plane(crtc_state); > +} > + > +static void pixpaper_crtc_atomic_enable(struct drm_crtc *crtc, > + struct drm_atomic_state *state) > +{ > + struct pixpaper_panel *panel = to_pixpaper_panel(crtc->dev); > + struct drm_device *drm = &panel->drm; > + int idx; > + struct pixpaper_error_ctx err = { .errno_code = 0 }; > + > + if (!drm_dev_enter(drm, &idx)) > + return; > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_POWER_ON, &err); > + if (err.errno_code) { > + drm_err(drm, "Failed to send PON command: %d\n", > + err.errno_code); Code in atomic_enable/_disable/_update can be triggered from user space and possible runs several times per second. Rather use drm_err_once() to avoid spamming the kernel log. Users still get the message from the first error that happens. > + goto exit_drm_dev; > + } > + > + pixpaper_wait_busy(panel); > + > + drm_dbg(drm, "Panel enabled and powered on\n"); > + > +exit_drm_dev: > + drm_dev_exit(idx); > +} > + > +static void pixpaper_crtc_atomic_disable(struct drm_crtc *crtc, > + struct drm_atomic_state *state) > +{ > + struct pixpaper_panel *panel = to_pixpaper_panel(crtc->dev); > + struct drm_device *drm = &panel->drm; > + struct pixpaper_error_ctx err = { .errno_code = 0 }; > + int idx; > + > + if (!drm_dev_enter(drm, &idx)) > + return; > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_POWER_OFF, &err); > + if (err.errno_code) { > + drm_err(drm, "Failed to send POF command: %d\n", > + err.errno_code); > + goto exit_drm_dev; > + } > + pixpaper_wait_busy(panel); > + > + drm_dbg(drm, "Panel disabled\n"); > + > +exit_drm_dev: > + drm_dev_exit(idx); > +} > + > +static void pixpaper_plane_atomic_update(struct drm_plane *plane, > + struct drm_atomic_state *state) > +{ > + struct drm_plane_state *plane_state = > + drm_atomic_get_new_plane_state(state, plane); > + struct drm_shadow_plane_state *shadow_plane_state = > + to_drm_shadow_plane_state(plane_state); > + struct drm_crtc *crtc = plane_state->crtc; > + struct pixpaper_panel *panel = to_pixpaper_panel(crtc->dev); > + > + struct drm_device *drm = &panel->drm; > + struct drm_framebuffer *fb = plane_state->fb; > + struct iosys_map map = shadow_plane_state->data[0]; > + void *vaddr = map.vaddr; > + int i, j, idx; > + u32 *src_pixels = NULL; > + struct pixpaper_error_ctx err = { .errno_code = 0 }; > + > + if (!drm_dev_enter(drm, &idx)) > + return; > + > + drm_dbg(drm, "Starting frame update (phys=%dx%d, buf_w=%d)\n", > + PIXPAPER_WIDTH, PIXPAPER_HEIGHT, PIXPAPER_PANEL_BUFFER_WIDTH); > + > + if (!fb || !plane_state->visible) { > + drm_err(drm, > + "No framebuffer or plane not visible, skipping update\n"); > + goto update_cleanup; > + } > + > + src_pixels = (u32 *)vaddr; > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_DATA_START_TRANSMISSION, &err); > + if (err.errno_code) > + goto update_cleanup; > + > + pixpaper_wait_busy(panel); > + > + for (i = 0; i < PIXPAPER_HEIGHT; i++) { > + for (j = 0; j < PIXPAPER_PANEL_BUFFER_TWO_BYTES_PER_ROW; j++) { > + u8 packed_byte = > + pack_pixels_to_byte(src_pixels, i, j, fb); > + > + pixpaper_wait_busy(panel); > + pixpaper_send_data(panel, packed_byte, &err); > + } > + } > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_POWER_ON, &err); > + if (err.errno_code) { > + drm_err(drm, "Failed to send PON command: %d\n", > + err.errno_code); > + goto update_cleanup; > + } > + pixpaper_wait_busy(panel); > + > + pixpaper_send_cmd(panel, PIXPAPER_CMD_DISPLAY_REFRESH, &err); > + pixpaper_send_data(panel, PIXPAPER_DRF_VCOM_AC, &err); > + if (err.errno_code) { > + drm_err(drm, "Failed sending data after DRF: %d\n", > + err.errno_code); > + goto update_cleanup; > + } > + pixpaper_wait_busy(panel); > + > +update_cleanup: > + if (err.errno_code && err.errno_code != -ETIMEDOUT) > + drm_err(drm, "Frame update function failed with error %d\n", > + err.errno_code); > + > + drm_dev_exit(idx); > +} > + > +static int pixpaper_connector_get_modes(struct drm_connector *connector) > +{ > + struct drm_display_mode *mode; > + > + drm_dbg(connector->dev, "CALLED for connector %s (id: %d)\n", > + connector->name, connector->base.id); > + > + mode = drm_mode_create(connector->dev); > + if (!mode) { > + drm_err(connector->dev, > + "Failed to create mode for connector %s\n", > + connector->name); Get_modes can be triggered from user space. So this error message has the potential for spamming the log. Rather use drm_err_once(). > + return 0; > + } > + > + mode->hdisplay = PIXPAPER_WIDTH; > + mode->hsync_start = PIXPAPER_WIDTH + PIXPAPER_HFP; > + mode->hsync_end = mode->hsync_start + PIXPAPER_HSYNC; > + mode->htotal = PIXPAPER_HTOTAL; > + > + mode->vdisplay = PIXPAPER_HEIGHT; > + mode->vsync_start = PIXPAPER_HEIGHT + PIXPAPER_VFP; > + mode->vsync_end = mode->vsync_start + PIXPAPER_VSYNC; > + mode->vtotal = PIXPAPER_VTOTAL; > + > + mode->clock = PIXPAPER_PIXEL_CLOCK; > + > + mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; > + drm_mode_set_name(mode); Is there a reason why you write this by yourself? I think this whole function can be condensed to a predefined mode and drm_connector_helper_get_modes_fixed(). See [1] for an example [1] https://elixir.bootlin.com/linux/v6.16.3/source/drivers/gpu/drm/panel/panel… > + > + if (drm_mode_validate_size(mode, connector->dev->mode_config.max_width, > + connector->dev->mode_config.max_height) != No need for this test. The DRM framework will do this for you. See [2] [2] https://elixir.bootlin.com/linux/v6.16.3/source/drivers/gpu/drm/drm_probe_h… > + MODE_OK) { > + drm_warn(connector->dev, > + "Mode %s (%dx%d) failed size validation against max %dx%d\n", > + mode->name, mode->hdisplay, mode->vdisplay, > + connector->dev->mode_config.max_width, > + connector->dev->mode_config.max_height); Mode validation should be silent. > + drm_mode_destroy(connector->dev, mode); > + return 0; > + } > + > + drm_mode_probed_add(connector, mode); > + drm_dbg(connector->dev, "Added mode '%s' (%dx%d@%d) to connector %s\n", > + mode->name, mode->hdisplay, mode->vdisplay, > + drm_mode_vrefresh(mode), connector->name); > + > + connector->display_info.width_mm = PIXPAPER_WIDTH_MM; > + connector->display_info.height_mm = PIXPAPER_HEIGHT_MM; > + > + return 1; > +} > + > +static const struct drm_plane_funcs pixpaper_plane_funcs = { > + .update_plane = drm_atomic_helper_update_plane, > + .disable_plane = drm_atomic_helper_disable_plane, > + .destroy = drm_plane_cleanup, > + DRM_GEM_SHADOW_PLANE_FUNCS, > +}; > + > +static const struct drm_plane_helper_funcs pixpaper_plane_helper_funcs = { > + DRM_GEM_SHADOW_PLANE_HELPER_FUNCS, > + .atomic_check = pixpaper_plane_helper_atomic_check, > + .atomic_update = pixpaper_plane_atomic_update, > +}; > + > +static const struct drm_crtc_funcs pixpaper_crtc_funcs = { > + .set_config = drm_atomic_helper_set_config, > + .page_flip = drm_atomic_helper_page_flip, > + .reset = drm_atomic_helper_crtc_reset, > + .destroy = drm_crtc_cleanup, > + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, > +}; > + > +static const struct drm_crtc_helper_funcs pixpaper_crtc_helper_funcs = { > + .atomic_check = pixpaper_crtc_helper_atomic_check, > + .atomic_enable = pixpaper_crtc_atomic_enable, > + .atomic_disable = pixpaper_crtc_atomic_disable, > +}; > + > +static const struct drm_encoder_funcs pixpaper_encoder_funcs = { > + .destroy = drm_encoder_cleanup, > +}; > + > +static const struct drm_connector_funcs pixpaper_connector_funcs = { > + .reset = drm_atomic_helper_connector_reset, > + .fill_modes = drm_helper_probe_single_connector_modes, > + .destroy = drm_connector_cleanup, > + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, > + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, > +}; > + > +static const struct drm_connector_helper_funcs pixpaper_connector_helper_funcs = { > + .get_modes = pixpaper_connector_get_modes, > +}; > + > +DEFINE_DRM_GEM_FOPS(pixpaper_fops); > + > +static struct drm_driver pixpaper_drm_driver = { > + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, > + .fops = &pixpaper_fops, > + .name = "pixpaper", > + .desc = "DRM driver for PIXPAPER e-ink", > + .major = 1, > + .minor = 0, > + DRM_GEM_SHMEM_DRIVER_OPS, > + DRM_FBDEV_SHMEM_DRIVER_OPS, > +}; > + > +static int pixpaper_mode_valid(struct drm_device *dev, > + const struct drm_display_mode *mode) This validates the resolution. So it should be a CRTC callback [3] instead of a mode_config callback. [3] https://elixir.bootlin.com/linux/v6.16.3/source/include/drm/drm_modeset_hel… Best regards Thomas > +{ > + if (mode->hdisplay == PIXPAPER_WIDTH && > + mode->vdisplay == PIXPAPER_HEIGHT) { > + return MODE_OK; > + } > + return MODE_BAD; > +} > + > +static const struct drm_mode_config_funcs pixpaper_mode_config_funcs = { > + .fb_create = drm_gem_fb_create_with_dirty, > + .mode_valid = pixpaper_mode_valid, > + .atomic_check = drm_atomic_helper_check, > + .atomic_commit = drm_atomic_helper_commit, > +}; > + > +static int pixpaper_probe(struct spi_device *spi) > +{ > + struct device *dev = &spi->dev; > + struct pixpaper_panel *panel; > + struct drm_device *drm; > + int ret; > + > + panel = devm_drm_dev_alloc(dev, &pixpaper_drm_driver, > + struct pixpaper_panel, drm); > + if (IS_ERR(panel)) > + return PTR_ERR(panel); > + > + drm = &panel->drm; > + panel->spi = spi; > + spi_set_drvdata(spi, panel); > + > + spi->mode = SPI_MODE_0; > + spi->bits_per_word = PIXPAPER_SPI_BITS_PER_WORD; > + > + if (!spi->max_speed_hz) { > + drm_warn(drm, > + "spi-max-frequency not specified in DT, using default %u Hz\n", > + PIXPAPER_SPI_SPEED_DEFAULT); > + spi->max_speed_hz = PIXPAPER_SPI_SPEED_DEFAULT; > + } > + > + ret = spi_setup(spi); > + if (ret < 0) { > + drm_err(drm, "SPI setup failed: %d\n", ret); > + return ret; > + } > + > + if (!dev->dma_mask) > + dev->dma_mask = &dev->coherent_dma_mask; > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); > + if (ret) { > + drm_err(drm, "Failed to set DMA mask: %d\n", ret); > + return ret; > + } > + > + panel->reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); > + if (IS_ERR(panel->reset)) > + return PTR_ERR(panel->reset); > + > + panel->busy = devm_gpiod_get(dev, "busy", GPIOD_IN); > + if (IS_ERR(panel->busy)) > + return PTR_ERR(panel->busy); > + > + panel->dc = devm_gpiod_get(dev, "dc", GPIOD_OUT_HIGH); > + if (IS_ERR(panel->dc)) > + return PTR_ERR(panel->dc); > + > + ret = pixpaper_panel_hw_init(panel); > + if (ret) { > + drm_err(drm, "Panel hardware initialization failed: %d\n", ret); > + return ret; > + } > + > + ret = drmm_mode_config_init(drm); > + if (ret) > + return ret; > + drm->mode_config.funcs = &pixpaper_mode_config_funcs; > + drm->mode_config.min_width = PIXPAPER_WIDTH; > + drm->mode_config.max_width = PIXPAPER_WIDTH; > + drm->mode_config.min_height = PIXPAPER_HEIGHT; > + drm->mode_config.max_height = PIXPAPER_HEIGHT; > + > + ret = drm_universal_plane_init(drm, &panel->plane, 1, > + &pixpaper_plane_funcs, > + (const uint32_t[]){ DRM_FORMAT_XRGB8888 }, > + 1, NULL, DRM_PLANE_TYPE_PRIMARY, NULL); > + if (ret) > + return ret; > + drm_plane_helper_add(&panel->plane, &pixpaper_plane_helper_funcs); > + > + ret = drm_crtc_init_with_planes(drm, &panel->crtc, &panel->plane, NULL, > + &pixpaper_crtc_funcs, NULL); > + if (ret) > + return ret; > + drm_crtc_helper_add(&panel->crtc, &pixpaper_crtc_helper_funcs); > + > + ret = drm_encoder_init(drm, &panel->encoder, &pixpaper_encoder_funcs, > + DRM_MODE_ENCODER_NONE, NULL); > + if (ret) > + return ret; > + panel->encoder.possible_crtcs = drm_crtc_mask(&panel->crtc); > + > + ret = drm_connector_init(drm, &panel->connector, > + &pixpaper_connector_funcs, > + DRM_MODE_CONNECTOR_SPI); > + if (ret) > + return ret; > + > + drm_connector_helper_add(&panel->connector, > + &pixpaper_connector_helper_funcs); > + drm_connector_attach_encoder(&panel->connector, &panel->encoder); > + > + drm_mode_config_reset(drm); > + > + ret = drm_dev_register(drm, 0); > + if (ret) > + return ret; > + > + drm_client_setup(drm, NULL); > + > + return 0; > +} > + > +static void pixpaper_remove(struct spi_device *spi) > +{ > + struct pixpaper_panel *panel = spi_get_drvdata(spi); > + > + if (!panel) > + return; > + > + drm_dev_unplug(&panel->drm); > + drm_atomic_helper_shutdown(&panel->drm); > +} > + > +static const struct spi_device_id pixpaper_ids[] = { { "pixpaper", 0 }, {} }; > +MODULE_DEVICE_TABLE(spi, pixpaper_ids); > + > +static const struct of_device_id pixpaper_dt_ids[] = { > + { .compatible = "mayqueen,pixpaper" }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, pixpaper_dt_ids); > + > +static struct spi_driver pixpaper_spi_driver = { > + .driver = { > + .name = "pixpaper", > + .of_match_table = pixpaper_dt_ids, > + }, > + .id_table = pixpaper_ids, > + .probe = pixpaper_probe, > + .remove = pixpaper_remove, > +}; > + > +module_spi_driver(pixpaper_spi_driver); > + > +MODULE_AUTHOR("LiangCheng Wang"); > +MODULE_DESCRIPTION("DRM SPI driver for PIXPAPER e-ink panel"); > +MODULE_LICENSE("GPL"); > -- -- Thomas Zimmermann Graphics Driver Developer SUSE Software Solutions Germany GmbH Frankenstrasse 146, 90461 Nuernberg, Germany GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman HRB 36809 (AG Nuernberg)

3 months, 3 weeks

1
0
0 0

Re: [PATCH v8 03/11] tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF

by kernel test robot

Hi Amirreza, kernel test robot noticed the following build warnings: [auto build test WARNING on 5303936d609e09665deda94eaedf26a0e5c3a087] url: https://github.com/intel-lab-lkp/linux/commits/Amirreza-Zarrabi/tee-allow-a… base: 5303936d609e09665deda94eaedf26a0e5c3a087 patch link: https://lore.kernel.org/r/20250820-qcom-tee-using-tee-ss-without-mem-obj-v8… patch subject: [PATCH v8 03/11] tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF config: arm-randconfig-r133-20250821 (https://download.01.org/0day-ci/archive/20250822/202508220436.qjXO4p8r-lkp@…) compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 93d24b6b7b148c47a2fa228a4ef31524fa1d9f3f) reproduce: (https://download.01.org/0day-ci/archive/20250822/202508220436.qjXO4p8r-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202508220436.qjXO4p8r-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/tee/tee_core.c:640:33: sparse: sparse: cast removes address space '__user' of expression vim +/__user +640 drivers/tee/tee_core.c 618 619 static int params_to_supp(struct tee_context *ctx, 620 struct tee_ioctl_param __user *uparams, 621 size_t num_params, struct tee_param *params) 622 { 623 size_t n; 624 625 for (n = 0; n < num_params; n++) { 626 struct tee_ioctl_param ip; 627 struct tee_param *p = params + n; 628 629 ip.attr = p->attr; 630 switch (p->attr & TEE_IOCTL_PARAM_ATTR_TYPE_MASK) { 631 case TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT: 632 case TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INOUT: 633 ip.a = p->u.value.a; 634 ip.b = p->u.value.b; 635 ip.c = p->u.value.c; 636 break; 637 case TEE_IOCTL_PARAM_ATTR_TYPE_UBUF_INPUT: 638 case TEE_IOCTL_PARAM_ATTR_TYPE_UBUF_OUTPUT: 639 case TEE_IOCTL_PARAM_ATTR_TYPE_UBUF_INOUT: > 640 ip.a = (u64)p->u.ubuf.uaddr; 641 ip.b = p->u.ubuf.size; 642 ip.c = 0; 643 break; 644 case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT: 645 case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_OUTPUT: 646 case TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT: 647 ip.b = p->u.memref.size; 648 if (!p->u.memref.shm) { 649 ip.a = 0; 650 ip.c = (u64)-1; /* invalid shm id */ 651 break; 652 } 653 ip.a = p->u.memref.shm_offs; 654 ip.c = p->u.memref.shm->id; 655 break; 656 default: 657 ip.a = 0; 658 ip.b = 0; 659 ip.c = 0; 660 break; 661 } 662 663 if (copy_to_user(uparams + n, &ip, sizeof(ip))) 664 return -EFAULT; 665 } 666 667 return 0; 668 } 669 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

3 months, 3 weeks

1
0
0 0

[PATCH v3] drm/amdgpu: Pin buffers while vmap'ing exported dma-buf objects

by Thomas Zimmermann

Current dma-buf vmap semantics require that the mapped buffer remains in place until the corresponding vunmap has completed. For GEM-SHMEM, this used to be guaranteed by a pin operation while creating an S/G table in import. GEM-SHMEN can now import dma-buf objects without creating the S/G table, so the pin is missing. Leads to page-fault errors, such as the one shown below. [ 102.101726] BUG: unable to handle page fault for address: ffffc90127000000 [...] [ 102.157102] RIP: 0010:udl_compress_hline16+0x219/0x940 [udl] [...] [ 102.243250] Call Trace: [ 102.245695] <TASK> [ 102.2477V95] ? validate_chain+0x24e/0x5e0 [ 102.251805] ? __lock_acquire+0x568/0xae0 [ 102.255807] udl_render_hline+0x165/0x341 [udl] [ 102.260338] ? __pfx_udl_render_hline+0x10/0x10 [udl] [ 102.265379] ? local_clock_noinstr+0xb/0x100 [ 102.269642] ? __lock_release.isra.0+0x16c/0x2e0 [ 102.274246] ? mark_held_locks+0x40/0x70 [ 102.278177] udl_primary_plane_helper_atomic_update+0x43e/0x680 [udl] [ 102.284606] ? __pfx_udl_primary_plane_helper_atomic_update+0x10/0x10 [udl] [ 102.291551] ? lockdep_hardirqs_on_prepare.part.0+0x92/0x170 [ 102.297208] ? lockdep_hardirqs_on+0x88/0x130 [ 102.301554] ? _raw_spin_unlock_irq+0x24/0x50 [ 102.305901] ? wait_for_completion_timeout+0x2bb/0x3a0 [ 102.311028] ? drm_atomic_helper_calc_timestamping_constants+0x141/0x200 [ 102.317714] ? drm_atomic_helper_commit_planes+0x3b6/0x1030 [ 102.323279] drm_atomic_helper_commit_planes+0x3b6/0x1030 [ 102.328664] drm_atomic_helper_commit_tail+0x41/0xb0 [ 102.333622] commit_tail+0x204/0x330 [...] [ 102.529946] ---[ end trace 0000000000000000 ]--- [ 102.651980] RIP: 0010:udl_compress_hline16+0x219/0x940 [udl] In this stack strace, udl (based on GEM-SHMEM) imported and vmap'ed a dma-buf from amdgpu. Amdgpu relocated the buffer, thereby invalidating the mapping. Provide a custom dma-buf vmap method in amdgpu that pins the object before mapping it's buffer's pages into kernel address space. Do the opposite in vunmap. Note that dma-buf vmap differs from GEM vmap in how it handles relocation. While dma-buf vmap keeps the buffer in place, GEM vmap requires the caller to keep the buffer in place. Hence, this fix is in amdgpu's dma-buf code instead of its GEM code. A discussion of various approaches to solving the problem is available at [1]. v3: - try (GTT | VRAM); drop CPU domain (Christian) v2: - only use mapable domains (Christian) - try pinning to domains in preferred order Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Fixes: 660cd44659a0 ("drm/shmem-helper: Import dmabuf without mapping its sg_table") Reported-by: Thomas Zimmermann <tzimmermann(a)suse.de> Closes: https://lore.kernel.org/dri-devel/ba1bdfb8-dbf7-4372-bdcb-df7e0511c702@suse… Cc: Shixiong Ou <oushixiong(a)kylinos.cn> Cc: Thomas Zimmermann <tzimmermann(a)suse.de> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Maxime Ripard <mripard(a)kernel.org> Cc: David Airlie <airlied(a)gmail.com> Cc: Simona Vetter <simona(a)ffwll.ch> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: dri-devel(a)lists.freedesktop.org Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org Link: https://lore.kernel.org/dri-devel/9792c6c3-a2b8-4b2b-b5ba-fba19b153e21@suse… # [1] --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 34 +++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 5743ebb2f1b7..ce27cb5bb05e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -285,6 +285,36 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, return ret; } +static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret; + + /* + * Pin to keep buffer in place while it's vmap'ed. The actual + * domain is not that important as long as it's mapable. Using + * GTT and VRAM should be compatible with most use cases. + */ + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM); + if (ret) + return ret; + ret = drm_gem_dmabuf_vmap(dma_buf, map); + if (ret) + amdgpu_bo_unpin(bo); + + return ret; +} + +static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + drm_gem_dmabuf_vunmap(dma_buf, map); + amdgpu_bo_unpin(bo); +} + const struct dma_buf_ops amdgpu_dmabuf_ops = { .attach = amdgpu_dma_buf_attach, .pin = amdgpu_dma_buf_pin, @@ -294,8 +324,8 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .release = drm_gem_dmabuf_release, .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, .mmap = drm_gem_dmabuf_mmap, - .vmap = drm_gem_dmabuf_vmap, - .vunmap = drm_gem_dmabuf_vunmap, + .vmap = amdgpu_dma_buf_vmap, + .vunmap = amdgpu_dma_buf_vunmap, }; /** -- 2.50.1

3 months, 3 weeks

3
4
0 0

Re: [PATCH 2/2] dma-buf: add warning when dma_fence is signaled from IOCTL

by kernel test robot

Hello, kernel test robot noticed "WARNING:at_drivers/dma-buf/dma-fence.c:#dma_fence_signal" on: commit: 409db68e04bdf052bc03f620e70339764b598ade ("[PATCH 2/2] dma-buf: add warning when dma_fence is signaled from IOCTL") url: https://github.com/intel-lab-lkp/linux/commits/Christian-K-nig/dma-buf-add-… base: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git 53e760d8949895390e256e723e7ee46618310361 patch link: https://lore.kernel.org/all/20250812143402.8619-2-christian.koenig@amd.com/ patch subject: [PATCH 2/2] dma-buf: add warning when dma_fence is signaled from IOCTL in testcase: ltp version: ltp-x86_64-9f512c1d8-1_20250809 with following parameters: test: syscalls-ipc-msgstress config: x86_64-rhel-9.4-ltp compiler: gcc-12 test machine: 8 threads 1 sockets Intel(R) Core(TM) i7-4770 CPU @ 3.40GHz (Haswell) with 16G memory (please refer to attached dmesg/kmsg for entire log/backtrace) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <oliver.sang(a)intel.com> | Closes: https://lore.kernel.org/oe-lkp/202508200843.8b006132-lkp@intel.com [ 51.636268][ T218] ------------[ cut here ]------------ [ 51.636273][ T218] WARNING: CPU: 3 PID: 218 at drivers/dma-buf/dma-fence.c:420 dma_fence_signal (drivers/dma-buf/dma-fence.c:420 drivers/dma-buf/dma-fence.c:502) [ 51.636292][ T218] Modules linked in: coretemp sd_mod snd_hda_codec_realtek_lib snd_hda_codec_generic sg ipmi_devintf kvm_intel snd_hda_intel ipmi_msghandler platform_profile i915(+) kvm snd_hda_codec intel_gtt dell_wmi snd_hda_core drm_buddy binfmt_misc dell_smbios snd_intel_dspcfg ttm dell_wmi_descriptor snd_intel_sdw_acpi snd_hwdep mei_wdt sparse_keymap irqbypass drm_display_helper ahci ghash_clmulni_intel snd_pcm libahci rfkill cec mei_me rapl intel_cstate dcdbas snd_timer drm_client_lib libata intel_uncore mei snd drm_kms_helper i2c_i801 i2c_smbus pcspkr lpc_ich soundcore video wmi fuse drm loop dm_mod [ 51.636385][ T218] CPU: 3 UID: 0 PID: 218 Comm: (udev-worker) Not tainted 6.17.0-rc1-00006-g409db68e04bd #1 PREEMPT(voluntary) [ 51.636395][ T218] Hardware name: Dell Inc. OptiPlex 9020/0DNKMN, BIOS A05 12/05/2013 [ 51.636399][ T218] RIP: 0010:dma_fence_signal (drivers/dma-buf/dma-fence.c:420 drivers/dma-buf/dma-fence.c:502) [ 51.636415][ T218] Code: 00 fc ff df 80 3c 02 00 75 36 48 8b 3b 4c 89 e6 e8 10 33 27 01 89 e8 5b 5d 41 5c c3 cc cc cc cc e8 b0 2e 77 fe 48 85 c0 75 bc <0f> 0b eb b8 0f 0b bd ea ff ff ff 5b 89 e8 5d 41 5c c3 cc cc cc cc All code ======== 0: 00 fc add %bh,%ah 2: ff (bad) 3: df 80 3c 02 00 75 filds 0x7500023c(%rax) 9: 36 48 8b 3b ss mov (%rbx),%rdi d: 4c 89 e6 mov %r12,%rsi 10: e8 10 33 27 01 call 0x1273325 15: 89 e8 mov %ebp,%eax 17: 5b pop %rbx 18: 5d pop %rbp 19: 41 5c pop %r12 1b: c3 ret 1c: cc int3 1d: cc int3 1e: cc int3 1f: cc int3 20: e8 b0 2e 77 fe call 0xfffffffffe772ed5 25: 48 85 c0 test %rax,%rax 28: 75 bc jne 0xffffffffffffffe6 2a:* 0f 0b ud2 <-- trapping instruction 2c: eb b8 jmp 0xffffffffffffffe6 2e: 0f 0b ud2 30: bd ea ff ff ff mov $0xffffffea,%ebp 35: 5b pop %rbx 36: 89 e8 mov %ebp,%eax 38: 5d pop %rbp 39: 41 5c pop %r12 3b: c3 ret 3c: cc int3 3d: cc int3 3e: cc int3 3f: cc int3 Code starting with the faulting instruction =========================================== 0: 0f 0b ud2 2: eb b8 jmp 0xffffffffffffffbc 4: 0f 0b ud2 6: bd ea ff ff ff mov $0xffffffea,%ebp b: 5b pop %rbx c: 89 e8 mov %ebp,%eax e: 5d pop %rbp f: 41 5c pop %r12 11: c3 ret 12: cc int3 13: cc int3 14: cc int3 15: cc int3 [ 51.636420][ T218] RSP: 0018:ffffc90000a9ed30 EFLAGS: 00010046 [ 51.636428][ T218] RAX: 0000000000000000 RBX: ffff88811750fc00 RCX: 0000000000000018 [ 51.636437][ T218] RDX: 0000000000000000 RSI: 0000000000000004 RDI: ffff88810691512c [ 51.636440][ T218] RBP: 0000000be56b1408 R08: 0000000000000001 R09: fffff52000153d9a [ 51.636445][ T218] R10: 0000000000000003 R11: ffff888108145000 R12: 0000000000000246 [ 51.636452][ T218] R13: ffffffffc1c9b060 R14: ffff88810406ba0c R15: 1ffff92000153dc2 [ 51.636455][ T218] FS: 00007efd90c038c0(0000) GS:ffff8883e4077000(0000) knlGS:0000000000000000 [ 51.636459][ T218] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 51.636462][ T218] CR2: 00007f5bd8238c20 CR3: 000000040ed8a005 CR4: 00000000001726f0 [ 51.636466][ T218] Call Trace: [ 51.636469][ T218] <TASK> [ 51.636477][ T218] fence_work (include/linux/dma-fence.h:272 drivers/gpu/drm/i915/i915_sw_fence_work.c:23) i915 [ 51.637304][ T218] fence_notify (drivers/gpu/drm/i915/i915_sw_fence_work.c:39) i915 [ 51.637827][ T218] __i915_sw_fence_complete (drivers/gpu/drm/i915/i915_sw_fence.c:201) i915 [ 51.638300][ T218] i915_vma_pin_ww (drivers/gpu/drm/i915/i915_vma.c:1601) i915 [ 51.638763][ T218] ? __pfx_i915_vma_pin_ww (drivers/gpu/drm/i915/i915_vma.c:1434) i915 [ 51.639218][ T218] ? i915_gem_object_make_unshrinkable (include/linux/list.h:215 include/linux/list.h:287 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:500) i915 [ 51.639648][ T218] ? i915_vma_make_unshrinkable (drivers/gpu/drm/i915/i915_vma.c:2292) i915 [ 51.640091][ T218] ? intel_ring_pin (drivers/gpu/drm/i915/gt/intel_ring.c:73) i915 [ 51.640505][ T218] intel_ring_submission_setup (drivers/gpu/drm/i915/gt/intel_ring_submission.c:1290 drivers/gpu/drm/i915/gt/intel_ring_submission.c:1421) i915 [ 51.640918][ T218] ? __pfx_intel_ring_submission_setup (drivers/gpu/drm/i915/gt/intel_ring_submission.c:1349) i915 [ 51.641232][ T65] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00 [ 51.641321][ T218] ? intel_engine_init_whitelist (drivers/gpu/drm/i915/gt/intel_workarounds.c:2104) i915 [ 51.641735][ T218] ? __intel_wakeref_init (arch/x86/include/asm/atomic.h:28 include/linux/atomic/atomic-arch-fallback.h:503 include/linux/atomic/atomic-instrumented.h:68 drivers/gpu/drm/i915/intel_wakeref.c:109) i915 [ 51.642126][ T218] intel_engines_init (drivers/gpu/drm/i915/gt/intel_engine_cs.c:1514) i915 [ 51.642521][ T218] ? i915_gem_object_make_unshrinkable (arch/x86/include/asm/atomic.h:93 include/linux/atomic/atomic-arch-fallback.h:667 include/linux/atomic/atomic-arch-fallback.h:1119 include/linux/atomic/atomic-instrumented.h:524 drivers/gpu/drm/i915/gem/i915_gem_shrinker.c:498) i915 [ 51.642929][ T218] ? __pfx_intel_ring_submission_setup (drivers/gpu/drm/i915/gt/intel_ring_submission.c:1349) i915 [ 51.643331][ T218] intel_gt_init (drivers/gpu/drm/i915/gt/intel_gt.c:719) i915 [ 51.643728][ T218] i915_gem_init (drivers/gpu/drm/i915/i915_gem.c:1191) i915 [ 51.644140][ T218] i915_driver_probe (drivers/gpu/drm/i915/i915_driver.c:831) i915 [ 51.644524][ T218] ? __pfx_i915_driver_probe (drivers/gpu/drm/i915/i915_driver.c:780) i915 [ 51.644903][ T218] ? drm_privacy_screen_get (drivers/gpu/drm/drm_privacy_screen.c:169) drm [ 51.645047][ T218] ? intel_display_driver_probe_defer (drivers/gpu/drm/i915/display/intel_display_driver.c:84) i915 [ 51.645483][ T218] ? i915_pci_probe (drivers/gpu/drm/i915/i915_pci.c:995) i915 [ 51.645876][ T218] ? __pfx_i915_pci_probe (drivers/gpu/drm/i915/i915_pci.c:956) i915 [ 51.646267][ T218] local_pci_probe (drivers/pci/pci-driver.c:324) [ 51.646283][ T218] pci_call_probe (drivers/pci/pci-driver.c:392) [ 51.646295][ T218] ? _raw_spin_lock (arch/x86/include/asm/atomic.h:107 include/linux/atomic/atomic-arch-fallback.h:2170 include/linux/atomic/atomic-instrumented.h:1302 include/asm-generic/qspinlock.h:111 include/linux/spinlock.h:187 include/linux/spinlock_api_smp.h:134 kernel/locking/spinlock.c:154) [ 51.646308][ T218] ? __pfx_pci_call_probe (drivers/pci/pci-driver.c:352) [ 51.646321][ T218] ? kernfs_add_one (fs/kernfs/dir.c:834) [ 51.646337][ T218] ? pci_assign_irq (drivers/pci/irq.c:149) [ 51.646350][ T218] ? pci_match_device (drivers/pci/pci-driver.c:159 (discriminator 1)) [ 51.646362][ T218] ? kernfs_put (arch/x86/include/asm/atomic.h:67 (discriminator 1) include/linux/atomic/atomic-arch-fallback.h:2278 (discriminator 1) include/linux/atomic/atomic-instrumented.h:1384 (discriminator 1) fs/kernfs/dir.c:569 (discriminator 1)) [ 51.646368][ T218] pci_device_probe (drivers/pci/pci-driver.c:452) [ 51.646377][ T218] really_probe (drivers/base/dd.c:581 drivers/base/dd.c:659) [ 51.646391][ T218] __driver_probe_device (drivers/base/dd.c:801) [ 51.646404][ T218] driver_probe_device (drivers/base/dd.c:831) [ 51.646416][ T218] __driver_attach (drivers/base/dd.c:1218) [ 51.646424][ T218] ? __pfx___driver_attach (drivers/base/dd.c:1158) [ 51.646428][ T218] bus_for_each_dev (drivers/base/bus.c:369) [ 51.646441][ T218] ? __pfx_bus_for_each_dev (drivers/base/bus.c:358) [ 51.646444][ T218] ? __kmalloc_cache_noprof (arch/x86/include/asm/jump_label.h:46 include/linux/memcontrol.h:1714 mm/slub.c:2210 mm/slub.c:4190 mm/slub.c:4229 mm/slub.c:4391) [ 51.646456][ T218] ? klist_add_tail (include/linux/list.h:150 include/linux/list.h:183 lib/klist.c:104 lib/klist.c:137) [ 51.646468][ T218] bus_add_driver (drivers/base/bus.c:678) [ 51.646482][ T218] driver_register (drivers/base/driver.c:249) [ 51.646490][ T218] i915_init (drivers/gpu/drm/i915/i915_driver.c:1428) i915 [ 51.646891][ T218] ? __pfx_i915_init (drivers/gpu/drm/i915/i915_config.c:13) i915 [ 51.647101][ T67] sd 2:0:0:0: [sdb] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA [ 51.647277][ T218] do_one_initcall (init/main.c:1269) [ 51.647292][ T218] ? kfree (mm/slub.c:4680 mm/slub.c:4879) [ 51.647304][ T218] ? __pfx_do_one_initcall (init/main.c:1260) [ 51.647315][ T218] ? kasan_unpoison (mm/kasan/shadow.c:156 mm/kasan/shadow.c:182) [ 51.647327][ T218] ? __kasan_slab_alloc (mm/kasan/common.c:329 mm/kasan/common.c:356) [ 51.647340][ T218] ? __kmalloc_cache_noprof (mm/slub.c:4180 mm/slub.c:4229 mm/slub.c:4391) [ 51.647352][ T218] ? kasan_save_track (arch/x86/include/asm/current.h:25 mm/kasan/common.c:60 mm/kasan/common.c:69) [ 51.647365][ T218] ? kasan_unpoison (mm/kasan/shadow.c:156 mm/kasan/shadow.c:182) [ 51.647377][ T218] do_init_module (kernel/module/main.c:3039) [ 51.647388][ T218] ? __pfx_do_init_module (kernel/module/main.c:3011) [ 51.647402][ T218] ? kfree (mm/slub.c:4680 mm/slub.c:4879) [ 51.647414][ T218] ? klp_module_coming (kernel/livepatch/core.c:1317) [ 51.647426][ T218] ? load_module (kernel/module/main.c:2468 kernel/module/main.c:2463 kernel/module/main.c:3504) [ 51.647441][ T218] load_module (kernel/module/main.c:3509) [ 51.647449][ T218] ? ima_post_read_file (security/integrity/ima/ima_main.c:896 security/integrity/ima/ima_main.c:878) [ 51.647466][ T218] ? __pfx_load_module (kernel/module/main.c:3353) [ 51.647478][ T218] ? __pfx_kernel_read_file (fs/kernel_read_file.c:38) [ 51.647489][ T218] ? init_module_from_file (kernel/module/main.c:3701) [ 51.647499][ T218] init_module_from_file (kernel/module/main.c:3701) [ 51.647514][ T218] ? __pfx_init_module_from_file (kernel/module/main.c:3677) [ 51.647525][ T218] ? mm_get_unmapped_area (arch/x86/include/asm/bitops.h:206 arch/x86/include/asm/bitops.h:238 include/asm-generic/bitops/instrumented-non-atomic.h:142 mm/mmap.c:805 mm/mmap.c:871) [ 51.647540][ T218] ? _raw_spin_lock (arch/x86/include/asm/atomic.h:107 include/linux/atomic/atomic-arch-fallback.h:2170 include/linux/atomic/atomic-instrumented.h:1302 include/asm-generic/qspinlock.h:111 include/linux/spinlock.h:187 include/linux/spinlock_api_smp.h:134 kernel/locking/spinlock.c:154) [ 51.647547][ T218] ? __pfx__raw_spin_lock (kernel/locking/spinlock.c:153) [ 51.647560][ T218] idempotent_init_module (kernel/module/main.c:3713) [ 51.647573][ T218] ? __pfx_idempotent_init_module (kernel/module/main.c:3705) [ 51.647582][ T218] ? __pfx___seccomp_filter (kernel/seccomp.c:1244) [ 51.647590][ T218] ? fdget (include/linux/atomic/atomic-arch-fallback.h:479 include/linux/atomic/atomic-instrumented.h:50 fs/file.c:1167 fs/file.c:1181) [ 51.647607][ T218] ? security_capable (security/security.c:1142) [ 51.647615][ T218] __x64_sys_finit_module (include/linux/file.h:62 include/linux/file.h:83 kernel/module/main.c:3736 kernel/module/main.c:3723 kernel/module/main.c:3723) [ 51.647627][ T218] ? syscall_trace_enter (kernel/entry/syscall-common.c:44) [ 51.647640][ T218] do_syscall_64 (arch/x86/entry/syscall_64.c:63 arch/x86/entry/syscall_64.c:94) [ 51.647657][ T218] ? fput (arch/x86/include/asm/atomic64_64.h:79 include/linux/atomic/atomic-arch-fallback.h:2913 include/linux/atomic/atomic-arch-fallback.h:3364 include/linux/atomic/atomic-long.h:698 include/linux/atomic/atomic-instrumented.h:3767 include/linux/file_ref.h:157 fs/file_table.c:544) [ 51.647668][ T218] ? ksys_mmap_pgoff (mm/mmap.c:609) [ 51.647682][ T218] ? do_syscall_64 (arch/x86/entry/syscall_64.c:63 arch/x86/entry/syscall_64.c:94) [ 51.647694][ T218] ? from_kgid_munged (kernel/user_namespace.c:535) [ 51.647708][ T218] ? _copy_to_user (arch/x86/include/asm/uaccess_64.h:126 arch/x86/include/asm/uaccess_64.h:147 include/linux/uaccess.h:197 lib/usercopy.c:26) [ 51.647722][ T218] ? cp_new_stat (fs/stat.c:471) [ 51.647732][ T218] ? __pfx_cp_new_stat (fs/stat.c:471) The kernel config and materials to reproduce are available at: https://download.01.org/0day-ci/archive/20250820/202508200843.8b006132-lkp@… -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

3 months, 3 weeks

2
1
0 0

Re: [PATCH v8 04/11] tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF

by Randy Dunlap

On 8/20/25 4:38 PM, Amirreza Zarrabi wrote: > +/** > + * struct tee_ioctl_invoke_func_arg - Invokes an object in a Trusted Application > + * @id: [in] Object id > + * @op: [in] Object operation, specific to the object > + * @ret: [out] return value > + * @num_params [in] number of parameters following this struct Missing colon (':') above: * @num_params: > + */ > +struct tee_ioctl_object_invoke_arg { > + __u64 id; > + __u32 op; > + __u32 ret; > + __u32 num_params; > + /* num_params tells the actual number of element in params */ > + struct tee_ioctl_param params[]; > +}; -- ~Randy

3 months, 3 weeks

1
0
0 0

[PATCH v5 0/2] dma-buf: heaps: Support carved-out heaps

by Maxime Ripard

Hi, This series is the follow-up of the discussion that John and I had some time ago here: https://lore.kernel.org/all/CANDhNCquJn6bH3KxKf65BWiTYLVqSd9892-xtFDHHqqyrr… The initial problem we were discussing was that I'm currently working on a platform which has a memory layout with ECC enabled. However, enabling the ECC has a number of drawbacks on that platform: lower performance, increased memory usage, etc. So for things like framebuffers, the trade-off isn't great and thus there's a memory region with ECC disabled to allocate from for such use cases. After a suggestion from John, I chose to first start using heap allocations flags to allow for userspace to ask for a particular ECC setup. This is then backed by a new heap type that runs from reserved memory chunks flagged as such, and the existing DT properties to specify the ECC properties. After further discussion, it was considered that flags were not the right solution, and relying on the names of the heaps would be enough to let userspace know the kind of buffer it deals with. Thus, even though the uAPI part of it has been dropped in this second version, we still need a driver to create heaps out of carved-out memory regions. In addition to the original usecase, a similar driver can be found in BSPs from most vendors, so I believe it would be a useful addition to the kernel. Let me know what you think, Maxime Signed-off-by: Maxime Ripard <mripard(a)kernel.org> --- Changes in v5: - Rebased on 6.16-rc2 - Switch from property to dedicated binding - Link to v4: https://lore.kernel.org/r/20250520-dma-buf-ecc-heap-v4-1-bd2e1f1bb42c@kerne… Changes in v4: - Rebased on 6.15-rc7 - Map buffers only when map is actually called, not at allocation time - Deal with restricted-dma-pool and shared-dma-pool - Reword Kconfig options - Properly report dma_map_sgtable failures - Link to v3: https://lore.kernel.org/r/20250407-dma-buf-ecc-heap-v3-0-97cdd36a5f29@kerne… Changes in v3: - Reworked global variable patch - Link to v2: https://lore.kernel.org/r/20250401-dma-buf-ecc-heap-v2-0-043fd006a1af@kerne… Changes in v2: - Add vmap/vunmap operations - Drop ECC flags uapi - Rebase on top of 6.14 - Link to v1: https://lore.kernel.org/r/20240515-dma-buf-ecc-heap-v1-0-54cbbd049511@kerne… --- Maxime Ripard (2): dt-bindings: reserved-memory: Introduce carved-out memory region binding dma-buf: heaps: Introduce a new heap for reserved memory .../bindings/reserved-memory/carved-out.yaml | 49 +++ drivers/dma-buf/heaps/Kconfig | 8 + drivers/dma-buf/heaps/Makefile | 1 + drivers/dma-buf/heaps/carveout_heap.c | 362 +++++++++++++++++++++ 4 files changed, 420 insertions(+) --- base-commit: d076bed8cb108ba2236d4d49c92303fda4036893 change-id: 20240515-dma-buf-ecc-heap-28a311d2c94e Best regards, -- Maxime Ripard <mripard(a)kernel.org>

3 months, 3 weeks

3
11
0 0

[PATCH v2] drm/amdgpu: Pin buffers while vmap'ing exported dma-buf objects

by Thomas Zimmermann

Current dma-buf vmap semantics require that the mapped buffer remains in place until the corresponding vunmap has completed. For GEM-SHMEM, this used to be guaranteed by a pin operation while creating an S/G table in import. GEM-SHMEN can now import dma-buf objects without creating the S/G table, so the pin is missing. Leads to page-fault errors, such as the one shown below. [ 102.101726] BUG: unable to handle page fault for address: ffffc90127000000 [...] [ 102.157102] RIP: 0010:udl_compress_hline16+0x219/0x940 [udl] [...] [ 102.243250] Call Trace: [ 102.245695] <TASK> [ 102.2477V95] ? validate_chain+0x24e/0x5e0 [ 102.251805] ? __lock_acquire+0x568/0xae0 [ 102.255807] udl_render_hline+0x165/0x341 [udl] [ 102.260338] ? __pfx_udl_render_hline+0x10/0x10 [udl] [ 102.265379] ? local_clock_noinstr+0xb/0x100 [ 102.269642] ? __lock_release.isra.0+0x16c/0x2e0 [ 102.274246] ? mark_held_locks+0x40/0x70 [ 102.278177] udl_primary_plane_helper_atomic_update+0x43e/0x680 [udl] [ 102.284606] ? __pfx_udl_primary_plane_helper_atomic_update+0x10/0x10 [udl] [ 102.291551] ? lockdep_hardirqs_on_prepare.part.0+0x92/0x170 [ 102.297208] ? lockdep_hardirqs_on+0x88/0x130 [ 102.301554] ? _raw_spin_unlock_irq+0x24/0x50 [ 102.305901] ? wait_for_completion_timeout+0x2bb/0x3a0 [ 102.311028] ? drm_atomic_helper_calc_timestamping_constants+0x141/0x200 [ 102.317714] ? drm_atomic_helper_commit_planes+0x3b6/0x1030 [ 102.323279] drm_atomic_helper_commit_planes+0x3b6/0x1030 [ 102.328664] drm_atomic_helper_commit_tail+0x41/0xb0 [ 102.333622] commit_tail+0x204/0x330 [...] [ 102.529946] ---[ end trace 0000000000000000 ]--- [ 102.651980] RIP: 0010:udl_compress_hline16+0x219/0x940 [udl] In this stack strace, udl (based on GEM-SHMEM) imported and vmap'ed a dma-buf from amdgpu. Amdgpu relocated the buffer, thereby invalidating the mapping. Provide a custom dma-buf vmap method in amdgpu that pins the object before mapping it's buffer's pages into kernel address space. Do the opposite in vunmap. Note that dma-buf vmap differs from GEM vmap in how it handles relocation. While dma-buf vmap keeps the buffer in place, GEM vmap requires the caller to keep the buffer in place. Hence, this fix is in amdgpu's dma-buf code instead of its GEM code. A discussion of various approaches to solving the problem is available at [1]. v2: - only use mapable domains (Christian) - try pinning to domains in prefered order Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Fixes: 660cd44659a0 ("drm/shmem-helper: Import dmabuf without mapping its sg_table") Reported-by: Thomas Zimmermann <tzimmermann(a)suse.de> Closes: https://lore.kernel.org/dri-devel/ba1bdfb8-dbf7-4372-bdcb-df7e0511c702@suse… Cc: Shixiong Ou <oushixiong(a)kylinos.cn> Cc: Thomas Zimmermann <tzimmermann(a)suse.de> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Maxime Ripard <mripard(a)kernel.org> Cc: David Airlie <airlied(a)gmail.com> Cc: Simona Vetter <simona(a)ffwll.ch> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: dri-devel(a)lists.freedesktop.org Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org Link: https://lore.kernel.org/dri-devel/9792c6c3-a2b8-4b2b-b5ba-fba19b153e21@suse… # [1] Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 41 ++++++++++++++++++++- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 5743ebb2f1b7..471b41bd3e29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -285,6 +285,43 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, return ret; } +static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret; + + /* + * Pin to keep buffer in place while it's vmap'ed. The actual + * domain is not that important as long as it's mapable. Using + * GTT should be compatible with most use cases. VRAM and CPU + * are the fallbacks if the buffer has already been pinned there. + */ + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (ret) { + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_VRAM); + if (ret) { + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_CPU); + if (ret) + return ret; + } + } + ret = drm_gem_dmabuf_vmap(dma_buf, map); + if (ret) + amdgpu_bo_unpin(bo); + + return ret; +} + +static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + drm_gem_dmabuf_vunmap(dma_buf, map); + amdgpu_bo_unpin(bo); +} + const struct dma_buf_ops amdgpu_dmabuf_ops = { .attach = amdgpu_dma_buf_attach, .pin = amdgpu_dma_buf_pin, @@ -294,8 +331,8 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .release = drm_gem_dmabuf_release, .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, .mmap = drm_gem_dmabuf_mmap, - .vmap = drm_gem_dmabuf_vmap, - .vunmap = drm_gem_dmabuf_vunmap, + .vmap = amdgpu_dma_buf_vmap, + .vunmap = amdgpu_dma_buf_vunmap, }; /** -- 2.50.1

3 months, 3 weeks

2
2
0 0

Re: [PATCH net-next 5/6] net: ti: icssg-prueth: Add AF_XDP zero copy for RX

by Jakub Kicinski

On Mon, 18 Aug 2025 16:54:23 +0530 Meghana Malladi wrote: > @@ -1332,6 +1350,13 @@ static int prueth_xsk_wakeup(struct net_device *ndev, u32 qid, u32 flags) > } > } > > + if (flags & XDP_WAKEUP_RX) { > + if (!napi_if_scheduled_mark_missed(&emac->napi_rx)) { > + if (likely(napi_schedule_prep(&emac->napi_rx))) > + __napi_schedule(&emac->napi_rx); > + } > + } > + > return 0; I suspect this series is generated against old source or there's another conflicting series in flight, because git ends up applying this chunk to prueth_xsk_pool_disable() :S Before you proceed with AF_XDP could you make this driver build under COMPILE_TEST on x86? This is very easy to miss, luckily we got an off list report but its pure luck. And obviously much more effort for the maintainers to investigate than if it was caught by the CI. -- pw-bot: cr

3 months, 3 weeks

1
0
0 0

Re: [PATCH 4/4] dma-buf/fence-chain: Speed up processing of rearmed callbacks

by Christian König

On 19.08.25 11:04, Janusz Krzysztofik wrote: > On Monday, 18 August 2025 16:42:56 CEST Christian König wrote: >> On 18.08.25 16:30, Janusz Krzysztofik wrote: >>> Hi Christian, >>> >>> On Thursday, 14 August 2025 14:24:29 CEST Christian König wrote: >>>> >>>> On 14.08.25 10:16, Janusz Krzysztofik wrote: >>>>> When first user starts waiting on a not yet signaled fence of a chain >>>>> link, a dma_fence_chain callback is added to a user fence of that link. >>>>> When the user fence of that chain link is then signaled, the chain is >>>>> traversed in search for a first not signaled link and the callback is >>>>> rearmed on a user fence of that link. >>>>> >>>>> Since chain fences may be exposed to user space, e.g. over drm_syncobj >>>>> IOCTLs, users may start waiting on any link of the chain, then many links >>>>> of a chain may have signaling enabled and their callbacks added to their >>>>> user fences. Once an arbitrary user fence is signaled, all >>>>> dma_fence_chain callbacks added to it so far must be rearmed to another >>>>> user fence of the chain. In extreme scenarios, when all N links of a >>>>> chain are awaited and then signaled in reverse order, the dma_fence_chain >>>>> callback may be called up to N * (N + 1) / 2 times (an arithmetic series). >>>>> >>>>> To avoid that potential excessive accumulation of dma_fence_chain >>>>> callbacks, rearm a trimmed-down, signal only callback version to the base >>>>> fence of a previous link, if not yet signaled, otherwise just signal the >>>>> base fence of the current link instead of traversing the chain in search >>>>> for a first not signaled link and moving all callbacks collected so far to >>>>> a user fence of that link. >>>> >>>> Well clear NAK to that! You can easily overflow the kernel stack with that! >>> >>> I'll be happy to propose a better solution, but for that I need to understand >>> better your message. Could you please point out an exact piece of the >>> proposed code and/or describe a scenario where you can see the risk of stack >>> overflow? >> >> The sentence "rearm .. to the base fence of a previous link" sounds like you are trying to install a callback on the signaling to the previous chain element. >> >> That is exactly what I pointed out previously where you need to be super careful because when this chain signals the callbacks will execute recursively which means that you can trivially overflow the kernel stack if you have more than a handful of chain elements. >> >> In other words A waits for B, B waits for C, C waits for D etc.... when D finally signals it will call C which in turn calls B which in turn calls A. > > OK, maybe my commit description was not precise enough, however, I didn't > describe implementation details (how) intentionally. > When D signals then it doesn't call C directly, only it submits an irq work > that calls C. Then C doesn't just call B, only it submits another irq work > that calls B, and so on. > Doesn't that code pattern effectively break the recursion loop into separate > work items, each with its own separate stack? No, it's architecture dependent if the irq_work executes on a separate stack or not. You would need a work_struct to really separate the two and I would reject that because it adds additional latency to the signaling path. >> >> Even if the chain is a recursive data structure you absolutely can't use recursion for the handling of it. >> >> Maybe I misunderstood your textual description but reading a sentence like this rings all alarm bells here. Otherwise I can't see what the patch is supposed to be optimizing. > > OK, maybe I should start my commit description of this patch with a copy of > the first sentence from cover letter and also from patch 1/4 description that > informs about the problem as reported by CI. Maybe I should also provide a > comparison of measured signaling times from trybot executions [1][2][3]. > Here are example numbers from CI machine fi-bsw-n3050: Yeah and I've pointed out before that this is irrelevant. The problem is *not* the dma_fence_chain implementation, that one is doing exactly what is expected to do. The problem is that the test case is nonsense. I've pointed that out numerous times now! Regards, Christian. > > With signaling time reports only added to selftests (patch 1 of 4): > <6> [777.914451] dma-buf: Running dma_fence_chain/wait_forward > <6> [778.123516] wait_forward: 4096 signals in 21373487 ns > <6> [778.335709] dma-buf: Running dma_fence_chain/wait_backward > <6> [795.791546] wait_backward: 4096 signals in 17249051192 ns > <6> [795.859699] dma-buf: Running dma_fence_chain/wait_random > <6> [796.161375] wait_random: 4096 signals in 97386256 ns > > With dma_fence_enable_signaling() replaced in selftests with dma_fence_wait() > (patches 1-3 of 4): > <6> [782.505692] dma-buf: Running dma_fence_chain/wait_forward > <6> [784.609213] wait_forward: 4096 signals in 36513103 ns > <3> [784.837226] Reported -4 for kthread_stop_put(0)! > <6> [785.147643] dma-buf: Running dma_fence_chain/wait_backward > <6> [806.367763] wait_backward: 4096 signals in 18428009499 ns > <6> [807.175325] dma-buf: Running dma_fence_chain/wait_random > <6> [809.453942] wait_random: 4096 signals in 119761950 ns > > With the fix (patches 1-4 of 4): > <6> [731.519020] dma-buf: Running dma_fence_chain/wait_forward > <6> [733.623375] wait_forward: 4096 signals in 31890220 ns > <6> [734.258972] dma-buf: Running dma_fence_chain/wait_backward > <6> [736.267325] wait_backward: 4096 signals in 39007955 ns > <6> [736.700221] dma-buf: Running dma_fence_chain/wait_random > <6> [739.346706] wait_random: 4096 signals in 48384865 ns > > Signaling time in wait_backward selftest has been reduced from 17s to 39ms. > > [1] https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_152785v1/index.html? > [2] https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_152828v2/index.html? > [3] https://intel-gfx-ci.01.org/tree/drm-tip/Trybot_152830v2/index.html? > >> >>>> >>>> Additional to this messing with the fence ops outside of the dma_fence code is an absolute no-go. >>> >>> Could you please explain what piece of code you are referring to when you say >>> "messing with the fence ops outside the dma_fence code"? If not this patch >>> then which particular one of this series did you mean? I'm assuming you >>> didn't mean drm_syncobj code that I mentioned in my commit descriptions. >> >> See below. >> >>> >>> Thanks, >>> Janusz >>> >>>> >>>> Regards, >>>> Christian. >>>> >>>>> >>>>> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904 >>>>> Suggested-by: Chris Wilson <chris.p.wilson(a)linux.intel.com> >>>>> Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik(a)linux.intel.com> >>>>> --- >>>>> drivers/dma-buf/dma-fence-chain.c | 101 +++++++++++++++++++++++++----- >>>>> 1 file changed, 84 insertions(+), 17 deletions(-) >>>>> >>>>> diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c >>>>> index a8a90acf4f34d..90eff264ee05c 100644 >>>>> --- a/drivers/dma-buf/dma-fence-chain.c >>>>> +++ b/drivers/dma-buf/dma-fence-chain.c >>>>> @@ -119,46 +119,113 @@ static const char *dma_fence_chain_get_timeline_name(struct dma_fence *fence) >>>>> return "unbound"; >>>>> } >>>>> >>>>> -static void dma_fence_chain_irq_work(struct irq_work *work) >>>>> +static void signal_irq_work(struct irq_work *work) >>>>> { >>>>> struct dma_fence_chain *chain; >>>>> >>>>> chain = container_of(work, typeof(*chain), work); >>>>> >>>>> - /* Try to rearm the callback */ >>>>> - if (!dma_fence_chain_enable_signaling(&chain->base)) >>>>> - /* Ok, we are done. No more unsignaled fences left */ >>>>> - dma_fence_signal(&chain->base); >>>>> + dma_fence_signal(&chain->base); >>>>> dma_fence_put(&chain->base); >>>>> } >>>>> >>>>> -static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb) >>>>> +static void signal_cb(struct dma_fence *f, struct dma_fence_cb *cb) >>>>> +{ >>>>> + struct dma_fence_chain *chain; >>>>> + >>>>> + chain = container_of(cb, typeof(*chain), cb); >>>>> + init_irq_work(&chain->work, signal_irq_work); >>>>> + irq_work_queue(&chain->work); >>>>> +} >>>>> + >>>>> +static void rearm_irq_work(struct irq_work *work) >>>>> +{ >>>>> + struct dma_fence_chain *chain; >>>>> + struct dma_fence *prev; >>>>> + >>>>> + chain = container_of(work, typeof(*chain), work); >>>>> + >>>>> + rcu_read_lock(); >>>>> + prev = rcu_dereference(chain->prev); >>>>> + if (prev && dma_fence_add_callback(prev, &chain->cb, signal_cb)) >>>>> + prev = NULL; >>>>> + rcu_read_unlock(); >>>>> + if (prev) >>>>> + return; >>>>> + >>>>> + /* Ok, we are done. No more unsignaled fences left */ >>>>> + signal_irq_work(work); >>>>> +} >>>>> + >>>>> +static inline bool fence_is_signaled__nested(struct dma_fence *fence) >>>>> +{ >>>>> + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) >>>>> + return true; >>>>> + >> >>>>> + if (fence->ops->signaled && fence->ops->signaled(fence)) { >> >> Calling this outside of dma-fence.[ch] is a clear no-go. > > But this patch applies only to drivers/dma-buf/dma-fence-chain.c, not > outside of it. > > Thanks, > Janusz > >> >> Regards, >> Christian. >> >>>>> + unsigned long flags; >>>>> + >>>>> + spin_lock_irqsave_nested(fence->lock, flags, SINGLE_DEPTH_NESTING); >>>>> + dma_fence_signal_locked(fence); >>>>> + spin_unlock_irqrestore(fence->lock, flags); >>>>> + >>>>> + return true; >>>>> + } >>>>> + >>>>> + return false; >>>>> +} >>>>> + >>>>> +static bool prev_is_signaled(struct dma_fence_chain *chain) >>>>> +{ >>>>> + struct dma_fence *prev; >>>>> + bool result; >>>>> + >>>>> + rcu_read_lock(); >>>>> + prev = rcu_dereference(chain->prev); >>>>> + result = !prev || fence_is_signaled__nested(prev); >>>>> + rcu_read_unlock(); >>>>> + >>>>> + return result; >>>>> +} >>>>> + >>>>> +static void rearm_or_signal_cb(struct dma_fence *f, struct dma_fence_cb *cb) >>>>> { >>>>> struct dma_fence_chain *chain; >>>>> >>>>> chain = container_of(cb, typeof(*chain), cb); >>>>> - init_irq_work(&chain->work, dma_fence_chain_irq_work); >>>>> + if (prev_is_signaled(chain)) { >>>>> + /* Ok, we are done. No more unsignaled fences left */ >>>>> + init_irq_work(&chain->work, signal_irq_work); >>>>> + } else { >>>>> + /* Try to rearm the callback */ >>>>> + init_irq_work(&chain->work, rearm_irq_work); >>>>> + } >>>>> + >>>>> irq_work_queue(&chain->work); >>>>> - dma_fence_put(f); >>>>> } >>>>> >>>>> static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) >>>>> { >>>>> struct dma_fence_chain *head = to_dma_fence_chain(fence); >>>>> + int err = -ENOENT; >>>>> >>>>> - dma_fence_get(&head->base); >>>>> - dma_fence_chain_for_each(fence, &head->base) { >>>>> - struct dma_fence *f = dma_fence_chain_contained(fence); >>>>> + if (WARN_ON(!head)) >>>>> + return false; >>>>> >>>>> - dma_fence_get(f); >>>>> - if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) { >>>>> + dma_fence_get(fence); >>>>> + if (head->fence) >>>>> + err = dma_fence_add_callback(head->fence, &head->cb, rearm_or_signal_cb); >>>>> + if (err) { >>>>> + if (prev_is_signaled(head)) { >>>>> dma_fence_put(fence); >>>>> - return true; >>>>> + } else { >>>>> + init_irq_work(&head->work, rearm_irq_work); >>>>> + irq_work_queue(&head->work); >>>>> + err = 0; >>>>> } >>>>> - dma_fence_put(f); >>>>> } >>>>> - dma_fence_put(&head->base); >>>>> - return false; >>>>> + >>>>> + return !err; >>>>> } >>>>> >>>>> static bool dma_fence_chain_signaled(struct dma_fence *fence) >>>> >>>> >>> >>> >>> >>> >> >> > > > >

3 months, 3 weeks

1
0
0 0

[PATCH] drm/amdgpu: Pin buffer while vmap'ing exported dma-buf objects

by Thomas Zimmermann

Current dma-buf vmap semantics require that the mapped buffer remains in place until the corresponding vunmap has completed. For GEM-SHMEM, this used to be guaranteed by a pin operation while creating an S/G table in import. GEM-SHMEN can now import dma-buf objects without creating the S/G table, so the pin is missing. Leads to page-fault errors, such as the one shown below. [ 102.101726] BUG: unable to handle page fault for address: ffffc90127000000 [...] [ 102.157102] RIP: 0010:udl_compress_hline16+0x219/0x940 [udl] [...] [ 102.243250] Call Trace: [ 102.245695] <TASK> [ 102.2477V95] ? validate_chain+0x24e/0x5e0 [ 102.251805] ? __lock_acquire+0x568/0xae0 [ 102.255807] udl_render_hline+0x165/0x341 [udl] [ 102.260338] ? __pfx_udl_render_hline+0x10/0x10 [udl] [ 102.265379] ? local_clock_noinstr+0xb/0x100 [ 102.269642] ? __lock_release.isra.0+0x16c/0x2e0 [ 102.274246] ? mark_held_locks+0x40/0x70 [ 102.278177] udl_primary_plane_helper_atomic_update+0x43e/0x680 [udl] [ 102.284606] ? __pfx_udl_primary_plane_helper_atomic_update+0x10/0x10 [udl] [ 102.291551] ? lockdep_hardirqs_on_prepare.part.0+0x92/0x170 [ 102.297208] ? lockdep_hardirqs_on+0x88/0x130 [ 102.301554] ? _raw_spin_unlock_irq+0x24/0x50 [ 102.305901] ? wait_for_completion_timeout+0x2bb/0x3a0 [ 102.311028] ? drm_atomic_helper_calc_timestamping_constants+0x141/0x200 [ 102.317714] ? drm_atomic_helper_commit_planes+0x3b6/0x1030 [ 102.323279] drm_atomic_helper_commit_planes+0x3b6/0x1030 [ 102.328664] drm_atomic_helper_commit_tail+0x41/0xb0 [ 102.333622] commit_tail+0x204/0x330 [...] [ 102.529946] ---[ end trace 0000000000000000 ]--- [ 102.651980] RIP: 0010:udl_compress_hline16+0x219/0x940 [udl] In this stack strace, udl (based on GEM-SHMEM) imported and vmap'ed a dma-buf from amdgpu. Amdgpu relocated the buffer, thereby invalidating the mapping. Provide a custom dma-buf vmap method in amdgpu that pins the object before mapping it's buffer's pages into kernel address space. Do the opposite in vunmap. Note that dma-buf vmap differs from GEM vmap in how it handles relocation. While dma-buf vmap keeps the buffer in place, GEM vmap requires the caller to keep the buffer in place. Hence, this fix is in amdgpu's dma-buf code instead of its GEM code. A discussion of various approaches to solving the problem is available at [1]. Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Fixes: 660cd44659a0 ("drm/shmem-helper: Import dmabuf without mapping its sg_table") Reported-by: Thomas Zimmermann <tzimmermann(a)suse.de> Closes: https://lore.kernel.org/dri-devel/ba1bdfb8-dbf7-4372-bdcb-df7e0511c702@suse… Cc: Shixiong Ou <oushixiong(a)kylinos.cn> Cc: Thomas Zimmermann <tzimmermann(a)suse.de> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Maxime Ripard <mripard(a)kernel.org> Cc: David Airlie <airlied(a)gmail.com> Cc: Simona Vetter <simona(a)ffwll.ch> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: dri-devel(a)lists.freedesktop.org Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org Link: https://lore.kernel.org/dri-devel/9792c6c3-a2b8-4b2b-b5ba-fba19b153e21@suse… # [1] --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 36 +++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 5743ebb2f1b7..5b33776eeece 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -285,6 +285,38 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, return ret; } +static int amdgpu_dma_buf_vmap(struct dma_buf *dma_buf, struct iosys_map *map) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret; + + /* + * Pin to keep buffer in place while it's vmap'ed. The actual + * location is not important as long as it's mapable. + * + * This code is required for exporting to GEM-SHMEM without S/G table. + * Once GEM-SHMEM supports dynamic imports, it should be dropped. + */ + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_MASK); + if (ret) + return ret; + ret = drm_gem_dmabuf_vmap(dma_buf, map); + if (ret) + amdgpu_bo_unpin(bo); + + return ret; +} + +static void amdgpu_dma_buf_vunmap(struct dma_buf *dma_buf, struct iosys_map *map) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + drm_gem_dmabuf_vunmap(dma_buf, map); + amdgpu_bo_unpin(bo); +} + const struct dma_buf_ops amdgpu_dmabuf_ops = { .attach = amdgpu_dma_buf_attach, .pin = amdgpu_dma_buf_pin, @@ -294,8 +326,8 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .release = drm_gem_dmabuf_release, .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, .mmap = drm_gem_dmabuf_mmap, - .vmap = drm_gem_dmabuf_vmap, - .vunmap = drm_gem_dmabuf_vunmap, + .vmap = amdgpu_dma_buf_vmap, + .vunmap = amdgpu_dma_buf_vunmap, }; /** -- 2.50.1

3 months, 4 weeks

2
4
0 0

Re: [PATCH 4/4] dma-buf/fence-chain: Speed up processing of rearmed callbacks

by Christian König

On 18.08.25 16:30, Janusz Krzysztofik wrote: > Hi Christian, > > On Thursday, 14 August 2025 14:24:29 CEST Christian König wrote: >> >> On 14.08.25 10:16, Janusz Krzysztofik wrote: >>> When first user starts waiting on a not yet signaled fence of a chain >>> link, a dma_fence_chain callback is added to a user fence of that link. >>> When the user fence of that chain link is then signaled, the chain is >>> traversed in search for a first not signaled link and the callback is >>> rearmed on a user fence of that link. >>> >>> Since chain fences may be exposed to user space, e.g. over drm_syncobj >>> IOCTLs, users may start waiting on any link of the chain, then many links >>> of a chain may have signaling enabled and their callbacks added to their >>> user fences. Once an arbitrary user fence is signaled, all >>> dma_fence_chain callbacks added to it so far must be rearmed to another >>> user fence of the chain. In extreme scenarios, when all N links of a >>> chain are awaited and then signaled in reverse order, the dma_fence_chain >>> callback may be called up to N * (N + 1) / 2 times (an arithmetic series). >>> >>> To avoid that potential excessive accumulation of dma_fence_chain >>> callbacks, rearm a trimmed-down, signal only callback version to the base >>> fence of a previous link, if not yet signaled, otherwise just signal the >>> base fence of the current link instead of traversing the chain in search >>> for a first not signaled link and moving all callbacks collected so far to >>> a user fence of that link. >> >> Well clear NAK to that! You can easily overflow the kernel stack with that! > > I'll be happy to propose a better solution, but for that I need to understand > better your message. Could you please point out an exact piece of the > proposed code and/or describe a scenario where you can see the risk of stack > overflow? The sentence "rearm .. to the base fence of a previous link" sounds like you are trying to install a callback on the signaling to the previous chain element. That is exactly what I pointed out previously where you need to be super careful because when this chain signals the callbacks will execute recursively which means that you can trivially overflow the kernel stack if you have more than a handful of chain elements. In other words A waits for B, B waits for C, C waits for D etc.... when D finally signals it will call C which in turn calls B which in turn calls A. Even if the chain is a recursive data structure you absolutely can't use recursion for the handling of it. Maybe I misunderstood your textual description but reading a sentence like this rings all alarm bells here. Otherwise I can't see what the patch is supposed to be optimizing. >> >> Additional to this messing with the fence ops outside of the dma_fence code is an absolute no-go. > > Could you please explain what piece of code you are referring to when you say > "messing with the fence ops outside the dma_fence code"? If not this patch > then which particular one of this series did you mean? I'm assuming you > didn't mean drm_syncobj code that I mentioned in my commit descriptions. See below. > > Thanks, > Janusz > >> >> Regards, >> Christian. >> >>> >>> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904 >>> Suggested-by: Chris Wilson <chris.p.wilson(a)linux.intel.com> >>> Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik(a)linux.intel.com> >>> --- >>> drivers/dma-buf/dma-fence-chain.c | 101 +++++++++++++++++++++++++----- >>> 1 file changed, 84 insertions(+), 17 deletions(-) >>> >>> diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c >>> index a8a90acf4f34d..90eff264ee05c 100644 >>> --- a/drivers/dma-buf/dma-fence-chain.c >>> +++ b/drivers/dma-buf/dma-fence-chain.c >>> @@ -119,46 +119,113 @@ static const char *dma_fence_chain_get_timeline_name(struct dma_fence *fence) >>> return "unbound"; >>> } >>> >>> -static void dma_fence_chain_irq_work(struct irq_work *work) >>> +static void signal_irq_work(struct irq_work *work) >>> { >>> struct dma_fence_chain *chain; >>> >>> chain = container_of(work, typeof(*chain), work); >>> >>> - /* Try to rearm the callback */ >>> - if (!dma_fence_chain_enable_signaling(&chain->base)) >>> - /* Ok, we are done. No more unsignaled fences left */ >>> - dma_fence_signal(&chain->base); >>> + dma_fence_signal(&chain->base); >>> dma_fence_put(&chain->base); >>> } >>> >>> -static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb) >>> +static void signal_cb(struct dma_fence *f, struct dma_fence_cb *cb) >>> +{ >>> + struct dma_fence_chain *chain; >>> + >>> + chain = container_of(cb, typeof(*chain), cb); >>> + init_irq_work(&chain->work, signal_irq_work); >>> + irq_work_queue(&chain->work); >>> +} >>> + >>> +static void rearm_irq_work(struct irq_work *work) >>> +{ >>> + struct dma_fence_chain *chain; >>> + struct dma_fence *prev; >>> + >>> + chain = container_of(work, typeof(*chain), work); >>> + >>> + rcu_read_lock(); >>> + prev = rcu_dereference(chain->prev); >>> + if (prev && dma_fence_add_callback(prev, &chain->cb, signal_cb)) >>> + prev = NULL; >>> + rcu_read_unlock(); >>> + if (prev) >>> + return; >>> + >>> + /* Ok, we are done. No more unsignaled fences left */ >>> + signal_irq_work(work); >>> +} >>> + >>> +static inline bool fence_is_signaled__nested(struct dma_fence *fence) >>> +{ >>> + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) >>> + return true; >>> + >>> + if (fence->ops->signaled && fence->ops->signaled(fence)) { Calling this outside of dma-fence.[ch] is a clear no-go. Regards, Christian. >>> + unsigned long flags; >>> + >>> + spin_lock_irqsave_nested(fence->lock, flags, SINGLE_DEPTH_NESTING); >>> + dma_fence_signal_locked(fence); >>> + spin_unlock_irqrestore(fence->lock, flags); >>> + >>> + return true; >>> + } >>> + >>> + return false; >>> +} >>> + >>> +static bool prev_is_signaled(struct dma_fence_chain *chain) >>> +{ >>> + struct dma_fence *prev; >>> + bool result; >>> + >>> + rcu_read_lock(); >>> + prev = rcu_dereference(chain->prev); >>> + result = !prev || fence_is_signaled__nested(prev); >>> + rcu_read_unlock(); >>> + >>> + return result; >>> +} >>> + >>> +static void rearm_or_signal_cb(struct dma_fence *f, struct dma_fence_cb *cb) >>> { >>> struct dma_fence_chain *chain; >>> >>> chain = container_of(cb, typeof(*chain), cb); >>> - init_irq_work(&chain->work, dma_fence_chain_irq_work); >>> + if (prev_is_signaled(chain)) { >>> + /* Ok, we are done. No more unsignaled fences left */ >>> + init_irq_work(&chain->work, signal_irq_work); >>> + } else { >>> + /* Try to rearm the callback */ >>> + init_irq_work(&chain->work, rearm_irq_work); >>> + } >>> + >>> irq_work_queue(&chain->work); >>> - dma_fence_put(f); >>> } >>> >>> static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) >>> { >>> struct dma_fence_chain *head = to_dma_fence_chain(fence); >>> + int err = -ENOENT; >>> >>> - dma_fence_get(&head->base); >>> - dma_fence_chain_for_each(fence, &head->base) { >>> - struct dma_fence *f = dma_fence_chain_contained(fence); >>> + if (WARN_ON(!head)) >>> + return false; >>> >>> - dma_fence_get(f); >>> - if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) { >>> + dma_fence_get(fence); >>> + if (head->fence) >>> + err = dma_fence_add_callback(head->fence, &head->cb, rearm_or_signal_cb); >>> + if (err) { >>> + if (prev_is_signaled(head)) { >>> dma_fence_put(fence); >>> - return true; >>> + } else { >>> + init_irq_work(&head->work, rearm_irq_work); >>> + irq_work_queue(&head->work); >>> + err = 0; >>> } >>> - dma_fence_put(f); >>> } >>> - dma_fence_put(&head->base); >>> - return false; >>> + >>> + return !err; >>> } >>> >>> static bool dma_fence_chain_signaled(struct dma_fence *fence) >> >> > > > >

3 months, 4 weeks

1
0
0 0

[PATCH v2 0/3] udmabuf: Sync to attached devices

by Andrew Davis

Hello all, This series makes it so the udmabuf will sync the backing buffer with the set of attached devices as required for DMA-BUFs when doing {begin,end}_cpu_access. Thanks Andrew Changes for v2: - fix attachment table use-after-free - rebased on v6.17-rc1 Andrew Davis (3): udmabuf: Keep track current device mappings udmabuf: Sync buffer mappings for attached devices udmabuf: Use module_misc_device() to register this device drivers/dma-buf/udmabuf.c | 133 +++++++++++++++++++------------------- 1 file changed, 67 insertions(+), 66 deletions(-) -- 2.39.2

3 months, 4 weeks

2
6
0 0

[PATCH] drm/gem-shmem: Pin and unpin buffers when importing w/o S/G table

by Thomas Zimmermann

Imported dma-buf objects need to be pinned while being vmap'ed into kernel address space. This used to be done before while creating an S/G table. GEM-SHMEN can import dma-buf objects without creating the S/G table, but the pin/unpin is now missing. Leads to page-mapping errors such as the one shown below. [ 102.101726] BUG: unable to handle page fault for address: ffffc90127000000 [...] [ 102.157102] RIP: 0010:udl_compress_hline16+0x219/0x940 [udl] [...] [ 102.243250] Call Trace: [ 102.245695] <TASK> [ 102.2477V95] ? validate_chain+0x24e/0x5e0 [ 102.251805] ? __lock_acquire+0x568/0xae0 [ 102.255807] udl_render_hline+0x165/0x341 [udl] [ 102.260338] ? __pfx_udl_render_hline+0x10/0x10 [udl] [ 102.265379] ? local_clock_noinstr+0xb/0x100 [ 102.269642] ? __lock_release.isra.0+0x16c/0x2e0 [ 102.274246] ? mark_held_locks+0x40/0x70 [ 102.278177] udl_primary_plane_helper_atomic_update+0x43e/0x680 [udl] [ 102.284606] ? __pfx_udl_primary_plane_helper_atomic_update+0x10/0x10 [udl] [ 102.291551] ? lockdep_hardirqs_on_prepare.part.0+0x92/0x170 [ 102.297208] ? lockdep_hardirqs_on+0x88/0x130 [ 102.301554] ? _raw_spin_unlock_irq+0x24/0x50 [ 102.305901] ? wait_for_completion_timeout+0x2bb/0x3a0 [ 102.311028] ? drm_atomic_helper_calc_timestamping_constants+0x141/0x200 [ 102.317714] ? drm_atomic_helper_commit_planes+0x3b6/0x1030 [ 102.323279] drm_atomic_helper_commit_planes+0x3b6/0x1030 [ 102.328664] drm_atomic_helper_commit_tail+0x41/0xb0 [ 102.333622] commit_tail+0x204/0x330 [...] [ 102.529946] ---[ end trace 0000000000000000 ]--- [ 102.651980] RIP: 0010:udl_compress_hline16+0x219/0x940 [udl] Support pin/unpin in drm_buf_map_attachment() without creating an S/G table. Passing DMA_NONE for the DMA direction will only pin. Do the inverse for unmap_attachment(). Modify GEM-SHMEM accordingly, so that it pins the imported dma-buf. Signed-off-by: Thomas Zimmermann <tzimmermann(a)suse.de> Fixes: 660cd44659a0 ("drm/shmem-helper: Import dmabuf without mapping its sg_table") Reported-by: Thomas Zimmermann <tzimmermann(a)suse.de> Closes: https://lore.kernel.org/dri-devel/ba1bdfb8-dbf7-4372-bdcb-df7e0511c702@suse… Cc: Shixiong Ou <oushixiong(a)kylinos.cn> Cc: Thomas Zimmermann <tzimmermann(a)suse.de> Cc: Maarten Lankhorst <maarten.lankhorst(a)linux.intel.com> Cc: Maxime Ripard <mripard(a)kernel.org> Cc: David Airlie <airlied(a)gmail.com> Cc: Simona Vetter <simona(a)ffwll.ch> Cc: Sumit Semwal <sumit.semwal(a)linaro.org> Cc: "Christian König" <christian.koenig(a)amd.com> Cc: dri-devel(a)lists.freedesktop.org Cc: linux-media(a)vger.kernel.org Cc: linaro-mm-sig(a)lists.linaro.org --- drivers/dma-buf/dma-buf.c | 16 +++++++++++++--- drivers/gpu/drm/drm_gem_shmem_helper.c | 11 ++++++++++- drivers/gpu/drm/drm_prime.c | 2 ++ 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/dma-buf/dma-buf.c b/drivers/dma-buf/dma-buf.c index 2bcf9ceca997..f1e1385ce630 100644 --- a/drivers/dma-buf/dma-buf.c +++ b/drivers/dma-buf/dma-buf.c @@ -1086,7 +1086,8 @@ EXPORT_SYMBOL_NS_GPL(dma_buf_unpin, "DMA_BUF"); * @direction: [in] direction of DMA transfer * * Returns sg_table containing the scatterlist to be returned; returns ERR_PTR - * on error. May return -EINTR if it is interrupted by a signal. + * on error. May return -EINTR if it is interrupted by a signal. Returns NULL + * on success iff direction is DMA_NONE. * * On success, the DMA addresses and lengths in the returned scatterlist are * PAGE_SIZE aligned. @@ -1122,6 +1123,8 @@ struct sg_table *dma_buf_map_attachment(struct dma_buf_attachment *attach, if (ret) return ERR_PTR(ret); } + if (!valid_dma_direction(direction)) + return NULL; /* only pin; don't map */ sg_table = attach->dmabuf->ops->map_dma_buf(attach, direction); if (!sg_table) @@ -1216,14 +1219,21 @@ void dma_buf_unmap_attachment(struct dma_buf_attachment *attach, { might_sleep(); - if (WARN_ON(!attach || !attach->dmabuf || !sg_table)) + if (WARN_ON(!attach || !attach->dmabuf)) return; dma_resv_assert_held(attach->dmabuf->resv); + if (!valid_dma_direction(direction)) + goto unpin; + + if (WARN_ON(!sg_table)) + return; + mangle_sg_table(sg_table); attach->dmabuf->ops->unmap_dma_buf(attach, sg_table, direction); +unpin: if (dma_buf_pin_on_map(attach)) attach->dmabuf->ops->unpin(attach); } @@ -1245,7 +1255,7 @@ void dma_buf_unmap_attachment_unlocked(struct dma_buf_attachment *attach, { might_sleep(); - if (WARN_ON(!attach || !attach->dmabuf || !sg_table)) + if (WARN_ON(!attach || !attach->dmabuf)) return; dma_resv_lock(attach->dmabuf->resv, NULL); diff --git a/drivers/gpu/drm/drm_gem_shmem_helper.c b/drivers/gpu/drm/drm_gem_shmem_helper.c index 5d1349c34afd..1b66501420d3 100644 --- a/drivers/gpu/drm/drm_gem_shmem_helper.c +++ b/drivers/gpu/drm/drm_gem_shmem_helper.c @@ -817,6 +817,7 @@ struct drm_gem_object *drm_gem_shmem_prime_import_no_map(struct drm_device *dev, struct dma_buf *dma_buf) { struct dma_buf_attachment *attach; + struct sg_table *sgt; struct drm_gem_shmem_object *shmem; struct drm_gem_object *obj; size_t size; @@ -838,12 +839,18 @@ struct drm_gem_object *drm_gem_shmem_prime_import_no_map(struct drm_device *dev, get_dma_buf(dma_buf); + sgt = dma_buf_map_attachment_unlocked(attach, DMA_NONE); + if (IS_ERR(sgt)) { + ret = PTR_ERR(sgt); + goto fail_detach; + } + size = PAGE_ALIGN(attach->dmabuf->size); shmem = __drm_gem_shmem_create(dev, size, true, NULL); if (IS_ERR(shmem)) { ret = PTR_ERR(shmem); - goto fail_detach; + goto fail_unmap; } drm_dbg_prime(dev, "size = %zu\n", size); @@ -853,6 +860,8 @@ struct drm_gem_object *drm_gem_shmem_prime_import_no_map(struct drm_device *dev, return &shmem->base; +fail_unmap: + dma_buf_unmap_attachment_unlocked(attach, sgt, DMA_NONE); fail_detach: dma_buf_detach(dma_buf, attach); dma_buf_put(dma_buf); diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index 43a10b4af43a..b3b070868e3b 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -1109,6 +1109,8 @@ void drm_prime_gem_destroy(struct drm_gem_object *obj, struct sg_table *sg) attach = obj->import_attach; if (sg) dma_buf_unmap_attachment_unlocked(attach, sg, DMA_BIDIRECTIONAL); + else + dma_buf_unmap_attachment_unlocked(attach, NULL, DMA_NONE); dma_buf = attach->dmabuf; dma_buf_detach(attach->dmabuf, attach); /* remove the reference */ -- 2.50.1

3 months, 4 weeks

1
2
0 0

[PATCH v2 0/2] accel: Add Arm Ethos-U NPU

by Rob Herring (Arm)

The Arm Ethos-U65/85 NPUs are designed for edge AI inference applications[0]. The driver works with Mesa Teflon. A merge request for Ethos support is here[1]. The UAPI should also be compatible with the downstream (open source) driver stack[2] and Vela compiler though that has not been implemented. Testing so far has been on i.MX93 boards with Ethos-U65. Support for U85 is still todo. Only minor changes on driver side will be needed for U85 support. A git tree is here[3]. Rob [0] https://www.arm.com/products/silicon-ip-cpu?families=ethos%20npus [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36699/ [2] https://gitlab.arm.com/artificial-intelligence/ethos-u/ [3] git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git ethos-v2 Signed-off-by: Rob Herring (Arm) <robh(a)kernel.org> --- Changes in v2: - Rebase on v6.17-rc1 adapting to scheduler changes - scheduler: Drop the reset workqueue. According to the scheduler docs, we don't need it since we have a single h/w queue. - scheduler: Rework the timeout handling to continue running if we are making progress. Fixes timeouts on larger jobs. - Reset the NPU on resume so it's in a known state - Add error handling on clk_get() calls - Fix drm_mm splat on module unload. We were missing a put on the cmdstream BO in the scheduler clean-up. - Fix 0-day report needing explicit bitfield.h include - Link to v1: https://lore.kernel.org/r/20250722-ethos-v1-0-cc1c5a0cbbfb@kernel.org --- Rob Herring (Arm) (2): dt-bindings: npu: Add Arm Ethos-U65/U85 accel: Add Arm Ethos-U NPU driver .../devicetree/bindings/npu/arm,ethos.yaml | 79 +++ MAINTAINERS | 9 + drivers/accel/Kconfig | 1 + drivers/accel/Makefile | 1 + drivers/accel/ethos/Kconfig | 10 + drivers/accel/ethos/Makefile | 4 + drivers/accel/ethos/ethos_device.h | 181 ++++++ drivers/accel/ethos/ethos_drv.c | 418 ++++++++++++ drivers/accel/ethos/ethos_drv.h | 15 + drivers/accel/ethos/ethos_gem.c | 707 +++++++++++++++++++++ drivers/accel/ethos/ethos_gem.h | 46 ++ drivers/accel/ethos/ethos_job.c | 514 +++++++++++++++ drivers/accel/ethos/ethos_job.h | 41 ++ include/uapi/drm/ethos_accel.h | 262 ++++++++ 14 files changed, 2288 insertions(+) --- base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 change-id: 20250715-ethos-3fdd39ef6f19 Best regards, -- Rob Herring (Arm) <robh(a)kernel.org>

4 months

6
11
0 0

Re: [PATCH 4/4] dma-buf/fence-chain: Speed up processing of rearmed callbacks

by Christian König

On 14.08.25 10:16, Janusz Krzysztofik wrote: > When first user starts waiting on a not yet signaled fence of a chain > link, a dma_fence_chain callback is added to a user fence of that link. > When the user fence of that chain link is then signaled, the chain is > traversed in search for a first not signaled link and the callback is > rearmed on a user fence of that link. > > Since chain fences may be exposed to user space, e.g. over drm_syncobj > IOCTLs, users may start waiting on any link of the chain, then many links > of a chain may have signaling enabled and their callbacks added to their > user fences. Once an arbitrary user fence is signaled, all > dma_fence_chain callbacks added to it so far must be rearmed to another > user fence of the chain. In extreme scenarios, when all N links of a > chain are awaited and then signaled in reverse order, the dma_fence_chain > callback may be called up to N * (N + 1) / 2 times (an arithmetic series). > > To avoid that potential excessive accumulation of dma_fence_chain > callbacks, rearm a trimmed-down, signal only callback version to the base > fence of a previous link, if not yet signaled, otherwise just signal the > base fence of the current link instead of traversing the chain in search > for a first not signaled link and moving all callbacks collected so far to > a user fence of that link. Well clear NAK to that! You can easily overflow the kernel stack with that! Additional to this messing with the fence ops outside of the dma_fence code is an absolute no-go. Regards, Christian. > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904 > Suggested-by: Chris Wilson <chris.p.wilson(a)linux.intel.com> > Signed-off-by: Janusz Krzysztofik <janusz.krzysztofik(a)linux.intel.com> > --- > drivers/dma-buf/dma-fence-chain.c | 101 +++++++++++++++++++++++++----- > 1 file changed, 84 insertions(+), 17 deletions(-) > > diff --git a/drivers/dma-buf/dma-fence-chain.c b/drivers/dma-buf/dma-fence-chain.c > index a8a90acf4f34d..90eff264ee05c 100644 > --- a/drivers/dma-buf/dma-fence-chain.c > +++ b/drivers/dma-buf/dma-fence-chain.c > @@ -119,46 +119,113 @@ static const char *dma_fence_chain_get_timeline_name(struct dma_fence *fence) > return "unbound"; > } > > -static void dma_fence_chain_irq_work(struct irq_work *work) > +static void signal_irq_work(struct irq_work *work) > { > struct dma_fence_chain *chain; > > chain = container_of(work, typeof(*chain), work); > > - /* Try to rearm the callback */ > - if (!dma_fence_chain_enable_signaling(&chain->base)) > - /* Ok, we are done. No more unsignaled fences left */ > - dma_fence_signal(&chain->base); > + dma_fence_signal(&chain->base); > dma_fence_put(&chain->base); > } > > -static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb) > +static void signal_cb(struct dma_fence *f, struct dma_fence_cb *cb) > +{ > + struct dma_fence_chain *chain; > + > + chain = container_of(cb, typeof(*chain), cb); > + init_irq_work(&chain->work, signal_irq_work); > + irq_work_queue(&chain->work); > +} > + > +static void rearm_irq_work(struct irq_work *work) > +{ > + struct dma_fence_chain *chain; > + struct dma_fence *prev; > + > + chain = container_of(work, typeof(*chain), work); > + > + rcu_read_lock(); > + prev = rcu_dereference(chain->prev); > + if (prev && dma_fence_add_callback(prev, &chain->cb, signal_cb)) > + prev = NULL; > + rcu_read_unlock(); > + if (prev) > + return; > + > + /* Ok, we are done. No more unsignaled fences left */ > + signal_irq_work(work); > +} > + > +static inline bool fence_is_signaled__nested(struct dma_fence *fence) > +{ > + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) > + return true; > + > + if (fence->ops->signaled && fence->ops->signaled(fence)) { > + unsigned long flags; > + > + spin_lock_irqsave_nested(fence->lock, flags, SINGLE_DEPTH_NESTING); > + dma_fence_signal_locked(fence); > + spin_unlock_irqrestore(fence->lock, flags); > + > + return true; > + } > + > + return false; > +} > + > +static bool prev_is_signaled(struct dma_fence_chain *chain) > +{ > + struct dma_fence *prev; > + bool result; > + > + rcu_read_lock(); > + prev = rcu_dereference(chain->prev); > + result = !prev || fence_is_signaled__nested(prev); > + rcu_read_unlock(); > + > + return result; > +} > + > +static void rearm_or_signal_cb(struct dma_fence *f, struct dma_fence_cb *cb) > { > struct dma_fence_chain *chain; > > chain = container_of(cb, typeof(*chain), cb); > - init_irq_work(&chain->work, dma_fence_chain_irq_work); > + if (prev_is_signaled(chain)) { > + /* Ok, we are done. No more unsignaled fences left */ > + init_irq_work(&chain->work, signal_irq_work); > + } else { > + /* Try to rearm the callback */ > + init_irq_work(&chain->work, rearm_irq_work); > + } > + > irq_work_queue(&chain->work); > - dma_fence_put(f); > } > > static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) > { > struct dma_fence_chain *head = to_dma_fence_chain(fence); > + int err = -ENOENT; > > - dma_fence_get(&head->base); > - dma_fence_chain_for_each(fence, &head->base) { > - struct dma_fence *f = dma_fence_chain_contained(fence); > + if (WARN_ON(!head)) > + return false; > > - dma_fence_get(f); > - if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) { > + dma_fence_get(fence); > + if (head->fence) > + err = dma_fence_add_callback(head->fence, &head->cb, rearm_or_signal_cb); > + if (err) { > + if (prev_is_signaled(head)) { > dma_fence_put(fence); > - return true; > + } else { > + init_irq_work(&head->work, rearm_irq_work); > + irq_work_queue(&head->work); > + err = 0; > } > - dma_fence_put(f); > } > - dma_fence_put(&head->base); > - return false; > + > + return !err; > } > > static bool dma_fence_chain_signaled(struct dma_fence *fence)

4 months

1
0
0 0

Re: [PATCH v7 08/11] tee: add Qualcomm TEE driver

by kernel test robot

Hi Amirreza, kernel test robot noticed the following build warnings: [auto build test WARNING on 2674d1eadaa2fd3a918dfcdb6d0bb49efe8a8bb9] url: https://github.com/intel-lab-lkp/linux/commits/Amirreza-Zarrabi/tee-allow-a… base: 2674d1eadaa2fd3a918dfcdb6d0bb49efe8a8bb9 patch link: https://lore.kernel.org/r/20250812-qcom-tee-using-tee-ss-without-mem-obj-v7… patch subject: [PATCH v7 08/11] tee: add Qualcomm TEE driver config: hexagon-randconfig-r072-20250814 (https://download.01.org/0day-ci/archive/20250814/202508140527.ighXikjo-lkp@…) compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 3769ce013be2879bf0b329c14a16f5cb766f26ce) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250814/202508140527.ighXikjo-lkp@…) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp(a)intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202508140527.ighXikjo-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/tee/qcomtee/user_obj.c:384:12: warning: format specifies type 'unsigned long' but the argument has type 'u64' (aka 'unsigned long long') [-Wformat] 383 | &qcomtee_user_object_ops, "uo-%lu", | ~~~ | %llu 384 | param->u.objref.id); | ^~~~~~~~~~~~~~~~~~ 1 warning generated. vim +384 drivers/tee/qcomtee/user_obj.c 355 356 /** 357 * qcomtee_user_param_to_object() - OBJREF parameter to &struct qcomtee_object. 358 * @object: object returned. 359 * @param: TEE parameter. 360 * @ctx: context in which the conversion should happen. 361 * 362 * @param is an OBJREF with %QCOMTEE_OBJREF_FLAG_USER flags. 363 * 364 * Return: On success, returns 0; on failure, returns < 0. 365 */ 366 int qcomtee_user_param_to_object(struct qcomtee_object **object, 367 struct tee_param *param, 368 struct tee_context *ctx) 369 { 370 struct qcomtee_user_object *user_object __free(kfree) = NULL; 371 int err; 372 373 user_object = kzalloc(sizeof(*user_object), GFP_KERNEL); 374 if (!user_object) 375 return -ENOMEM; 376 377 user_object->ctx = ctx; 378 user_object->object_id = param->u.objref.id; 379 /* By default, always notify userspace upon release. */ 380 user_object->notify = true; 381 err = qcomtee_object_user_init(&user_object->object, 382 QCOMTEE_OBJECT_TYPE_CB, 383 &qcomtee_user_object_ops, "uo-%lu", > 384 param->u.objref.id); 385 if (err) 386 return err; 387 /* Matching teedev_ctx_put() is in qcomtee_user_object_release(). */ 388 teedev_ctx_get(ctx); 389 390 *object = &no_free_ptr(user_object)->object; 391 392 return 0; 393 } 394 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki

4 months

1
0
0 0

Re: [PATCH v7 00/11] Trusted Execution Environment (TEE) driver for Qualcomm TEE (QTEE)

by Jens Wiklander

Hi Amir, On Wed, Aug 13, 2025 at 2:37 AM Amirreza Zarrabi <amirreza.zarrabi(a)oss.qualcomm.com> wrote: > > This patch series introduces a Trusted Execution Environment (TEE) > driver for Qualcomm TEE (QTEE). QTEE enables Trusted Applications (TAs) > and services to run securely. It uses an object-based interface, where > each service is an object with sets of operations. Clients can invoke > these operations on objects, which can generate results, including other > objects. For example, an object can load a TA and return another object > that represents the loaded TA, allowing access to its services. > There are some build errors/warnings for arm and x86_64, see https://tuxapi.tuxsuite.com/v1/groups/linaro/projects/jens/plans/31DmCOn1pF… Thanks, Jens

4 months

1
0
0 0

Re: [PATCH v6 2/2] i2c: i2c-qcom-geni: Add Block event interrupt support

by Vinod Koul

On 25-07-25, 16:20, Jyothi Kumar Seerapu wrote: > > > On 7/23/2025 12:45 PM, Vinod Koul wrote: > > On 22-07-25, 15:46, Dmitry Baryshkov wrote: > > > On Tue, Jul 22, 2025 at 05:50:08PM +0530, Jyothi Kumar Seerapu wrote: > > > > On 7/19/2025 3:27 PM, Dmitry Baryshkov wrote: > > > > > On Mon, Jul 07, 2025 at 09:58:30PM +0530, Jyothi Kumar Seerapu wrote: > > > > > > On 7/4/2025 1:11 AM, Dmitry Baryshkov wrote: > > > > > > > On Thu, 3 Jul 2025 at 15:51, Jyothi Kumar Seerapu > > > > [Folks, would be nice to trim replies] > > > > > > > > Could you please confirm if can go with the similar approach of unmap the > > > > > > processed TREs based on a fixed threshold or constant value, instead of > > > > > > unmapping them all at once? > > > > > > > > > > I'd still say, that's a bad idea. Please stay within the boundaries of > > > > > the DMA API. > > > > > > > > > I agree with the approach you suggested—it's the GPI's responsibility to > > > > manage the available TREs. > > > > > > > > However, I'm curious whether can we set a dynamic watermark value perhaps > > > > half the available TREs) to trigger unmapping of processed TREs ? This would > > > > allow the software to prepare the next set of TREs while the hardware > > > > continues processing the remaining ones, enabling better parallelism and > > > > throughput. > > > > > > Let's land the simple implementation first, which can then be improved. > > > However I don't see any way to return 'above the watermark' from the DMA > > > controller. You might need to enhance the API. > > > > Traditionally, we set the dma transfers for watermark level and we get a > > interrupt. So you might want to set the callback for watermark level > > and then do mapping/unmapping etc in the callback. This is typical model > > for dmaengines, we should follow that well > > > > BR > > Thanks Dmitry and Vinod, I will work on V7 patch for submitting the I2C > messages until they fit and and unmap all processed messages together for > now. > > Regarding the watermark mechanism, looks GENI SE DMA supports watermark > interrupts but it appears that GPI DMA doesn't have such provision of > watermark. What is the mechanism to get interrupts from the GPI? If you submit 10 txn, can you ask it to interrupt when half of them are done? -- ~Vinod

4 months

1
0
0 0

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

Linaro-mm-sig