Linaro-mm-sig November 2025

linaro-mm-sig@lists.linaro.org

19 participants
100 discussions

Re: [PATCH v2 19/21] scsi: fnic: Switch to use %ptS

by Martin K. Petersen

Andy, > Use %ptS instead of open coded variants to print content of > struct timespec64 in human readable format. Reviewed-by: Martin K. Petersen <martin.petersen(a)oracle.com> -- Martin K. Petersen

2 weeks, 4 days

Re: [PATCH v2 20/21] scsi: snic: Switch to use %ptSp

by Martin K. Petersen

Andy, > Use %ptSp instead of open coded variants to print content of > struct timespec64 in human readable format. Reviewed-by: Martin K. Petersen <martin.petersen(a)oracle.com> -- Martin K. Petersen

2 weeks, 4 days

Re: [PATCH net-next v2 4/7] net: ethernet: ti: am65-cpsw: Add AF_XDP zero copy for RX

by Jakub Kicinski

On Sun, 09 Nov 2025 23:37:54 +0200 Roger Quadros wrote: > + ndev->stats.rx_dropped++; AFAIU the device is multi-queue so using per-device stats looks racy. Please create your own per queue stats.

2 weeks, 5 days

Re: [PATCH net-next v2 7/7] net: ethernet: ti: am65-cpsw: Fix clearing of irq_disabled flag in rx_poll

by Jakub Kicinski

On Sun, 09 Nov 2025 23:37:57 +0200 Roger Quadros wrote: > In am65_cpsw_nuss_rx_poll() there is a possibility that irq_disabled flag > is cleared but the IRQ is not enabled. > > This patch fixes by that by clearing irq_disabled flag right when enabling > the irq. > > Fixes: da70d184a8c3 ("net: ethernet: ti: am65-cpsw: Introduce multi queue Rx") > Signed-off-by: Roger Quadros <rogerq(a)kernel.org> This looks independent from the series, it needs to go to net. -- pw-bot: cr

2 weeks, 5 days

Re: [PATCH net-next v2 0/7] net: ethernet: ti: am65-cpsw: add AF_XDP zero copy support

by Jakub Kicinski

On Sun, 09 Nov 2025 23:37:50 +0200 Roger Quadros wrote: > This series adds AF_XDP zero coppy support to am65-cpsw driver. > > Tests were performed on AM62x-sk with xdpsock application [1]. > > A clear improvement is seen in 64 byte packets on Transmit (txonly) > and receive (rxdrop). > 1500 byte test seems to be limited by line rate (1G link) so no > improvement seen there in packet rate. A test on higher speed link > (or PHY-less setup) might be worthwile. > > There is some issue during l2fwd with 64 byte packets and benchmark > results show 0. This issue needs to be debugged further. > A 512 byte l2fwd test result has been added to compare instead. It appears that the drivers/net/ethernet/ti/am65-* files do not fall under any MAINTAINERS entry. Please add one or extend the existing CPSW entry as the first patch of the series.

2 weeks, 5 days

Re: [PATCH v2 04/21] dma-buf: Switch to use %ptSp

by Sumit Semwal

Hello Andy, On Tue, 11 Nov 2025 at 17:57, Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> wrote: > > Use %ptSp instead of open coded variants to print content of > struct timespec64 in human readable format. > > Reviewed-by: Christian König <christian.koenig(a)amd.com> > Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> Thanks for the patch. FWIW, please feel free to add Acked-by: Sumit Semwal <sumit.semwal(a)linaro.org> Best, Sumit. > --- > drivers/dma-buf/sync_debug.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/dma-buf/sync_debug.c b/drivers/dma-buf/sync_debug.c > index 67cd69551e42..9e5d662cd4e8 100644 > --- a/drivers/dma-buf/sync_debug.c > +++ b/drivers/dma-buf/sync_debug.c > @@ -59,7 +59,7 @@ static void sync_print_fence(struct seq_file *s, > struct timespec64 ts64 = > ktime_to_timespec64(fence->timestamp); > > - seq_printf(s, "@%lld.%09ld", (s64)ts64.tv_sec, ts64.tv_nsec); > + seq_printf(s, "@%ptSp", &ts64); > } > > seq_printf(s, ": %lld", fence->seqno); > -- > 2.50.1 >

2 weeks, 5 days

Re: [PATCH v7 00/11] vfio/pci: Allow MMIO regions to be exported through dma-buf

by Christian König

On 11/10/25 21:42, Alex Williamson wrote: > On Thu, 6 Nov 2025 16:16:45 +0200 > Leon Romanovsky <leon(a)kernel.org> wrote: > >> Changelog: >> v7: >> * Dropped restore_revoke flag and added vfio_pci_dma_buf_move >> to reverse loop. >> * Fixed spelling errors in documentation patch. >> * Rebased on top of v6.18-rc3. >> * Added include to stddef.h to vfio.h, to keep uapi header file independent. > > I think we're winding down on review comments. It'd be great to get > p2pdma and dma-buf acks on this series. Otherwise it's been posted > enough that we'll assume no objections. Thanks, Already have it on my TODO list to take a closer look, but no idea when that will be. This patch set is on place 4 or 5 on a rather long list of stuff to review/finish. Christian. > > Alex

2 weeks, 5 days

Re: [PATCH v1 12/23] ipmi: Switch to use %ptSp

by Sergey Senozhatsky

On (25/11/10 19:40), Andy Shevchenko wrote: [..] > + dev_dbg(smi_info->io.dev, "**%s: %ptSp\n", msg, &t); Strictly speaking, this is not exactly equivalent to %lld.%9.9ld or %lld.%6.6ld but I don't know if that's of any importance.

2 weeks, 5 days

Re: [PATCH v7 11/11] vfio/nvgrace: Support get_dmabuf_phys

by Leon Romanovsky

On Mon, Nov 10, 2025 at 01:05:34PM -0700, Alex Williamson wrote: > On Thu, 6 Nov 2025 16:16:56 +0200 > Leon Romanovsky <leon(a)kernel.org> wrote: > > > From: Jason Gunthorpe <jgg(a)nvidia.com> > > > > Call vfio_pci_core_fill_phys_vec() with the proper physical ranges for the > > synthetic BAR 2 and BAR 4 regions. Otherwise use the normal flow based on > > the PCI bar. > > > > This demonstrates a DMABUF that follows the region info report to only > > allow mapping parts of the region that are mmapable. Since the BAR is > > power of two sized and the "CXL" region is just page aligned the there can > > be a padding region at the end that is not mmaped or passed into the > > DMABUF. > > > > The "CXL" ranges that are remapped into BAR 2 and BAR 4 areas are not PCI > > MMIO, they actually run over the CXL-like coherent interconnect and for > > the purposes of DMA behave identically to DRAM. We don't try to model this > > distinction between true PCI BAR memory that takes a real PCI path and the > > "CXL" memory that takes a different path in the p2p framework for now. > > > > Signed-off-by: Jason Gunthorpe <jgg(a)nvidia.com> > > Tested-by: Alex Mastro <amastro(a)fb.com> > > Tested-by: Nicolin Chen <nicolinc(a)nvidia.com> > > Signed-off-by: Leon Romanovsky <leonro(a)nvidia.com> > > --- > > drivers/vfio/pci/nvgrace-gpu/main.c | 56 +++++++++++++++++++++++++++++++++++++ > > 1 file changed, 56 insertions(+) > > > > diff --git a/drivers/vfio/pci/nvgrace-gpu/main.c b/drivers/vfio/pci/nvgrace-gpu/main.c > > index e346392b72f6..7d7ab2c84018 100644 > > --- a/drivers/vfio/pci/nvgrace-gpu/main.c > > +++ b/drivers/vfio/pci/nvgrace-gpu/main.c > > @@ -7,6 +7,7 @@ > > #include <linux/vfio_pci_core.h> > > #include <linux/delay.h> > > #include <linux/jiffies.h> > > +#include <linux/pci-p2pdma.h> > > > > /* > > * The device memory usable to the workloads running in the VM is cached > > @@ -683,6 +684,54 @@ nvgrace_gpu_write(struct vfio_device *core_vdev, > > return vfio_pci_core_write(core_vdev, buf, count, ppos); > > } > > > > +static int nvgrace_get_dmabuf_phys(struct vfio_pci_core_device *core_vdev, > > + struct p2pdma_provider **provider, > > + unsigned int region_index, > > + struct dma_buf_phys_vec *phys_vec, > > + struct vfio_region_dma_range *dma_ranges, > > + size_t nr_ranges) > > +{ > > + struct nvgrace_gpu_pci_core_device *nvdev = container_of( > > + core_vdev, struct nvgrace_gpu_pci_core_device, core_device); > > + struct pci_dev *pdev = core_vdev->pdev; > > + > > + if (nvdev->resmem.memlength && region_index == RESMEM_REGION_INDEX) { > > + /* > > + * The P2P properties of the non-BAR memory is the same as the > > + * BAR memory, so just use the provider for index 0. Someday > > + * when CXL gets P2P support we could create CXLish providers > > + * for the non-BAR memory. > > + */ > > + *provider = pcim_p2pdma_provider(pdev, 0); > > + if (!*provider) > > + return -EINVAL; > > + return vfio_pci_core_fill_phys_vec(phys_vec, dma_ranges, > > + nr_ranges, > > + nvdev->resmem.memphys, > > + nvdev->resmem.memlength); > > + } else if (region_index == USEMEM_REGION_INDEX) { > > + /* > > + * This is actually cachable memory and isn't treated as P2P in > > + * the chip. For now we have no way to push cachable memory > > + * through everything and the Grace HW doesn't care what caching > > + * attribute is programmed into the SMMU. So use BAR 0. > > + */ > > + *provider = pcim_p2pdma_provider(pdev, 0); > > + if (!*provider) > > + return -EINVAL; > > + return vfio_pci_core_fill_phys_vec(phys_vec, dma_ranges, > > + nr_ranges, > > + nvdev->usemem.memphys, > > + nvdev->usemem.memlength); > > + } > > + return vfio_pci_core_get_dmabuf_phys(core_vdev, provider, region_index, > > + phys_vec, dma_ranges, nr_ranges); > > +} > > > Unless my eyes deceive, we could reduce the redundancy a bit: > > struct mem_region *mem_region = NULL; > > if (nvdev->resmem.memlength && region_index == RESMEM_REGION_INDEX) { > /* > * The P2P properties of the non-BAR memory is the same as the > * BAR memory, so just use the provider for index 0. Someday > * when CXL gets P2P support we could create CXLish providers > * for the non-BAR memory. > */ > mem_region = &nvdev->resmem; > } else if (region_index == USEMEM_REGION_INDEX) { > /* > * This is actually cachable memory and isn't treated as P2P in > * the chip. For now we have no way to push cachable memory > * through everything and the Grace HW doesn't care what caching > * attribute is programmed into the SMMU. So use BAR 0. > */ > mem_region = &nvdev->usemem; > } > > if (mem_region) { > *provider = pcim_p2pdma_provider(pdev, 0); > if (!*provider) > return -EINVAL; > return vfio_pci_core_fill_phys_vec(phys_vec, dma_ranges, > nr_ranges, > mem_region->memphys, > mem_region->memlength); > } > > return vfio_pci_core_get_dmabuf_phys(core_vdev, provider, region_index, > phys_vec, dma_ranges, nr_ranges); Yes, this will work too. Thanks > > Thanks, > Alex

2 weeks, 6 days

Re: [PATCH v1 23/23] tracing: Switch to use %ptSp

by Steven Rostedt

On Mon, 10 Nov 2025 19:40:42 +0100 Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> wrote: > Use %ptSp instead of open coded variants to print content of > struct timespec64 in human readable format. > > Signed-off-by: Andy Shevchenko <andriy.shevchenko(a)linux.intel.com> > --- > kernel/trace/trace_output.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Acked-by: Steven Rostedt (Google) <rostedt(a)goodmis.org> -- Steve

2 weeks, 6 days

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Linaro-mm-sig November 2025